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| ? 2006 microchip technology inc. advance information ds39762a pic18f97j60 family data sheet 64/80/100-pin, high-performance, 1 mbit flash microcontrollers with ethernet
ds39762a-page ii advance information ? 2006 microchip technology inc. information contained in this publication regarding device applications and the like is provi ded only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or war- ranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, accuron, dspic, k ee l oq , micro id , mplab, pic, picmicro, picstart, pro mate, powersmart, rfpic and smartshunt are registered trademarks of micr ochip technology incorporated in the u.s.a. and other countries. amplab, filterlab, migratable memory, mxdev, mxlab, seeval, smartsensor and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, dspicdem, dspicdem.net, dspicworks, ecan, economonitor, fansense, flexrom, fuzzylab, in-circuit serial programming, icsp, icepic, linear active thermistor, mpasm, mplib, mplink, mpsim, pickit, picdem, picdem.net, piclab, pictail, powercal, powerinfo, powermate, powertool, real ice, rflab, rfpicdem, select mode, smart serial, smarttel, total endurance, uni/o, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2006, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona and mountain view, california in october 2003. the company?s quality system processes and procedures are for its picmicro ? 8-bit mcus, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. ? 2006 microchip technology inc. advance information ds39762a-page 1 pic18f97j60 family ethernet features: ? ieee 802.3 compatible ethernet controller ? integrated mac and 10base-t phy ? 8-kbyte transmit/receive packet buffer sram ? supports one 10base-t port with automatic polarity detection and correction ? programmable automatic retransmit on collision ? programmable padding and crc generation ? programmable automatic rejection of erroneous packets ? activity outputs for 2 led indicators ?buffer: - configurable transmit/receive buffer size - hardware-managed circular receive fifo - byte-wide random and sequential access - internal dma for fast memory copying - hardware assisted checksum calculation for various protocols ?mac: - support for unicast, multicast and broadcast packets - programmable pattern match of up to 64 bytes within packet at user-defined offset - programmable wake-up on multiple packet formats ?phy: - wave shaping output filter - loopback mode flexible oscillator structure: ? selectable system clock derived from single 25 mhz external source: - 2.78 to 41.67 mhz ? internal 31 khz oscillator ? secondary oscillator using timer1 @ 32 khz ? fail-safe clock monitor: - allows for safe shutdown if oscillator stops ? two-speed oscillator start-up external memory bus (100-pin devices only): ? address capability of up to 2 mbytes ? 8-bit or 16-bit interface ? 12-bit, 16-bit and 20-bit addressing modes peripheral highlights: ? high-current sink/source: 25 ma/25 ma on portb and portc ? five timer modules (timer0 to timer4) ? four external interrupt pins ? two capture/compare/pwm (ccp) modules ? three enhanced capture/compare/pwm (eccp) modules: - one, two or four pwm outputs - selectable polarity - programmable dead time - auto-shutdown and auto-restart ? up to two master synchronous serial port (mssp) modules supporting spi (all 4 modes) and i 2 c? master and slave modes ? up to two enhanced usart modules: - supports rs-485, rs-232 and lin 1.2 - auto-wake-up on start bit - auto-baud detect ? 10-bit, up to 16-channel analog-to-digital converter module (a/d): - auto-acquisition capability - conversion available during sleep ? dual analog comparators with input multiplexing ? parallel slave port (psp) module (100-pin devices only) special microcontroller features: ? 5.5v tolerant inputs (digital-only pins) ? low-power, high-speed cmos flash technology: - self-reprogrammable under software control ? c compiler optimized architecture for re-entrant code ? power management features: - run: cpu on, peripherals on - idle: cpu off, peripherals on - sleep: cpu off, peripherals off ? priority levels for interrupts ? 8 x 8 single-cycle hardware multiplier ? extended watchdog timer (wdt): - programmable period from 4 ms to 134s ? single-supply 3.3v in-circuit serial programming? (icsp?) via two pins ? in-circuit debug (icd) with 3 breakpoints via two pins ? operating voltage range of 2.35v to 3.6v (3.14v to 3.45v using ethernet module) ? on-chip 2.5v regulator 64/80/100-pin, high-performance, 1-mbit flash microcontrollers with ethernet pic18f97j60 family ds39762a-page 2 advance information ? 2006 microchip technology inc. pin diagrams device flash program memory (bytes) sram data memory (bytes) ethernet tx/rx buffer (bytes) i/o 10-bit a/d (ch) ccp/ eccp mssp eusart comparators timers 8/16-bit psp external memory bus spi master i 2 c? pic18f66j60 64k 3808 8192 39 11 2/3 1 y y 1 2 2/3 n n pic18f66j65 96k 3808 8192 39 11 2/3 1 y y 1 2 2/3 n n pic18f67j60 128k 3808 8192 39 11 2/3 1 y y 1 2 2/3 n n PIC18F86J60 64k 3808 8192 55 15 2/3 1 y y 2 2 2/3 n n pic18f86j65 96k 3808 8192 55 15 2/3 1 y y 2 2 2/3 n n pic18f87j60 128k 3808 8192 55 15 2/3 1 y y 2 2 2/3 n n pic18f96j60 64k 3808 8192 70 16 2/3 2 y y 2 2 2/3 y y pic18f96j65 96k 3808 8192 70 16 2/3 2 y y 2 2 2/3 y y pic18f97j60 128k 3808 8192 70 16 2/3 2 y y 2 2 2/3 y y pic18f66j65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 38 37 36 35 34 33 50 49 17 18 19 20 21 22 23 24 25 26 v dd mclr v ss v ddcore /v cap osc2/clko osc1/clki 15 16 31 40 39 27 28 29 30 32 48 47 46 45 44 43 42 41 54 53 52 51 58 57 56 55 60 59 64 63 62 61 64-pin tqfp rb4/kbi0 rb5/kbi1 rb6/kbi2/pgc v ss v dd rb7/kbi3/pgd rc4/sdi1/sda1 rc3/sck1/scl1 rc2/eccp1/p1a rc5/sdo1 v ddrx tpin+ tpin- v ssrx re2/p2b re3/p3c re4/p3b re5/p1c rd0/p1b rd1/eccp3/p3a rd2/ccp4/p3d v sspll v ddpll rbias v sstx tpout+ tpout- v ddtx v ss re1/p2c re0/p2d rg4/ccp5/p1d rf7/ss1 rb0/int0/flt0 rb1/int1 rb2/int2 rb3/int3 rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rf6/an11 envreg rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/ledb/an1 ra0/leda/an0 v ss v dd ra4/t0cki ra5/an4 rc1/t1osi/eccp2/p2a rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 pic18f67j60 pic18f66j60 ? 2006 microchip technology inc. advance information ds39762a-page 3 pic18f97j60 family pin diagrams (continued) pic18f86j65 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 re2/p2b re3/p3c (2) re4/p3b (2) re5/p1c (2) re6/p1b (2) re7/eccp2 (1) /p2a (1) rd0 v dd v ss rd1 rd2 re1/p2c re0/p2d rg0/eccp3/p3a rg1/tx2/ck2 rg2/rx2/dt2 rg3/ccp4/p3d mclr rg4/ccp5/p1d v ss v ddcore /v cap rf7/ss1 rb0/int0/flt0 rb1/int1 rb2/int2 rb3/int3 rb4/kbi0 rb5/kbi1 rb6/kbi2/pgc v ss osc2/clko osc1/clki v dd rb7/kbi3/pgd rc4/sdi1/sda1 rc3/sck1/scl1 rc2/eccp1/p1a envreg rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/ledb/an1 ra0/leda/an0 v ss v dd ra4/t0cki ra5/an4 rc1/t1osi/eccp2 (1) /p2a (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rc5/sdo1 rh1 rh0 1 2 rh2 rh3 17 18 rh7/an15/p1b (2) rh6/an14/p1c (2) rh5/an13/p3b (2) rh4/an12/p3c (2) rj5 rj4 37 50 49 19 20 33 34 35 36 38 58 57 56 55 54 53 52 51 60 59 68 67 66 65 72 71 70 69 74 73 78 77 76 75 79 80 80-pin tqfp pinouts are preliminary and subject to change. note 1: the eccp2/p2a pin placement depends on the ccp2mx configuration bit setting. 2: p1b, p1c, p3b and p3c pin placement depends on the eccpmx configuration bit setting. rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rf6/an11 v sspll v ddpll rbias v sstx tpout+ tpout- v ddtx v ddrx tpin+ tpin- v ssrx pic18f87j60 PIC18F86J60 pic18f97j60 family ds39762a-page 4 advance information ? 2006 microchip technology inc. pin diagrams (continued) 92 94 93 91 90 89 88 87 86 85 84 83 82 81 80 79 78 20 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 65 64 63 62 61 60 59 26 56 45 44 43 42 41 40 39 28 29 30 31 32 33 34 35 36 37 38 17 18 19 21 22 95 1 76 77 72 71 70 69 68 67 66 75 74 73 58 57 24 23 25 96 98 97 99 27 46 47 48 49 50 55 54 53 52 51 100 100-pin tqfp rb0/int0/flt0 rb1/int1 rb2/int2 rb3/int3/eccp2 (1) /p2a (1) rb4/kbi0 rb5/kbi1 rb6/kbi2/pgc v ss osc2/clko osc1/clki v dd rb7/kbi3/pgd rc4/sdi1/sda1 rc3/sck1/scl1 rc2/eccp1/p1a rc5/sdo1 rj7/ub rj6/lb rj2/wrl rj3/wrh re1/ad9/wr /p2c re0/ad8/rd /p2d rg0/eccp3/p3a rg1/tx2/ck2 rg2/rx2/dt2 rg3/ccp4/p3d mclr rg4/ccp5/p1d v ss v ddcore /v cap rf7/ss1 rh2/a18 rh3/a19 rh7/an15/p1b (2) rh6/an14/p1c (2) rf5/an10/cv ref rf4/an9 rf3/an8 rf2/an7/c1out rf6/an11 re2/ad10/cs /p2b re3/ad11/p3c (2) re4/ad12/p3b (2) re5/ad13/p1c (2) re6/ad14/p1b (2) re7/ad15/eccp2 (1) /p2a (1) rd0/ad0/psp0 v dd v ss rd1/ad1/psp1 rd2/ad2/psp2 rd3/ad3/psp3 rd4/ad4/psp4/sdo2 rd5/ad5/psp5/sdi2/sda2 rd6/ad6/psp6/sck2/scl2 rj0/ale rj1/oe rh1/a17 rh0/a16 envreg rf1/an6/c2out av dd av ss ra3/an3/v ref + ra2/an2/v ref - ra1/ledb/an1 ra0/leda/an0 v ss v dd ra4/t0cki ra5/an4 rc1/t1osi/eccp2 (1) /p2a (1) rc0/t1oso/t13cki rc7/rx1/dt1 rc6/tx1/ck1 rh5/an13/p3b (2) rh4/an12/p3c (2) rj5/ce rj4/ba0 v ss v sspll v ddpll rbias v sstx tpout+ tpout- v ddtx v ddrx tpin+ tpin- v ssrx rg6 rg5 rf0/an5 v dd rg7 v ss rd7/ad7/psp7/ss2 v dd pic18f96j65 pic18f97j60 pinouts are preliminary and subject to change. note 1: the eccp2/p2a pin placement depends on the ccp2mx configuration bit and processor mode settings. 2: p1b, p1c, p3b and p3c pin placement depends on the eccpmx configuration bit setting. nc pic18f96j60 ? 2006 microchip technology inc. advance information ds39762a-page 5 pic18f97j60 family table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 oscillator configurations ..................................... .............................................................. ......................................................... 39 3.0 power-managed modes ......................................................................................................... .................................................... 45 4.0 reset ....................................................................................................................... ................................................................... 53 5.0 memory organization ......................................................................................................... ........................................................ 67 6.0 flash program memory........................................................................................................ ...................................................... 95 7.0 external memory bus ......................................................................................................... ...................................................... 105 8.0 8 x 8 hardware multiplier................................................................................................... ....................................................... 117 9.0 interrupts .................................................................................................................. ................................................................ 119 10.0 i/o ports .................................................................................................................. ................................................................. 135 11.0 timer0 module .............................................................................................................. ........................................................... 163 12.0 timer1 module .............................................................................................................. ........................................................... 167 13.0 timer2 module .............................................................................................................. ........................................................... 173 14.0 timer3 module .............................................................................................................. ........................................................... 175 15.0 timer4 module .............................................................................................................. ........................................................... 179 16.0 capture/compare/pwm (ccp) modules .......................................................................................... ....................................... 181 17.0 enhanced capture/compare/pwm (eccp) module................................................................................. ............................... 189 18.0 ethernet module ............................................................................................................ ........................................................... 205 19.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 255 20.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) .................................................. ............. 301 21.0 10-bit analog-to-digital converter (a/d) module ............................................................................ ......................................... 325 22.0 comparator module.......................................................................................................... ........................................................ 335 23.0 comparator voltage reference module........................................................................................ ........................................... 341 24.0 special features of the cpu................................................................................................ .................................................... 345 25.0 instruction set summary .................................................................................................... ...................................................... 359 26.0 development support........................................................................................................ ....................................................... 409 27.0 electrical characteristics ................................................................................................. ......................................................... 413 28.0 dc and ac characteristics graphs and tables................................................................................ ....................................... 449 29.0 packaging information...................................................................................................... ........................................................ 451 appendix a: revision history................................................................................................... .......................................................... 455 appendix b: device differences ................................................................................................. ....................................................... 455 index .......................................................................................................................... ........................................................................ 457 the microchip web site ......................................................................................................... ............................................................ 469 customer change notification service ........................................................................................... ................................................... 469 customer support............................................................................................................... ............................................................... 469 reader response ................................................................................................................ .............................................................. 470 product identification system .................................................................................................. .......................................................... 471 pic18f97j60 family ds39762a-page 6 advance information ? 2006 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/doc umentation issues become known to us, we will publis h an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particul ar device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please spec ify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. ? 2006 microchip technology inc. advance information ds39762a-page 7 pic18f97j60 family 1.0 device overview this document contains device-specific information for the following devices: this family introduces a new line of low-voltage devices with the foremost traditional advantage of all pic18 microcontrollers ? namely, high computational per- formance and a rich feature set at an extremely competitive price point. these features make the pic18f97j60 family a logical choice for many high-performance applications where cost is a primary consideration. 1.1 core features 1.1.1 nanowatt technology all of the devices in the pic18f97j60 family incorporate a range of features that c an significantly reduce power consumption during operation. key items include: ? alternate run modes: by clocking the controller from the timer1 source or the internal rc oscillator, power consumption during code execution can be reduced by as much as 90%. ? multiple idle modes: the controller can also run with its cpu core disabled but the peripherals still active. in these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. ? on-the-fly mode switching: the power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application?s software design. 1.1.2 oscillator options and features all of the devices in the pic18f97j60 family offer five different oscillator options, allowing users a range of choices in developing application hardware. these options include: ? two crystal modes, using crystals or ceramic resonators. ? two external clock modes, offering the option of a divide-by-4 clock output. ? a phase lock loop (pll) frequency multiplier, available to the external oscillator modes, which allows clock speeds of up to 41.67 mhz. ? an internal rc oscillator with a fixed 31 khz output which provides an extremely low-power option for timing-insensitive applications. the internal oscillator block provides a stable reference source that gives the family additional features for robust operation: ? fail-safe clock monitor: this option constantly monitors the main clock source against a reference signal provided by the internal oscillator. if a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. ? two-speed start-up: this option allows the internal oscillator to serve as the clock source from power-on reset, or wake-up from sleep mode, until the primary clock source is available. 1.1.3 expanded memory the pic18f97j60 family provides ample room for application code, from 64 kbytes to 128 kbytes of code space. the flash cells for program memory are rated to last up to 100 erase/write cycles. data retention without refresh is conservatively estimated to be greater than 20 years. the pic18f97j60 family also provides plenty of room for dynamic application data with 3808 bytes of data ram. 1.1.4 external memory bus in the unlikely event that 128 kbytes of memory are inadequate for an application, the 100-pin members of the pic18f97j60 family also implement an external memory bus. this allows the controller?s internal program counter to address a memory space of up to 2 mbytes, permitting a level of data access that few 8-bit devices can claim. this allows additional memory options, including: ? using combinations of on-chip and external memory up to the 2-mbyte limit ? using external flash memory for reprogrammable application code or large data tables ? using external ram devices for storing large amounts of variable data 1.1.5 extended instruction set the pic18f97j60 family implements the optional extension to the pic18 instruction set, adding eight new instructions and an indexed addressing mode. enabled as a device configuration option, the extension has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as c. 1.1.6 easy migration regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. ? pic18f66j60 ? pic18f87j60 ? pic18f66j65 ? pic18f96j60 ? pic18f67j60 ? pic18f96j65 ? PIC18F86J60 ? pic18f97j60 ? pic18f86j65 pic18f97j60 family ds39762a-page 8 advance information ? 2006 microchip technology inc. 1.2 other special features ? communications: the pic18f97j60 family incorporates a range of serial communication peripherals, including up to two independent enhanced usarts and up to two master ssp modules, capable of both spi and i 2 c? (master and slave) modes of operation. in addition, one of the general purpose i/o ports can be reconfigured as an 8-bit parallel slave port for direct processor-to-processor communications. ? ccp modules: all devices in the family incorporate two capture/compare/pwm (ccp) modules and three enhanced ccp (eccp) modules to maximize flexibility in control applications. up to four different time bases may be used to perform several different operations at once. each of the three eccp modules offers up to four pwm outputs, allowing for a total of twelve pwms. the eccp modules also offer many beneficial features, including polarity selection, programmable dead time, auto-shutdown and restart and half-bridge and full-bridge output modes. ? 10-bit a/d converter: this module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reducing code overhead. ? extended watchdog timer (wdt): this enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. see section 27.0 ?electrical characteristics? for time-out periods. 1.3 details on individual family members devices in the pic18f97j60 family are available in 64-pin, 80-pin and 100-pin packages. block diagrams for the three groups are shown in figure 1-1, figure 1-2 and figure 1-3. the devices are differentiated from each other in four ways: 1. flash program memory (three sizes, ranging from 64 kbytes for pic18fx6j60 devices to 128 kbytes for pic18fx7j60 devices). 2. a/d channels (eleven for 64-pin devices, fifteen for 80-pin pin devices and sixteen for 100-pin devices). 3. serial communication modules (one eusart module and one mssp module on 64-pin devices, two eusart modules and one mssp module on 80-pin devices and two eusart modules and two mssp modules on 100-pin devices 4. i/o pins (39 on 64-pin devices, 55 on 80-pin devices and 70 on 100-pin devices). all other features for devices in this family are identical. these are summarized in table 1-1, table 1-2 and table 1-3. the pinouts for all devices are listed in table 1-4, table 1-5 and table 1-6. ? 2006 microchip technology inc. advance information ds39762a-page 9 pic18f97j60 family table 1-1: device features for the pic18f97j60 family (64-pin devices) table 1-2: device features for the pic18f97j60 family (80-pin devices) features pic18f66j60 pic18f66j65 pic18f67j60 operating frequency dc ? 41.67 mhz dc ? 41.67 mhz dc ? 41.67 mhz program memory (bytes) 64k 96k 128k program memory (instructions) 32764 49148 65532 data memory (bytes) 3808 interrupt sources 26 i/o ports ports a, b, c, d, e, f, g i/o pins 39 timers 5 capture/compare/pwm modules 2 enhanced capture/compare/pwm modules 3 serial communications mssp (1), enhanced usart (1) ethernet communications (10base-t) yes parallel slave port communications (psp) no external memory bus no 10-bit analog-to-digital module 11 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow, mclr , wdt (pwrt, ost) instruction set 75 instructions, 83 with extended instruction set enabled packages 64-pin tqfp features PIC18F86J60 pic18f86j65 pic18f87j60 operating frequency dc ? 41.67 mhz dc ? 41.67 mhz dc ? 41.67 mhz program memory (bytes) 64k 96k 128k program memory (instructions) 32764 49148 65532 data memory (bytes) 3808 interrupt sources 27 i/o ports ports a, b, c, d, e, f, g, h, j i/o pins 55 timers 5 capture/compare/pwm modules 2 enhanced capture/compare/pwm modules 3 serial communications mssp (1), enhanced usart (2) ethernet communications (10base-t) yes parallel slave port communications (psp) no external memory bus no 10-bit analog-to-digital module 15 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow, mclr , wdt (pwrt, ost) instruction set 75 instructions, 83 with extended instruction set enabled packages 80-pin tqfp pic18f97j60 family ds39762a-page 10 advance information ? 2006 microchip technology inc. table 1-3: device features for the pic18f97j60 family (100-pin devices) features pic18f96j65 pic18f97j60 pic18f86j10 operating frequency dc ? 41.67 mhz dc ? 41.67 mhz dc ? 41.67 mhz program memory (bytes) 64k 96k 128k program memory (instructions) 32764 49148 65532 data memory (bytes) 3808 interrupt sources 29 i/o ports ports a, b, c, d, e, f, g, h, j i/o pins 70 timers 5 capture/compare/pwm modules 2 enhanced capture/compare/pwm modules 3 serial communications mssp (2), enhanced usart (2) ethernet communications (10base-t) yes parallel slave port communications (psp) yes external memory bus yes 10-bit analog-to-digital module 16 input channels resets (and delays) por, bor, reset instruction, stack full, stack underflow, mclr , wdt (pwrt, ost) instruction set 75 instructions, 83 with extended instruction set enabled packages 100-pin tqfp ? 2006 microchip technology inc. advance information ds39762a-page 11 pic18f97j60 family figure 1-1: pic18f66j60/66j65/67j60 (64-pin) block diagram instruction decode and control porta data latch data memory (3808 bytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31 level stack program counter prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> address latch program memory (64, 96, 128 kbytes) data latch 20 8 8 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 3 pclatu pcu note 1: see table 1-4 for i/o port pin descriptions. 2: bor functionality is provided when the on-board voltage regulator is enabled. eusart1 comparators mssp1 timer2 timer1 timer3 timer0 eccp1 adc 10-bit w instruction bus <16> stkptr bank 8 state machine control signals decode 8 8 eccp2 rom latch eccp3 ccp4 ccp5 portc portd porte portf portg ra0:ra5 (1) rc0:rc7 (1) rd0:rd2 (1) re0:re5 (1) rf1:rf7 (1) rg4 (1) portb rb0:rb7 (1) timer4 osc1/clki osc2/clko v dd , timing generation v ss mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset (2) precision reference band gap intrc oscillator regulator voltage v ddcore /v cap envreg ethernet pic18f97j60 family ds39762a-page 12 advance information ? 2006 microchip technology inc. figure 1-2: PIC18F86J60/86j65/87j60 (80-pin) block diagram prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> 8 8 3 w 8 8 8 instruction decode & control state machine control signals porta portc portd porte portf portg ra0:ra5 (1) rc0:rc7 (1) rd0:rd2 (1) re0:re7 (1) rf1:rf7 (1) rg0:rg4 (1) portb rb0:rb7 (1) porth rh0:rh7 (1) portj rj4:rj5 (1) eusart1 comparators mssp1 timer2 timer1 timer3 timer0 eccp1 adc 10-bit eusart2 eccp2 eccp3 ccp4 ccp5 timer4 note 1: see table 1-5 for i/o port pin descriptions. 2: bor functionality is provided when the on-board voltage regulator is enabled. osc1/clki osc2/clko v dd , v ss timing generation mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset (2) precision reference band gap intrc oscillator regulator voltage v ddcore /v cap envreg data latch data memory (3808 bytes) address latch data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31 level stack program counter 20 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 pclatu pcu instruction bus <16> stkptr bank decode rom latch ethernet address latch program memory (64, 96, 128 kbytes) data latch ? 2006 microchip technology inc. advance information ds39762a-page 13 pic18f97j60 family figure 1-3: pic18f96j60/96j65/97j60 (100-pin) block diagram prodl prodh 8 x 8 multiply 8 bitop 8 8 alu<8> 8 8 3 w 8 8 8 instruction decode & control data address<12> 12 access bsr fsr0 fsr1 fsr2 inc/dec logic address 4 12 4 pch pcl pclath 8 31 level stack program counter 20 table pointer<21> inc/dec logic 21 8 data bus<8> table latch 8 ir 12 rom latch pclatu pcu instruction bus <16> stkptr bank state machine control signals decode system bus interface ad15:ad0, a19:a16 (multiplexed with portd, porte and porth) porta portc portd porte portf portg ra0:ra5 (1) rc0:rc7 (1) rd0:rd7 (1) re0:re7 (1) rf0:rf7 (1) rg0:rg7 (1) portb rb0:rb7 (1) porth rh0:rh7 (1) portj rj0:rj7 (1) eusart1 comparators mssp1 timer2 timer1 timer3 timer0 eccp1 adc 10-bit eusart2 eccp2 eccp3 mssp2 ccp4 ccp5 timer4 note 1: see table 1-6 for i/o port pin descriptions. 2: bor functionality is provided when the on-board voltage regulator is enabled. osc1/clki osc2/clko v dd , v ss timing generation mclr power-up timer oscillator start-up timer power-on reset watchdog timer brown-out reset (2) precision reference band gap intrc oscillator regulator voltage v ddcore /v cap envreg ethernet data latch data memory (3808 bytes) address latch address latch program memory (64, 96, 128 kbytes) data latch pic18f97j60 family ds39762a-page 14 advance information ? 2006 microchip technology inc. table 1-4: pic18f66j60/66j65/67j60 pinout i/o descriptions pin name pin number pin type buffer type description tqfp mclr 7 i st master clear (reset) input. this pin is an active-low reset to the device. osc1/clki osc1 clki 39 i i st cmos oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in internal rc mode; cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc2/clko pin.) osc2/clko osc2 clko 40 o o ? ? oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in internal rc mode, osc2 pin outputs clko which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. porta is a bidirectional i/o port. ra0/leda/an0 ra0 leda an0 24 i/o o i ttl ? analog digital i/o. ethernet leda indicator output. analog input 0. ra1/ledb/an1 ra1 ledb an1 23 i/o o i ttl ? analog digital i/o. ethernet ledb indicator output. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 22 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 21 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 28 i/o i st st digital i/o. timer0 external clock input. ra5/an4 ra5 an4 27 i/o i ttl analog digital i/o. analog input 4. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) ? 2006 microchip technology inc. advance information ds39762a-page 15 pic18f97j60 family portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/flt0 rb0 int0 flt0 3 i/o i i ttl st st digital i/o. external interrupt 0. enhanced pwm fault input (eccp modules); enabled in software. rb1/int1 rb1 int1 4 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 5 i/o i ttl st digital i/o. external interrupt 2. rb3/int3 rb3 int3 6 i/o i ttl st digital i/o. external interrupt 3. rb4/kbi0 rb4 kbi0 44 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb5/kbi1 rb5 kbi1 43 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb6/kbi2/pgc rb6 kbi2 pgc 42 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 37 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-4: pic18f66j60/66j65/67j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) pic18f97j60 family ds39762a-page 16 advance information ? 2006 microchip technology inc. portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 30 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/eccp2/p2a rc1 t1osi eccp2 p2a 29 i/o i i/o o st cmos st ? digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm 2 output. eccp2 pwm output a. rc2/eccp1/p1a rc2 eccp1 p1a 33 i/o i/o o st st ? digital i/o. capture 1 input/compare 1 output/pwm 1 output. eccp1 pwm output a. rc3/sck1/scl1 rc3 sck1 scl1 34 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi1/sda1 rc4 sdi1 sda1 35 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo1 rc5 sdo1 36 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 31 i/o o i/o st ? st digital i/o. eusart1 asynchronous transmit. eusart1 synchronous clock (see related rx1/dt1 pin). rc7/rx1/dt1 rc7 rx1 dt1 32 i/o i i/o st st st digital i/o. eusart1 asynchronous receive. eusart1 synchronous data (see related tx1/ck1 pin). table 1-4: pic18f66j60/66j65/67j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) ? 2006 microchip technology inc. advance information ds39762a-page 17 pic18f97j60 family portd is a bidirectional i/o port. rd0/p1b rd0 p1b 60 i/o o st ? digital i/o. eccp1 pwm output b. rd1/eccp3/p3a rd1 eccp3 p3a 59 i/o i/o o st st ? digital i/o. capture 3 input/compare 3 output/pwm 3 output. eccp3 pwm output a. rd2/ccp4/p3d rd2 ccp4 p3d 58 i/o i/o o st st ? digital i/o. capture 4 input/compare 4 output/pwm 4 output. eccp4 pwm output d. table 1-4: pic18f66j60/66j65/67j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) pic18f97j60 family ds39762a-page 18 advance information ? 2006 microchip technology inc. porte is a bidirectional i/o port. re0/p2d re0 p2d 2 i/o o st ? digital i/o. eccp2 pwm output d. re1/p2c re1 p2c 1 i/o o st ? digital i/o. eccp2 pwm output c. re2/p2b re2 p2b 64 i/o o st ? digital i/o. eccp2 pwm output b. re3/p3c re3 p3c 63 i/o o st ? digital i/o. eccp3 pwm output c. re4/p3b re4 p3b 62 i/o o st ? digital i/o. eccp3 pwm output b. re5/p1c re5 p1c 61 i/o o st ? digital i/o. eccp1 pwm output c. table 1-4: pic18f66j60/66j65/67j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) ? 2006 microchip technology inc. advance information ds39762a-page 19 pic18f97j60 family portf is a bidirectional i/o port. rf1/an6/c2out rf1 an6 c2out 17 i/o i o st analog ? digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 16 i/o i o st analog ? digital i/o. analog input 7. comparator 1 output. rf3/an8 rf3 an8 15 i/o i st analog digital i/o. analog input 8. rf4/an9 rf4 an9 14 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf5 an10 cv ref 13 i/o i o st analog ? digital i/o. analog input 10. comparator reference voltage output. rf6/an11 rf6 an11 12 i/o i st analog digital i/o. analog input 11. rf7/ss1 rf7 ss1 11 i/o i st ttl digital i/o. spi slave select input. table 1-4: pic18f66j60/66j65/67j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) pic18f97j60 family ds39762a-page 20 advance information ? 2006 microchip technology inc. portg is a bidirectional i/o port. rg4/ccp5/p1d rg4 ccp5 p1d 8 i/o i/o o st st ? digital i/o. capture 5 input/compare 5 output/pwm 5 output. eccp1 pwm output d. v ss 9, 25, 41, 56 p ? ground reference for logic and i/o pins. v dd 26, 38, 57 p ? positive supply for peripheral digital logic and i/o pins. av ss 20 p ? ground reference for analog modules. av dd 19 p ? positive supply for analog modules. envreg 18 i st enable for on-chip voltage regulator. v ddcore /v cap v ddcore v cap 10 p p ? ? core logic power or external filter capacitor connection. positive supply for microcontroller core logic (regulator disabled). external filter capacitor connection (regulator enabled). v sspll 55 p ? ground reference for ethernet phy pll. v ddpll 54 p ? positive 3.3v supply for ethernet phy pll. v sstx 52 p ? ground reference for ethernet phy transmit subsystem. v ddtx 49 p ? positive 3.3v supply for ethernet phy transmit subsystem. v ssrx 45 p ? ground reference for ethernet phy receive subsystem. v ddrx 48 p ? positive 3.3v supply for ethernet phy receive subsystem. rbias 53 p ? bias current for ethernet phy. must be tied to v ss via a resistor; see section 18.0 ?ethernet module? for specification. tpout+ 51 o ? ethernet differential signal output. tpout- 50 o ? ethernet differential signal output. tpin+ 47 i analog ethernet differential signal input. tpin- 46 i analog ethernet differential signal input. table 1-4: pic18f66j60/66j65/67j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) ? 2006 microchip technology inc. advance information ds39762a-page 21 pic18f97j60 family table 1-5: PIC18F86J60/86j65/87j60 pinout i/o descriptions pin name pin number pin type buffer type description tqfp m cl r 9 i st master clear (reset) input. this pin is an active-low reset to the device. osc1/clki osc1 clki 49 i i st cmos oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in internal rc mode; cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc2/clko pin.) osc2/clko osc2 clko 50 o o ? ? oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in internal rc mode, osc2 pin outputs clko which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. porta is a bidirectional i/o port. ra0/leda/an0 ra0 leda an0 30 i/o o i ttl ? analog digital i/o. ethernet leda indicator output. analog input 0. ra1/ledb/an1 ra1 ledb an1 29 i/o o i ttl ? analog digital i/o. ethernet ledb indicator output. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 28 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 27 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 34 i/o i st st digital i/o. timer0 external clock input. ra5/an4 ra5 an4 33 i/o i ttl analog digital i/o. analog input 4. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for eccp2/p2a when ccp2mx configuration bit is set. 2: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 3: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared. 4: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). pic18f97j60 family ds39762a-page 22 advance information ? 2006 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/flt0 rb0 int0 flt0 5 i/o i i ttl st st digital i/o. external interrupt 0. enhanced pwm fault input (eccp modules); enabled in software. rb1/int1 rb1 int1 6 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 7 i/o i ttl st digital i/o. external interrupt 2. rb3/int3 rb3 int3 8 i/o i ttl st digital i/o. external interrupt 3. rb4/kbi0 rb4 kbi0 54 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb5/kbi1 rb5 kbi1 53 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb6/kbi2/pgc rb6 kbi2 pgc 52 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 47 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-5: PIC18F86J60/86j65/87j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for eccp2/p2a when ccp2mx configuration bit is set. 2: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 3: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared. 4: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). ? 2006 microchip technology inc. advance information ds39762a-page 23 pic18f97j60 family portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 36 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/eccp2/p2a rc1 t1osi eccp2 (1) p2a (1) 35 i/o i i/o o st cmos st ? digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm 2 output. eccp2 pwm output a. rc2/eccp1/p1a rc2 eccp1 p1a 43 i/o i/o o st st ? digital i/o. capture 1 input/compare 1 output/pwm 1 output. eccp1 pwm output a. rc3/sck1/scl1 rc3 sck1 scl1 44 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi1/sda1 rc4 sdi1 sda1 45 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo1 rc5 sdo1 46 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 37 i/o o i/o st ? st digital i/o. eusart1 asynchronous transmit. eusart1 synchronous clock (see related rx1/dt1 pin). rc7/rx1/dt1 rc7 rx1 dt1 38 i/o i i/o st st st digital i/o. eusart1 asynchronous receive. eusart1 synchronous data (see related tx1/ck1 pin). table 1-5: PIC18F86J60/86j65/87j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for eccp2/p2a when ccp2mx configuration bit is set. 2: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 3: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared. 4: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). pic18f97j60 family ds39762a-page 24 advance information ? 2006 microchip technology inc. portd is a bidirectional i/o port. rd0 72 i/o st digital i/o. rd1 69 i/o st digital i/o. rd2 68 i/o st digital i/o. porte is a bidirectional i/o port. re0/p2d re0 p2d 4 i/o o st ? digital i/o. eccp2 pwm output d. re1/p2c re1 p2c 3 i/o o st ? digital i/o. eccp2 pwm output c. re2/p2b re2 p2b 78 i/o o st ? digital i/o. eccp2 pwm output b. re3/p3c re3 p3c (2) 77 i/o o st ? digital i/o. eccp3 pwm output c. re4/p3b re4 p3b (2) 76 i/o o st ? digital i/o. eccp3 pwm output b. re5/p1c re5 p1c (2) 75 i/o o st ? digital i/o. eccp1 pwm output c. re6/p1b re6 p1b (2) 74 i/o o st ? digital i/o. eccp1 pwm output b. re7/eccp2/p2a re7 eccp2 (3) p2a (3) 73 i/o i/o o st st ? digital i/o. capture 2 input/compare 2 output/pwm 2 output. eccp2 pwm output a. table 1-5: PIC18F86J60/86j65/87j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for eccp2/p2a when ccp2mx configuration bit is set. 2: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 3: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared. 4: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). ? 2006 microchip technology inc. advance information ds39762a-page 25 pic18f97j60 family portf is a bidirectional i/o port. rf1/an6/c2out rf1 an6 c2out 23 i/o i o st analog ? digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 18 i/o i o st analog ? digital i/o. analog input 7. comparator 1 output. rf3/an8 rf3 an8 17 i/o i st analog digital i/o. analog input 8. rf4/an9 rf4 an9 16 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf5 an10 cv ref 15 i/o i o st analog ? digital i/o. analog input 10. comparator reference voltage output. rf6/an11 rf6 an11 14 i/o i st analog digital i/o. analog input 11. rf7/ss1 rf7 ss1 13 i/o i st ttl digital i/o. spi slave select input. table 1-5: PIC18F86J60/86j65/87j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for eccp2/p2a when ccp2mx configuration bit is set. 2: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 3: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared. 4: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). pic18f97j60 family ds39762a-page 26 advance information ? 2006 microchip technology inc. portg is a bidirectional i/o port. rg0/eccp3/p3a rg0 eccp3 p3a 56 i/o i/o o st st ? digital i/o. capture 3 input/compare 3 output/pwm 3 output. eccp3 pwm output a. rg1/tx2/ck2 rg1 tx2 ck2 55 i/o o i/o st ? st digital i/o. eusart2 asynchronous transmit. eusart2 synchronous clock (see related rx2/dt2 pin). rg2/rx2/dt2 rg2 rx2 dt2 42 i/o i i/o st st st digital i/o. eusart2 asynchronous receive. eusart2 synchronous data (see related tx2/ck2 pin). rg3/ccp4/p3d rg3 ccp4 p3d 41 i/o i/o o st st ? digital i/o. capture 4 input/compare 4 output/pwm 4 output. eccp3 pwm output d. rg4/ccp5/p1d rg4 ccp5 p1d 10 i/o i/o o st st ? digital i/o. capture 5 input/compare 5 output/pwm 5 output. eccp1 pwm output d. table 1-5: PIC18F86J60/86j65/87j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for eccp2/p2a when ccp2mx configuration bit is set. 2: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 3: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared. 4: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). ? 2006 microchip technology inc. advance information ds39762a-page 27 pic18f97j60 family porth is a bidirectional i/o port. rh0 79 i/o st digital i/o. rh1 80 i/o st digital i/o. rh2 1 i/o st digital i/o. rh3 2 i/o st digital i/o. rh4/an12/p3c rh4 an12 p3c (4) 22 i/o i o st analog ? digital i/o. analog input 12. eccp3 pwm output c. rh5/an13/p3b rh5 an13 p3b (4) 21 i/o i o st analog ? digital i/o. analog input 13. eccp3 pwm output b. rh6/an14/p1c rh6 an14 p1c (4) 20 i/o i o st analog ? digital i/o. analog input 14. eccp1 pwm output c. rh7/an15/p1b rh7 an15 p1b (4) 19 i/o i o st analog ? digital i/o. analog input 15. eccp1 pwm output b. table 1-5: PIC18F86J60/86j65/87j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for eccp2/p2a when ccp2mx configuration bit is set. 2: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 3: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared. 4: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). pic18f97j60 family ds39762a-page 28 advance information ? 2006 microchip technology inc. portj is a bidirectional i/o port. rj4 39 i/o st digital i/o. rj5 40 i/o st digital i/o v ss 11, 31, 51, 70 p ? ground reference for logic and i/o pins. v dd 32, 48, 71 p ? positive supply for peripheral digital logic and i/o pins. av ss 26 p ? ground reference for analog modules. av dd 25 p ? positive supply for analog modules. envreg 24 i st enable for on-chip voltage regulator. v ddcore /v cap v ddcore v cap 12 p p ? ? core logic power or external filter capacitor connection. positive supply for microcontroller core logic (regulator disabled). external filter capacitor connection (regulator enabled). v sspll 67 p ? ground reference for ethernet phy pll. v ddpll 66 p ? positive 3.3v supply for ethernet phy pll. v sstx 64 p ? ground reference for ethernet phy transmit subsystem. v ddtx 61 p ? positive 3.3v supply for ethernet phy transmit subsystem. v ssrx 57 p ? ground reference for ethernet phy receive subsystem. v ddrx 60 p ? positive 3.3v supply for ethernet phy receive subsystem. rbias 65 p ? bias current for ethernet phy. must be tied to v ss via a resistor; see section 18.0 ?ethernet module? for specification. tpout+ 63 o ? ethernet differential signal output. tpout- 62 o ? ethernet differential signal output. tpin+ 59 i analog ethernet differential signal input. tpin- 58 i analog ethernet differential signal input. table 1-5: PIC18F86J60/86j65/87j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: default assignment for eccp2/p2a when ccp2mx configuration bit is set. 2: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 3: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared. 4: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). ? 2006 microchip technology inc. advance information ds39762a-page 29 pic18f97j60 family table 1-6: pic18f96j60/96j65/97j60 pinout i/o descriptions pin name pin number pin type buffer type description tqfp mclr 13 i st master clear (reset) input. this pin is an active-low reset to the device. osc1/clki osc1 clki 63 i i st cmos oscillator crystal or external clock input. oscillator crystal input or external clock source input. st buffer when configured in internal rc mode; cmos otherwise. external clock source input. always associated with pin function osc1. (see related osc2/clko pin.) osc2/clko osc2 clko 64 o o ? ? oscillator crystal or clock output. oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in internal rc mode, osc2 pin outputs clko which has 1/4 the frequency of osc1 and denotes the instruction cycle rate. porta is a bidirectional i/o port. ra0/leda/an0 ra0 leda an0 35 i/o o i ttl ? analog digital i/o. ethernet leda indicator output. analog input 0. ra1/ledb/an1 ra1 ledb an1 34 i/o o i ttl ? analog digital i/o. ethernet ledb indicator output. analog input 1. ra2/an2/v ref - ra2 an2 v ref - 33 i/o i i ttl analog analog digital i/o. analog input 2. a/d reference voltage (low) input. ra3/an3/v ref + ra3 an3 v ref + 32 i/o i i ttl analog analog digital i/o. analog input 3. a/d reference voltage (high) input. ra4/t0cki ra4 t0cki 42 i/o i st st digital i/o. timer0 external clock input. ra5/an4 ra5 an4 41 i/o i ttl analog digital i/o. analog input 4. legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (extended microcontroller mode). 2: default assignment for eccp2/p2a for all devices in all operating modes (ccp2mx configuration bit is set). 3: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 4: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (microcontroller mode). 5: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). pic18f97j60 family ds39762a-page 30 advance information ? 2006 microchip technology inc. portb is a bidirectional i/o port. portb can be software programmed for internal weak pull-ups on all inputs. rb0/int0/flt0 rb0 int0 flt0 5 i/o i i ttl st st digital i/o. external interrupt 0. enhanced pwm fault input (eccp modules); enabled in software. rb1/int1 rb1 int1 6 i/o i ttl st digital i/o. external interrupt 1. rb2/int2 rb2 int2 7 i/o i ttl st digital i/o. external interrupt 2. rb3/int3/eccp2/p2a rb3 int3 eccp2 (1) p2a (1) 8 i/o i i/o o ttl st st ? digital i/o. external interrupt 3. capture 2 input/compare 2 output/pwm 2 output. eccp2 pwm output a. rb4/kbi0 rb4 kbi0 69 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb5/kbi1 rb5 kbi1 68 i/o i ttl ttl digital i/o. interrupt-on-change pin. rb6/kbi2/pgc rb6 kbi2 pgc 67 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp? programming clock pin. rb7/kbi3/pgd rb7 kbi3 pgd 57 i/o i i/o ttl ttl st digital i/o. interrupt-on-change pin. in-circuit debugger and icsp programming data pin. table 1-6: pic18f96j60/96j65/97j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (extended microcontroller mode). 2: default assignment for eccp2/p2a for all devices in all operating modes (ccp2mx configuration bit is set). 3: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 4: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (microcontroller mode). 5: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). ? 2006 microchip technology inc. advance information ds39762a-page 31 pic18f97j60 family portc is a bidirectional i/o port. rc0/t1oso/t13cki rc0 t1oso t13cki 44 i/o o i st ? st digital i/o. timer1 oscillator output. timer1/timer3 external clock input. rc1/t1osi/eccp2/p2a rc1 t1osi eccp2 (2) p2a (2) 43 i/o i i/o o st cmos st ? digital i/o. timer1 oscillator input. capture 2 input/compare 2 output/pwm 2 output. eccp2 pwm output a. rc2/eccp1/p1a rc2 eccp1 p1a 53 i/o i/o o st st ? digital i/o. capture 1 input/compare 1 output/pwm 1 output. eccp1 pwm output a. rc3/sck1/scl1 rc3 sck1 scl1 54 i/o i/o i/o st st st digital i/o. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c? mode. rc4/sdi1/sda1 rc4 sdi1 sda1 55 i/o i i/o st st st digital i/o. spi data in. i 2 c data i/o. rc5/sdo1 rc5 sdo1 56 i/o o st ? digital i/o. spi data out. rc6/tx1/ck1 rc6 tx1 ck1 45 i/o o i/o st ? st digital i/o. eusart1 asynchronous transmit. eusart1 synchronous clock (see related rx1/dt1 pin). rc7/rx1/dt1 rc7 rx1 dt1 46 i/o i i/o st st st digital i/o. eusart1 asynchronous receive. eusart1 synchronous data (see related tx1/ck1 pin). table 1-6: pic18f96j60/96j65/97j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (extended microcontroller mode). 2: default assignment for eccp2/p2a for all devices in all operating modes (ccp2mx configuration bit is set). 3: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 4: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (microcontroller mode). 5: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). pic18f97j60 family ds39762a-page 32 advance information ? 2006 microchip technology inc. portd is a bidirectional i/o port. rd0/ad0/psp0 rd0 ad0 psp0 92 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 0. parallel slave port data. rd1/ad1/psp1 rd1 ad1 psp1 91 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 1. parallel slave port data. rd2/ad2/psp2 rd2 ad2 psp2 90 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 2. parallel slave port data. rd3/ad3/psp3 rd3 ad3 psp3 89 i/o i/o i/o st ttl ttl digital i/o. external memory address/data 3. parallel slave port data. rd4/ad4/psp4/sdo2 rd4 ad4 psp4 sdo2 88 i/o i/o i/o o st ttl ttl ? digital i/o. external memory address/data 4. parallel slave port data. spi data out. rd5/ad5/psp5/ sdi2/sda2 rd5 ad5 psp5 sdi2 sda2 87 i/o i/o i/o i i/o st ttl ttl st st digital i/o. external memory address/data 5. parallel slave port data. spi data in. i 2 c? data i/o. rd6/ad6/psp6/ sck2/scl2 rd6 ad6 psp6 sck2 scl2 84 i/o i/o i/o i/o i/o st ttl ttl st st digital i/o. external memory address/data 6. parallel slave port data. synchronous serial clock input/output for spi mode. synchronous serial clock input/output for i 2 c mode. rd7/ad7/psp7/ss2 rd7 ad7 psp7 ss2 83 i/o i/o i/o i st ttl ttl ttl digital i/o. external memory address/data 7. parallel slave port data. spi slave select input. table 1-6: pic18f96j60/96j65/97j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (extended microcontroller mode). 2: default assignment for eccp2/p2a for all devices in all operating modes (ccp2mx configuration bit is set). 3: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 4: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (microcontroller mode). 5: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). ? 2006 microchip technology inc. advance information ds39762a-page 33 pic18f97j60 family porte is a bidirectional i/o port. re0/ad8/rd /p2d re0 ad8 rd p2d 4 i/o i/o i o st ttl ttl ? digital i/o. external memory address/data 8. read control for parallel slave port. eccp2 pwm output d. re1/ad9/wr /p2c re1 ad9 wr p2c 3 i/o i/o i o st ttl ttl ? digital i/o. external memory address/data 9. write control for parallel slave port. eccp2 pwm output c. re2/ad10/cs /p2b re2 ad10 cs p2b 98 i/o i/o i o st ttl ttl ? digital i/o. external memory address/data 10. chip select control for parallel slave port. eccp2 pwm output b. re3/ad11/p3c re3 ad11 p3c (3) 97 i/o i/o o st ttl ? digital i/o. external memory address/data 11. eccp3 pwm output c. re4/ad12/p3b re4 ad12 p3b (3) 96 i/o i/o o st ttl ? digital i/o. external memory address/data 12. eccp3 pwm output b. re5/ad13/p1c re5 ad13 p1c (3) 95 i/o i/o o st ttl ? digital i/o. external memory address/data 13. eccp1 pwm output c. re6/ad14/p1b re6 ad14 p1b (3) 94 i/o i/o o st ttl ? digital i/o. external memory address/data 14. eccp1 pwm output b. re7/ad15/eccp2/p2a re7 ad15 eccp2 (4) p2a (4) 93 i/o i/o i/o o st ttl st ? digital i/o. external memory address/data 15. capture 2 input/compare 2 output/pwm 2 output. eccp2 pwm output a. table 1-6: pic18f96j60/96j65/97j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (extended microcontroller mode). 2: default assignment for eccp2/p2a for all devices in all operating modes (ccp2mx configuration bit is set). 3: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 4: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (microcontroller mode). 5: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). pic18f97j60 family ds39762a-page 34 advance information ? 2006 microchip technology inc. portf is a bidirectional i/o port. rf0/an5 rf0 an5 12 i/o i st analog digital i/o. analog input 5. rf1/an6/c2out rf1 an6 c2out 28 i/o i o st analog ? digital i/o. analog input 6. comparator 2 output. rf2/an7/c1out rf2 an7 c1out 23 i/o i o st analog ? digital i/o. analog input 7. comparator 1 output. rf3/an8 rf3 an8 22 i/o i st analog digital i/o. analog input 8. rf4/an9 rf4 an9 21 i/o i st analog digital i/o. analog input 9. rf5/an10/cv ref rf5 an10 cv ref 20 i/o i o st analog ? digital i/o. analog input 10. comparator reference voltage output. rf6/an11 rf6 an11 19 i/o i st analog digital i/o. analog input 11. rf7/ss1 rf7 ss1 18 i/o i st ttl digital i/o. spi slave select input. table 1-6: pic18f96j60/96j65/97j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (extended microcontroller mode). 2: default assignment for eccp2/p2a for all devices in all operating modes (ccp2mx configuration bit is set). 3: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 4: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (microcontroller mode). 5: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). ? 2006 microchip technology inc. advance information ds39762a-page 35 pic18f97j60 family portg is a bidirectional i/o port. rg0/eccp3/p3a rg0 eccp3 p3a 71 i/o i/o o st st ? digital i/o. capture 3 input/compare 3 output/pwm 3 output. eccp3 pwm output a. rg1/tx2/ck2 rg1 tx2 ck2 70 i/o o i/o st ? st digital i/o. eusart2 asynchronous transmit. eusart2 synchronous clock (see related rx2/dt2 pin). rg2/rx2/dt2 rg2 rx2 dt2 52 i/o i i/o st st st digital i/o. eusart2 asynchronous receive. eusart2 synchronous data (see related tx2/ck2 pin). rg3/ccp4/p3d rg3 ccp4 p3d 51 i/o i/o o st st ? digital i/o. capture 4 input/compare 4 output/pwm 4 output. eccp3 pwm output d. rg4/ccp5/p1d rg4 ccp5 p1d 14 i/o i/o o st st ? digital i/o. capture 5 input/compare 5 output/pwm 5 output. eccp1 pwm output d. rg5 11 i/o st digital i/o. rg6 10 i/o st digital i/o. rg7 38 i/o st digital i/o. table 1-6: pic18f96j60/96j65/97j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (extended microcontroller mode). 2: default assignment for eccp2/p2a for all devices in all operating modes (ccp2mx configuration bit is set). 3: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 4: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (microcontroller mode). 5: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). pic18f97j60 family ds39762a-page 36 advance information ? 2006 microchip technology inc. porth is a bidirectional i/o port. rh0/a16 rh0 a16 99 i/o o st ? digital i/o. external memory address 16. rh1/a17 rh1 a17 100 i/o o st ? digital i/o. external memory address 17. rh2/a18 rh2 a18 1 i/o o st ? digital i/o. external memory address 18. rh3/a19 rh3 a19 2 i/o o st ? digital i/o. external memory address 19. rh4/an12/p3c rh4 an12 p3c (5) 27 i/o i o st analog ? digital i/o. analog input 12. eccp3 pwm output c. rh5/an13/p3b rh5 an13 p3b (5) 26 i/o i o st analog ? digital i/o. analog input 13. eccp3 pwm output b. rh6/an14/p1c rh6 an14 p1c (5) 25 i/o i o st analog ? digital i/o. analog input 14. eccp1 pwm output c. rh7/an15/p1b rh7 an15 p1b (5) 24 i/o i o st analog ? digital i/o. analog input 15. eccp1 pwm output b. table 1-6: pic18f96j60/96j65/97j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (extended microcontroller mode). 2: default assignment for eccp2/p2a for all devices in all operating modes (ccp2mx configuration bit is set). 3: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 4: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (microcontroller mode). 5: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). ? 2006 microchip technology inc. advance information ds39762a-page 37 pic18f97j60 family portj is a bidirectional i/o port. rj0/ale rj0 ale 49 i/o o st ? digital i/o. external memory address latch enable. rj1/oe rj1 oe 50 i/o o st ? digital i/o. external memory output enable. rj2/wrl rj2 wrl 66 i/o o st ? digital i/o. external memory write low control. rj3/wrh rj3 wrh 61 i/o o st ? digital i/o. external memory write high control. rj4/ba0 rj4 ba0 47 i/o o st ? digital i/o. external memory byte address 0 control. rj5/ce rj5 ce 48 i/o o st ? digital i/o external memory chip enable control. rj6/lb rj6 lb 58 i/o o st ? digital i/o. external memory low byte control. rj7/ub rj7 ub 39 i/o o st ? digital i/o. external memory high byte control. table 1-6: pic18f96j60/96j65/97j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (extended microcontroller mode). 2: default assignment for eccp2/p2a for all devices in all operating modes (ccp2mx configuration bit is set). 3: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 4: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (microcontroller mode). 5: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). pic18f97j60 family ds39762a-page 38 advance information ? 2006 microchip technology inc. nc 9 ? ? no connect. v ss 15, 36, 40, 60, 65, 85 p ? ground reference for logic and i/o pins. v dd 17, 37, 59, 62, 86 p ? positive supply for peripheral digital logic and i/o pins. av ss 31 p ? ground reference for analog modules. av dd 30 p ? positive supply for analog modules. envreg 29 i st enable for on-chip voltage regulator. v ddcore /v cap v ddcore v cap 16 p p ? ? core logic power or external filter capacitor connection. positive supply for microcontroller core logic (regulator disabled). external filter capacitor connection (regulator enabled). v sspll 82 p ? ground reference for ethernet phy pll. v ddpll 81 p ? positive 3.3v supply for ethernet phy pll. v sstx 79 p ? ground reference for ethernet phy transmit subsystem. v ddtx 76 p ? positive 3.3v supply for ethernet phy transmit subsystem. v ssrx 72 p ? ground reference for ethernet phy receive subsystem. v ddrx 75 p ? positive 3.3v supply for ethernet phy receive subsystem. rbias 80 p ? bias current for ethernet phy. must be tied to v ss via a resistor; see section 18.0 ?ethernet module? for specification. tpout+ 78 o ? ethernet differential signal output. tpout- 77 o ? ethernet differential signal output. tpin+ 74 i analog ethernet differential signal input. tpin- 73 i analog ethernet differential signal input. table 1-6: pic18f96j60/96j65/97j60 pinout i/o descriptions (continued) pin name pin number pin type buffer type description tqfp legend: ttl = ttl compatible input cmos = cmos compatible input or output st = schmitt trigger input with cmos levels analog = analog input i = input o = output p = power od = open-drain (no p diode to v dd ) note 1: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (extended microcontroller mode). 2: default assignment for eccp2/p2a for all devices in all operating modes (ccp2mx configuration bit is set). 3: default assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is set). 4: alternate assignment for eccp2/p2a when ccp2mx configuration bit is cleared (microcontroller mode). 5: alternate assignments for p1b/p1c/p3b/p3c (eccpmx configuration bit is cleared). ? 2006 microchip technology inc. advance information ds39762a-page 39 pic18f97j60 family 2.0 oscillator configurations 2.1 overview devices in the pic18f97j60 family incorporate an oscillator and microcontroller clock system that differs from standard pic18fxxjxx devices. the addition of the ethernet module, with its requirement for a stable 25 mhz clock source, makes it necessary to provide a primary oscillator that can provide this frequency, as well as a range of different microcontroller clock speeds. an overview of the oscillator structure is shown in figure 2-1. other oscillator features used in pic18fxxjxx enhanced microcontrollers, such as the internal rc oscillator and clock switching, remain the same. they are discussed later in this chapter. 2.2 oscillator types the pic18f97j60 family of devices can be operated in five different oscillator modes: 1. hs high-speed crystal/resonator 2. hspll high-speed crystal/resonator with software pll control 3. ec external clock with f osc /4 output 4. ecpll external clock with software pll control 5. intrc internal 31 khz oscillator 2.2.1 oscillator control the oscillator mode is selected by programming the fosc2:fosc0 configuration bits. fosc1:fosc0 bits select the default primary oscillator modes, while fosc2 selects when intrc may be invoked. the osccon register (register 2-2) selects the active clock mode. it is primarily used in controlling clock switching in power-managed modes. its use is discussed in section 2.7.1 ?oscillator control register? . the osctune register (register 2-1) is used to select the system clock frequency from the primary oscillator source by selecting combinations of prescaler/postscaler settings and enabling the pll. its use is described in section 2.6.1 ?pll block? . figure 2-1: pic18f97j60 family clock diagram pic18f97j60 family 5x pll fosc2:fosc0 secondary oscillator t1oscen enable oscillator t1oso t1osi clock source option for other modules osc1 osc2 sleep primary oscillator t1osc cpu peripherals idlen mux intrc source wdt, pwrt, fscm internal oscillator clock control osccon<1:0> and two-speed start-up ethernet clock prescaler postscaler pll/prescaler/postscaler pll osctune<7:5> (1) pll ec, hs, ecpll, hspll note: see table 2-2 for osctune register conf igurations and their corresponding frequencies. pic18f97j60 family ds39762a-page 40 advance information ? 2006 microchip technology inc. 2.3 crystal oscillator/ceramic resonators (hs modes) in hs or hspll oscillator modes, a crystal is connected to the osc1 and osc2 pins to establish oscillation. figure 2-2 shows the pin connections. the oscillator design requires the use of a parallel cut crystal. figure 2-2: crystal oscillator operation (hs or hspll configuration) table 2-1: capacitor selection for crystal oscillator 2.4 external clock input (ec modes) the ec and ecpll oscillator modes require an exter- nal clock source to be connected to the osc1 pin. there is no oscillator start-up time required after a power-on reset or after an exit from sleep mode. in the ec oscillator mode, the oscillator frequency divided by 4 is available on the osc2 pin. this signal may be used for test purposes or to synchronize other logic. figure 2-3 shows the pin connections for the ec oscillator mode. figure 2-3: external clock input operation (ec configuration) an external clock source may also be connected to the osc1 pin in the hs mode, as shown in figure 2-4. in this configuration, the osc2 pin is left open. figure 2-4: external clock input operation (hs osc configuration) note: use of a series cut crystal may give a fre- quency out of the crystal manufacturer?s specifications. osc type crystal freq. typical capacitor values tested: c1 c2 hs 25 mhz 15 pf 15 pf capacitor values are for design guidance only. different capacitor values may be required to produce acceptable oscillator operation. the user should test the performance of the oscillator over the expected v dd and temperature range for the application. refer to the following application notes for oscillator specific information: ? an588, ?picmicro ? microcontroller oscillator design guide? ? an826, ?crystal oscillator basics and crystal selection for rfpic ? and picmicro ? devices? ? an849, ?basic picmicro ? oscillator design? ? an943, ?practical picmicro ? oscillator analysis and design? ? an949, ?making your oscillator work? see the notes following this table for additional information. note 1: see table 2-1 for initial values of c1 and c2. 2: a series resistor (r s ) may be required for at strip cut crystals. 3: r f varies with the osci llator mode chosen. c1 (1) c2 (1) xtal osc2 osc1 r f (3) sleep to logic pic18fxxj6x r s (2) internal note 1: higher capacitance increases the stability of the oscillator but also increases the start-up time. 2: since each crystal has its own character- istics, the user should consult the crystal manufacturer for appropriate values of external components. 3: rs may be required to avoid overdriving crystals with low drive level specifications. 4: always verify oscillator performance over the v dd and temperature range that is expected for the application. osc1/clki osc2/clko f osc /4 clock from ext. system pic18fxxj6x osc1 osc2 open clock from ext. system pic18fxxj6x (hs mode) ? 2006 microchip technology inc. advance information ds39762a-page 41 pic18f97j60 family 2.5 internal oscillator block the pic18f97j60 family of devices includes an internal oscillator source (intrc) which provides a nominal 31 khz output. the intrc is enabled on device power-up and clocks the device during its configuration cycle until it enters operating mode. intrc is also enabled if it is selected as the device clock source or if any of the following are enabled: ? fail-safe clock monitor ? watchdog timer ? two-speed start-up these features are discussed in greater detail in section 24.0 ?special features of the cpu? . the intrc can also be optionally configured as the default clock source on device start-up by setting the fosc2 configuration bit. this is discussed in section 2.7.1 ?oscillator control register? . 2.6 ethernet operation and the microcontroller clock although devices of the pic18f97j60 family can accept a wide range of crystals and external oscillator inputs, they must always have a 25 mhz clock source when used for ethernet applications. no provision is made for internally generating the required ethernet clock from a primary oscillator source of a different frequency. a frequency tolerance is specified, likely excluding the use of ceramic resonators. see section 27.0 ?electrical characteristics? , table 27-6, parameter 5, for more details. 2.6.1 pll block to accommodate a range of applications and microcon- troller clock speeds, a separate pll block is incorporated into the clock system. it consists of three components: ? a configurable prescaler (1:2 or 1:3) ? a 5x pll frequency multiplier ? a configurable postscaler (1:1, 1:2, or 1:3) the operation of the pll block?s components is controlled by the osctune register (register 2-1). the use of the pll block?s prescaler and postscaler, with or without the pll itself, provides a range of sys- tem clock frequencies to choose from, including the unaltered 25 mhz of the primary oscillator. the full range of possible oscillator configurations compatible with operation is shown in table 2-2. register 2-1: osctune: pll block control register r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ppst1 pllen (1) ppst0 ppre ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ppst1: pll postscaler configuration bit 1 = divide-by-2 0 = divide-by-3 bit 6 pllen: 5x frequency multiplier pll enable bit (1) 1 = pll enabled 0 = pll disabled bit 5 ppst0: pll postscaler enable bit 1 = postscaler enabled 0 = postscaler disabled bit 4 ppre: pll prescaler configuration bit 1 = divide-by-2 0 = divide-by-3 bit 3-0 unimplemented: read as ? 0 ? note 1: available only for ecpll and hspll oscillator configurations; otherwise, this bit is unavailable and is read as ? 0 ?. pic18f97j60 family ds39762a-page 42 advance information ? 2006 microchip technology inc. table 2-2: device clock speeds fo r various pll block configurations 2.7 clock sources and oscillator switching the pic18f97j60 family of devices includes a feature that allows the device clock source to be switched from the main oscillator to an alternate clock source. these devices also offer two alternate clock sources. when an alternate clock source is enabled, the various power-managed operating modes are available. essentially, there are three clock sources for these devices: ? primary oscillators ? secondary oscillators ? internal oscillator block the primary oscillators include the external crystal and resonator modes and the external clock modes. the particular mode is defined by the fosc2:fosc0 configuration bits. the details of these modes are covered earlier in this chapter. the secondary oscillators are those external sources not connected to the osc1 or osc2 pins. these sources may continue to operate even after the controller is placed in a power-managed mode. the pic18f97j60 family of devices offers the timer1 oscillator as a second- ary oscillator. in all power-managed modes, this oscillator is often the time base for functions such as a real-time clock. most often, a 32.768 khz watch crystal is connected between the rc0/t1oso/t13cki and rc1/t1osi pins. loading capacitors are also connected from each pin to ground. the timer1 oscillator is discussed in greater detail in section 12.3 ?timer1 oscillator? . in addition to being a primary clock source, the internal oscillator is available as a power-managed mode clock source. the intrc source is also used as the clock source for several special features, such as the wdt and fail-safe clock monitor. the clock sources for the pic18f97j60 family devices are shown in figure 2-1. see section 24.0 ?special features of the cpu? for configuration register details. 5x pll pll prescaler pll postscaler pll block configuration (osctune<7:4>) clock frequency (mhz) enabled 2 disabled x101 (note 1) 2 1111 31.2500 3 0111 20.8333 3 disabled x100 41.6667 2 1110 20.8333 3 0110 13.8899 disabled disabled (2) disabled x00x 25 (default) 2 2 1011 6.2500 3 0010 4.1667 3 2 1011 4.1667 3 1000 2.7778 legend: x = don?t care note 1: unimplemented configuration; represents a clock frequency beyond the microcontroller?s operating range. 2: the prescaler is automatically disabled when the pll and postscaler are both disabled. ? 2006 microchip technology inc. advance information ds39762a-page 43 pic18f97j60 family 2.7.1 oscillator control register the osccon register (register 2-2) controls several aspects of the device clock?s operation, both in full power operation and in power-managed modes. the system clock select bits, scs1:scs0, select the clock source. the available clock sources are the primary clock (defined by the fosc2:fosc0 configu- ration bits), the secondary clock (timer1 oscillator) and the internal oscillator. the clock source changes after one or more of the bits are changed, following a brief clock transition interval. the osts (osccon<3>) and t1run (t1con<6>) bits indicate which clock source is currently providing the device clock. the t1run bit indicates when the timer1 oscillator is providing the device clock in secondary clock modes. in power-managed modes, only one of these bits will be set at any time. if neither bit is set, the intrc source is providing the clock, or the internal oscillator has just started and is not yet stable. the idlen bit determines if the device goes into sleep mode or one of the idle modes when the sleep instruction is executed. the use of the flag and control bits in the osccon register is discussed in more detail in section 3.0 ?power-managed modes? . note 1: the timer1 oscillator must be enabled to select the secondary clock source. the timer1 oscillator is enabled by setting the t1oscen bit in the timer1 control regis- ter (t1con<3>). if the timer1 oscillator is not enabled, then any attempt to select a secondary clock source will be ignored. 2: it is recommended that the timer1 oscillator be operating and stable before executing the sleep instruction or a very long delay may occur while the timer1 oscillator starts. register 2-2: osccon: oscillator control register r/w-0 u-0 u-0 u-0 r-q u-0 r/w-0 r/w-0 idlen ? ? ?osts (1) ?scs1scs0 bit 7 bit 0 legend: q = value determined by configuration r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 idlen: idle enable bit 1 = device enters idle mode on sleep instruction 0 = device enters sleep mode on sleep instruction bit 6-4 unimplemented: read as ? 0 ? bit 3 osts: oscillator status bit (1) 1 = device is running from oscillator source defined when scs1:scs0 = 00 0 = device is running from oscillator source defined when scs1:scs0 = 01 , 10 or 11 bit 2 unimplemented: read as ? 0 ? bit 1-0 scs1:scs0: system clock select bits 11 = internal oscillator 10 = primary oscillator 01 = timer1 oscillator when fosc2 = 1 ; 00 = primary oscillator when fosc2 = 0 ; 00 = internal oscillator note 1: reset value is ? 0 ? when two-speed start-up is enabled and ? 1 ? if disabled. pic18f97j60 family ds39762a-page 44 advance information ? 2006 microchip technology inc. 2.7.1.1 system clock selection and the fosc2 configuration bit the scs bits are cleared on all forms of reset. in the device?s default configuration, this means the primary oscillator defined by fosc1:fosc0 (that is, one of the hc or ec modes) is used as the primary clock source on device resets. the default clock configuration on reset can be changed with the fosc2 configuration bit. this bit affects the clock source selection setting when scs1:scs0 = 00 . when fosc2 = 1 (default), the oscillator source defined by fosc1:fosc0 is selected whenever scs1:scs0 = 00 . when fosc2 = 0 , the intrc oscilla- tor is selected whenever scs1:scs2 = 00 . because the scs bits are cleared on reset, the fosc2 setting also changes the default oscillator mode on reset. regardless of the setting of fosc2, intrc will always be enabled on device power-up. it will serve as the clock source until the device has loaded its configura- tion values from memory. it is at this point that the fosc configuration bits are read and the oscillator selection of operational mode is made. note that either the primary clock or the internal oscillator will have two bit setting options, at any given time, depending on the setting of fosc2. 2.7.2 oscillator transitions pic18f97j60 family devices contain circuitry to prevent clock ?glitches? when switching between clock sources. a short pause in the device clock occurs during the clock switch. the length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. this formula assumes that the new clock source is stable. clock transitions are discussed in greater detail in section 3.1.2 ?entering power-managed modes? . 2.8 effects of power-managed modes on the various clock sources when pri_idle mode is selected, the designated primary oscillator continues to run without interruption. for all other power-managed modes, the oscillator using the osc1 pin is disabled. the osc1 pin (and osc2 pin if used by the oscillator) will stop oscillating. in secondary clock modes (sec_run and sec_idle), the timer1 oscillator is operating and providing the device clock. the timer1 oscillator may also run in all power-managed modes if required to clock timer1 or timer3. in rc_run and rc_idle modes, the internal oscilla- tor provides the device clock source. the 31 khz intrc output can be used directly to provide the clock and may be enabled to support various special features, regardless of the power-managed mode (see section 24.2 ?watchdog timer (wdt)? through section 24.5 ?fail-safe clock monitor? for more information on wdt, fail-safe clock monitor and two-speed start-up). if the sleep mode is selected, all clock sources are stopped. since all the transistor switching currents have been stopped, sleep mode achieves the lowest current consumption of the device (only leakage currents). enabling any on-chip feature that will operate during sleep will increase the current consumed during sleep. the intrc is required to support wdt operation. the timer1 oscillator may be operating to support a real-time clock. other features may be operating that do not require a device clock source (i.e., mssp slave, psp, intx pins and others). peripherals that may add significant current consumption are listed in section 27.2 ?dc characteristics: power-down and supply current? . 2.9 power-up delays power-up delays are controlled by two timers, so that no external reset circuitry is required for most applica- tions. the delays ensure that the device is kept in reset until the device power supply is stable under nor- mal circumstances and the primary clock is operating and stable. for additional information on power-up delays, see section 4.5 ?power-up timer (pwrt)? . the first timer is the power-up timer (pwrt), which provides a fixed delay on power-up (parameter 33, table 27-12); it is always enabled. the second timer is the oscillator start-up timer (ost), intended to keep the chip in reset until the crystal oscillator is stable (hs modes). the ost does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. there is a delay of interval t csd (parameter 38, table 27-12), following por, while the controller becomes ready to execute instructions. table 2-3: osc1 and osc2 pin states in sleep mode oscillator mode osc1 pin osc2 pin ec, ecpll floating, pulled by external clock at logic low (clock/4 output) hs, hspll feedback inverter disabled at quiescent voltage level feedback inverter disabled at quiescent voltage level note: see table 4-2 in section 4.0 ?reset? for time-outs due to sleep and mclr reset. ? 2006 microchip technology inc. advance information ds39762a-page 45 pic18f97j60 family 3.0 power-managed modes the pic18f97j60 family devices provide the ability to manage power consumption by simply managing clock- ing to the cpu and the peripherals. in general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. for the sake of managing power in an application, there are three primary modes of operation: ? run mode ? idle mode ? sleep mode these modes define which portions of the device are clocked and at what speed. the run and idle modes may use any of the three available clock sources (primary, secondary or internal oscillator block); the sleep mode does not use a clock source. the power-managed modes include several power-saving features offered on previous picmicro ? devices. one is the clock switching feature, offered in other pic18 devices, allowing the controller to use the timer1 oscillator in place of the primary oscillator. also included is the sleep mode, offered by all picmicro devices, where all device clocks are stopped. 3.1 selecting power-managed modes selecting a power-managed mode requires two decisions: if the cpu is to be clocked or not and which clock source is to be used. the idlen bit (osccon<7>) controls cpu clocking, while the scs1:scs0 bits (osccon<1:0>) select the clock source. the individual modes, bit settings, clock sources and affected modules are summarized in table 3-1. 3.1.1 clock sources the scs1:scs0 bits allow the selection of one of three clock sources for power-managed modes. they are: ? the primary clock, as defined by the fosc2:fosc0 configuration bits ? the secondary clock (timer1 oscillator) ? the internal oscillator 3.1.2 entering power-managed modes switching from one power-managed mode to another begins by loading the osccon register. the scs1:scs0 bits select the clock source and determine which run or idle mode is to be used. changing these bits causes an immediate switch to the new clock source, assuming that it is running. the switch may also be subject to clock transition delays. these are discussed in section 3.1.3 ?clock transitions and status indicators? and subsequent sections. entry to the power-managed idle or sleep modes is triggered by the execution of a sleep instruction. the actual mode that results depends on the status of the idlen bit. depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. many transitions may be done by changing the oscillator select bits, or changing the idlen bit, prior to issuing a sleep instruction. if the idlen bit is already configured correctly, it may only be necessary to perform a sleep instruction to switch to the desired mode. table 3-1: power-managed modes mode osccon bits module clocking available clock and oscillator source idlen<7> (1) scs1:scs0<1:0> cpu peripherals sleep 0 n/a off off none ? all clocks are disabled pri_run n/a 10 clocked clocked primary ? hs, ec, hspll, ecpll; this is the normal full power execution mode. sec_run n/a 01 clocked clocked secondary ? timer1 oscillator rc_run n/a 11 clocked clocked internal oscillator pri_idle 110 off clocked primary ? hs, ec, hspll, ecpll sec_idle 101 off clocked secondary ? timer1 oscillator rc_idle 111 off clocked internal oscillator note 1: idlen reflects its value when the sleep instruction is executed. pic18f97j60 family ds39762a-page 46 advance information ? 2006 microchip technology inc. 3.1.3 clock transitions and status indicators the length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. this formula assumes that the new clock source is stable. two bits indicate the current clock source and its status: osts (osccon<3>) and t1run (t1con<6>). in general, only one of these bits will be set while in a given power-managed mode. when the osts bit is set, the primary clock is providing the device clock. when the t1run bit is set, the timer1 oscillator is providing the clock. if neither of these bits is set, intrc is clocking the device. 3.1.4 multiple sleep commands the power-managed mode that is invoked with the sleep instruction is determined by the setting of the idlen bit at the time the instruction is executed. if another sleep instruction is executed, the device will enter the power-managed mode specified by idlen at that time. if idlen has changed, the device will enter the new power-managed mode specified by the new setting. 3.2 run modes in the run modes, clocks to both the core and peripherals are active. the difference between these modes is the clock source. 3.2.1 pri_run mode the pri_run mode is the normal, full power execution mode of the microcontroller. this is also the default mode upon a device reset unless two-speed start-up is enabled (see section 24.4 ?two-speed start-up? for details). in this mode, the osts bit is set. (see section 2.7.1 ?oscillator control register? ). 3.2.2 sec_run mode the sec_run mode is the compatible mode to the ?clock switching? feature offered in other pic18 devices. in this mode, the cpu and peripherals are clocked from the timer1 oscillator. this gives users the option of lower power consumption while still using a high-accuracy clock source. sec_run mode is entered by setting the scs1:scs0 bits to ? 01 ?. the device clock source is switched to the timer1 oscillator (see figure 3-1), the primary oscillator is shut down, the t1run bit (t1con<6>) is set and the osts bit is cleared. on transitions from sec_run mode to pri_run, the peripherals and cpu continue to be clocked from the timer1 oscillator while the primary clock is started. when the primary clock becomes ready, a clock switch back to the primary clock occurs (see figure 3-2). when the clock switch is complete, the t1run bit is cleared, the osts bit is set and the primary clock is providing the clock. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run. note: executing a sleep instruction does not necessarily place the device into sleep mode. it acts as the trigger to place the controller into either the sleep mode or one of the idle modes, depending on the setting of the idlen bit. note: the timer1 oscillator should already be running prior to entering sec_run mode. if the t1oscen bit is not set when the scs1:scs0 bits are set to ? 01 ?, entry to sec_run mode will not occur. if the timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. in such situations, initial oscillator operation is far from stable and unpredictable operation may result. ? 2006 microchip technology inc. advance information ds39762a-page 47 pic18f97j60 family figure 3-1: transition timing for entry to sec_run mode figure 3-2: transition timing from sec_run mode to pri_run mode (hspll) q4 q3 q2 osc1 peripheral program q1 t1osi q1 counter clock cpu clock pc + 2 pc 123 n-1 n clock transition q4 q3 q2 q1 q3 q2 pc + 4 q1 q3 q4 osc1 peripheral program pc t1osi pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. scs1:scs0 bits changed t pll (1) 12 n-1n clock osts bit set transition t ost (1) pic18f97j60 family ds39762a-page 48 advance information ? 2006 microchip technology inc. 3.2.3 rc_run mode in rc_run mode, the cpu and peripherals are clocked from the internal oscillator; the primary clock is shut down. this mode provides the best power conser- vation of all the run modes, while still executing code. it works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times. this mode is entered by setting scs to ? 11 ?. when the clock source is switched to the intrc (see figure 3-3), the primary oscillator is shut down and the osts bit is cleared. on transitions from rc_run mode to pri_run mode, the device continues to be clocked from the intrc while the primary clock is started. when the primary clock becomes ready, a clock switch to the primary clock occurs (see figure 3-4). when the clock switch is complete, the osts bit is set and the primary clock is providing the device clock. the idlen and scs bits are not affected by the switch. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. figure 3-3: transition timing to rc_run mode figure 3-4: transition timing fr om rc_run mode to pri_run mode q4 q3 q2 osc1 peripheral program q1 intrc q1 counter clock cpu clock pc + 2 pc 123 n-1n clock transition q4 q3 q2 q1 q3 q2 pc + 4 q1 q3 q4 osc1 peripheral program pc intrc pll clock q1 pc + 4 q2 output q3 q4 q1 cpu clock pc + 2 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. scs1:scs0 bits changed t pll (1) 12 n-1n clock osts bit set transition t ost (1) ? 2006 microchip technology inc. advance information ds39762a-page 49 pic18f97j60 family 3.3 sleep mode the power-managed sleep mode is identical to the legacy sleep mode offered in all other picmicro devices. it is entered by clearing the idlen bit (the default state on device reset) and executing the sleep instruction. this shuts down the selected oscillator (figure 3-5). all clock source status bits are cleared. entering the sleep mode from any other mode does not require a clock switch. this is because no clocks are needed once the controller has entered sleep. if the wdt is selected, the intrc source will continue to operate. if the timer1 oscillator is enabled, it will also continue to run. when a wake event occurs in sleep mode (by interrupt, reset or wdt time-out), the device will not be clocked until the clock source selected by the scs1:scs0 bits becomes ready (see figure 3-6), or it will be clocked from the internal oscillator if either the two-speed start-up or the fail-safe clock monitor are enabled (see section 24.0 ?special features of the cpu? ). in either case, the osts bit is set when the primary clock is providing the device clocks. the idlen and scs bits are not affected by the wake-up. 3.4 idle modes the idle modes allow the controller?s cpu to be selectively shut down while the peripherals continue to operate. selecting a particular idle mode allows users to further manage power consumption. if the idlen bit is set to a ? 1 ? when a sleep instruction is executed, the peripherals will be clocked from the clock source selected using the scs1:scs0 bits; however, the cpu will not be clocked. the clock source status bits are not affected. setting idlen and executing a sleep instruction provides a quick method of switching from a given run mode to its corresponding idle mode. if the wdt is selected, the intrc source will continue to operate. if the timer1 oscillator is enabled, it will also continue to run. since the cpu is not executing instructions, the only exits from any of the idle modes are by interrupt, wdt time-out or a reset. when a wake event occurs, cpu execution is delayed by an interval of t csd (parameter 38, table 27-12) while it becomes ready to execute code. when the cpu begins executing code, it resumes with the same clock source for the current idle mode. for example, when waking from rc_idle mode, the internal oscillator block will clock the cpu and peripherals (in other words, rc_run mode). the idlen and scs bits are not affected by the wake-up. while in any idle mode or the sleep mode, a wdt time-out will result in a wdt wake-up to the run mode currently specified by the scs1:scs0 bits. figure 3-5: transition timing for entry to sleep mode figure 3-6: transition timing for wake from sleep mode (hspll) q4 q3 q2 osc1 peripheral sleep program q1 q1 counter clock cpu clock pc + 2 pc q3 q4 q1 q2 osc1 peripheral program pc pll clock q3 q4 output cpu clock q1 q2 q3 q4 q1 q2 clock counter pc + 6 pc + 4 q1 q2 q3 q4 wake event note1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. t ost (1) t pll (1) osts bit set pc + 2 pic18f97j60 family ds39762a-page 50 advance information ? 2006 microchip technology inc. 3.4.1 pri_idle mode this mode is unique among the three low-power idle modes in that it does not disable the primary device clock. for timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to ?warm up? or transition from another oscillator. pri_idle mode is entered from pri_run mode by setting the idlen bit and executing a sleep instruc- tion. if the device is in another run mode, set idlen first, then set the scs bits to ? 10 ? and execute sleep . although the cpu is disabled, the peripherals continue to be clocked from the primary clock source specified by the fosc1:fosc0 configuration bits. the osts bit remains set (see figure 3-7). when a wake event occurs, the cpu is clocked from the primary clock source. a delay of interval t csd is required between the wake event and when code execution starts. this is required to allow the cpu to become ready to execute instructions. after the wake-up, the osts bit remains set. the idlen and scs bits are not affected by the wake-up (see figure 3-8). 3.4.2 sec_idle mode in sec_idle mode, the cpu is disabled but the peripherals continue to be clocked from the timer1 oscillator. this mode is entered from sec_run by set- ting the idlen bit and executing a sleep instruction. if the device is in another run mode, set idlen first, then set scs1:scs0 to ? 01 ? and execute sleep . when the clock source is switched to the timer1 oscillator, the primary oscillator is shut down, the osts bit is cleared and the t1run bit is set. when a wake event occurs, the peripherals continue to be clocked from the timer1 oscillator. after an interval of t csd following the wake event, the cpu begins exe- cuting code being clocked by the timer1 oscillator. the idlen and scs bits are not affected by the wake-up; the timer1 oscillator continues to run (see figure 3-8). figure 3-7: transition timing for entry to idle mode figure 3-8: transition timing for wake from idle to run mode note: the timer1 oscillator should already be running prior to entering sec_idle mode. if the t1oscen bit is not set when the sleep instruction is executed, the sleep instruction will be ignored and entry to sec_idle mode will not occur. if the timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. in such situations, initial oscillator operation is far from stable and unpredictable operation may result. q1 peripheral program pc pc + 2 osc1 q3 q4 q1 cpu clock clock counter q2 osc1 peripheral program pc cpu clock q1 q3 q4 clock counter q2 wake event t csd ? 2006 microchip technology inc. advance information ds39762a-page 51 pic18f97j60 family 3.4.3 rc_idle mode in rc_idle mode, the cpu is disabled but the periph- erals continue to be clocked from the internal oscillator. this mode allows for controllable power conservation during idle periods. from rc_run, this mode is entered by setting the idlen bit and executing a sleep instruction. if the device is in another run mode, first set idlen, then clear the scs bits and execute sleep . when the clock source is switched to the intrc, the primary oscillator is shut down and the osts bit is cleared. when a wake event occurs, the peripherals continue to be clocked from the intrc. after a delay of t csd following the wake event, the cpu begins executing code being clocked by the intrc. the idlen and scs bits are not affected by the wake-up. the intrc source will continue to run if either the wdt or the fail-safe clock monitor is enabled. 3.5 exiting idle and sleep modes an exit from sleep mode, or any of the idle modes, is triggered by an interrupt, a reset or a wdt time-out. this section discusses the triggers that cause exits from power-managed modes. the clocking subsystem actions are discussed in each of the power-managed modes sections (see section 3.2 ?run modes?, section 3.3 ?sleep mode? and section 3.4 ?idle modes? ). 3.5.1 exit by interrupt any of the available interrupt sources can cause the device to exit from an idle mode, or the sleep mode, to a run mode. to enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the intcon or pie registers. the exit sequence is initiated when the corresponding interrupt flag bit is set. on all exits from idle or sleep modes by interrupt, code execution branches to the interrupt vector if the gie/gieh bit (intcon<7>) is set. otherwise, code execution continues or resumes without branching (see section 9.0 ?interrupts? ). a fixed delay of interval t csd following the wake event is required when leaving the sleep and idle modes. this delay is required for the cpu to prepare for execu- tion. instruction execution resumes on the first clock cycle following this delay. 3.5.2 exit by wdt time-out a wdt time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs. if the device is not executing code (all idle modes and sleep mode), the time-out will result in an exit from the power-managed mode (see section 3.2 ?run modes? and section 3.3 ?sleep mode? ). if the device is executing code (all run modes), the time-out will result in a wdt reset (see section 24.2 ?watchdog timer (wdt)? ). the wdt timer and postscaler are cleared by one of the following events: ? executing a sleep or clrwdt instruction ? the loss of a currently selected clock source (if the fail-safe clock monitor is enabled) 3.5.3 exit by reset exiting an idle or sleep mode by reset automatically forces the device to run from the intrc. 3.5.4 exit without an oscillator start-up delay certain exits from power-managed modes do not invoke the ost at all. there are two cases: ? pri_idle mode, where the primary clock source is not stopped ? the primary clock source is either the ec or ecpll mode in these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (pri_idle), or normally does not require an oscillator start-up delay (ec). however, a fixed delay of interval t csd following the wake event is still required when leaving the sleep and idle modes to allow the cpu to prepare for execution. instruction execution resumes on the first clock cycle following this delay. pic18f97j60 family ds39762a-page 52 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 53 pic18f97j60 family 4.0 reset the pic18f97j60 family of devices differentiate between various kinds of reset: a) power-on reset (por) b) mclr reset during normal operation c) mclr reset during power-managed modes d) watchdog timer (wdt) reset during execution e) brown-out reset (bor) f) reset instruction g) stack full reset h) stack underflow reset this section discusses resets generated by mclr , por and bor and covers the operation of the various start-up timers. stack reset events are covered in section 5.1.6.4 ?stack full and underflow resets? . wdt resets are covered in section 24.2 ?watchdog timer (wdt)? . a simplified block diagram of the on-chip reset circuit is shown in figure 4-1. 4.1 rcon register device reset events are tracked through the rcon register (register 4-1). the lower five bits of the register indicate that a specific reset event has occurred. in most cases, these bits can only be set by the event and must be cleared by the application after the event. the state of these flag bits, taken together, can be read to indicate the type of reset that just occurred. this is described in more detail in section 4.6 ?reset state of registers? . the rcon register also has a control bit for setting interrupt priority (ipen). interrupt priority is discussed in section 9.0 ?interrupts? . figure 4-1: simplified block diagram of on-chip reset circuit external reset mclr v dd wdt time-out v dd rise detect pwrt intrc por pulse chip_reset brown-out reset (1) reset instruction stack pointer stack full/underflow reset sleep ( )_idle 32 s note 1: the envreg pin must be tied high to enable brown-out reset. the brown-out reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. pwrt 11-bit ripple counter 66 ms s r q pic18f97j60 family ds39762a-page 54 advance information ? 2006 microchip technology inc. register 4-1: rcon: reset control register r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen ? ?ri to pd por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6-5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit 1 = the reset instruction was not executed (set by firmware only) 0 = the reset instruction was executed causing a device reset (must be set in software after a brown-out reset occurs) bit 3 to : watchdog time-out flag bit 1 = set by power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 2 pd : power-down detection flag bit 1 = set by power-up or by the clrwdt instruction 0 = set by execution of the sleep instruction bit 1 por : power-on reset status bit 1 = a power-on reset has not occurred (set by firmware only) 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = a brown-out reset has not occurred (set by firmware only) 0 = a brown-out reset occurred (must be set in software after a brown-out reset occurs) note 1: it is recommended that the por bit be set after a power-on reset has been detected so that subsequent power-on resets may be detected. 2: if the on-chip voltage regulator is disabled, bor remains ? 0 ? at all times. see section 4.4.1 ?detecting bor? for more information. 3: brown-out reset is said to have occurred when bor is ? 0 ? and por is ? 1 ? (assuming that por was set to ? 1 ? by software immediately after a power-on reset). ? 2006 microchip technology inc. advance information ds39762a-page 55 pic18f97j60 family 4.2 master clear (mclr ) the mclr pin provides a method for triggering a hard external reset of the device. a reset is generated by holding the pin low. pic18 extended microcontroller devices have a noise filter in the mclr reset path which detects and ignores small pulses. the mclr pin is not driven low by any internal resets, including the wdt. 4.3 power-on reset (por) a power-on reset condition is generated on-chip whenever v dd rises above a certain threshold. this allows the device to start in the initialized state when v dd is adequate for operation. to take advantage of the por circuitry, tie the mclr pin through a resistor (1 k to 10 k ) to v dd . this will eliminate external rc components usually needed to create a power-on reset delay. a minimum rise rate for v dd is specified (parameter d004). for a slow rise time, see figure 4-2. when the device starts normal operation (i.e., exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. por events are captured by the por bit (rcon<1>). the state of the bit is set to ? 0 ? whenever a power-on reset occurs; it does not change for any other reset event. por is not reset to ? 1 ? by any hardware event. to capture multiple events, the user manually resets the bit to ? 1 ? in software following any power-on reset. 4.4 brown-out reset (bor) the pic18f97j60 family of devices incorporates a simple bor function when the internal regulator is enabled (envreg pin is tied to v dd ). any drop of v dd below v bor (parameter d005) for greater than time t bor (parameter 35) will reset the device. a reset may or may not occur if v dd falls below v bor for less than t bor . the chip will remain in brown-out reset until v dd rises above v bor . once a bor has occurred, the power-up timer will keep the chip in reset for t pwrt (parameter 33). if v dd drops below v bor while the power-up timer is running, the chip will go back into a brown-out reset and the power-up timer will be initialized. once v dd rises above v bor , the power-up timer will execute the additional time delay. figure 4-2: external power-on reset circuit (for slow v dd power-up) 4.4.1 detecting bor the bor bit always resets to ? 0 ? on any brown-out reset or power-on reset event. this makes it difficult to determine if a brown-out reset event has occurred just by reading the state of bor alone. a more reliable method is to simultaneously check the state of both por and bor . this assumes that the por bit is reset to ? 1 ? in software immediately after any power-on reset event. if b or is ? 0 ? while por is ? 1 ?, it can be reliably assumed that a brown-out reset event has occurred. if the voltage regulator is disabled, brown-out reset functionality is disabled. in this case, the bor bit cannot be used to determine a brown-out reset event. the bor bit is still cleared by a power-on reset event. note 1: external power-on reset circuit is required only if the v dd power-up slope is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. 2: r < 40 k is recommended to make sure that the voltage drop across r does not violate the device?s electrical specification. 3: r1 1 k will limit any current flowing into mclr from external capacitor c, in the event of mclr /v pp pin breakdown, due to electrostatic discharge (esd) or electrical overstress (eos). c r1 r d v dd mclr pic18fxxj6x v dd pic18f97j60 family ds39762a-page 56 advance information ? 2006 microchip technology inc. 4.5 power-up timer (pwrt) pic18f97j60 family of devices incorporates an on-chip power-up timer (pwrt) to help regulate the power-on reset process. the pwrt is always enabled. the main function is to ensure that the device voltage is stable before code is executed. the power-up timer (pwrt) of the pic18f97j60 fam- ily devices is an 11-bit counter which uses the intrc source as the clock input. this yields an approximate time interval of 2048 x 32 s = 66 ms. while the pwrt is counting, the device is held in reset. the power-up time delay depends on the intrc clock and will vary from chip-to-chip due to temperature and process variation. see dc parameter 33 for details. 4.5.1 time-out sequence the pwrt time-out is invoked after the por pulse has cleared. the total time-out will vary based on the status of the pwrt. figure 4-3, figure 4-4, figure 4-5 and figure 4-6 all depict time-out sequences on power-up. since the time-outs occur from the por pulse, if mclr is kept low long enough, the pwrt will expire. bringing mclr high will begin execution immediately (figure 4-5). this is useful for testing purposes or to synchronize more than one pic18fxxj6x device operating in parallel. figure 4-3: time-out sequence on power-up (mclr tied to v dd , v dd rise < t pwrt ) figure 4-4: time-out sequence on power-up (mclr not tied to v dd ): case 1 t pwrt v dd mclr internal por pwrt time-out internal reset t pwrt v dd mclr internal por pwrt time-out internal reset ? 2006 microchip technology inc. advance information ds39762a-page 57 pic18f97j60 family figure 4-5: time-out sequence on power-up (mclr not tied to v dd ): case 2 figure 4-6: slow rise time (mclr tied to v dd , v dd rise > t pwrt ) v dd mclr internal por pwrt time-out internal reset t pwrt v dd mclr internal por pwrt time-out internal reset 0v 1v 3.3v t pwrt pic18f97j60 family ds39762a-page 58 advance information ? 2006 microchip technology inc. 4.6 reset state of registers most registers are unaffected by a reset. their status is unknown on por and unchanged by all other resets. the other registers are forced to a ?reset state? depending on the type of reset that occurred. most registers are not affected by a wdt wake-up, since this is viewed as the resumption of normal operation. status bits from the rcon register, ri , to , pd , por and bor, are set or cleared differently in different reset situations, as indicated in table 4-1. these bits are used in software to determine the nature of the reset. table 4-2 describes the reset states for all of the special function registers. these are categorized by power-on and brown-out resets, master clear and wdt resets and wdt wake-ups. table 4-1: status bits, their significance and the initialization condition for rcon register condition program counter (1) rcon register stkptr register ri to pd por bor stkful stkunf power-on reset 0000h 11100 0 0 reset instruction 0000h 0uuuu u u brown-out reset 0000h 111u0 u u mclr during power-managed run modes 0000h u1uuu u u mclr during power-managed idle modes and sleep mode 0000h u10uu u u wdt time-out during full power or power-managed run modes 0000h u0uuu u u mclr during full power execution 0000h uuuuu u u stack full reset (stvren = 1 ) 0000h uuuuu 1 u stack underflow reset (stvren = 1 ) 0000h uuuuu u 1 stack underflow error (not an actual reset, stvren = 0 ) 0000h uuuuu u 1 wdt time-out during power-managed idle or sleep modes pc + 2 u00uu u u interrupt exit from power-managed modes pc + 2 uu0uu u u legend: u = unchanged note 1: when the wake-up is due to an interrupt and the gieh or giel bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). ? 2006 microchip technology inc. advance information ds39762a-page 59 pic18f97j60 family table 4-2: initialization conditions for all registers register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt tosu pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---0 uuuu (1) tosh pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu (1) tosl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu (1) stkptr pic18f6xj6x pic18f8xj6x pic18f9xj6x 00-0 0000 uu-0 0000 uu-u uuuu (1) pclatu pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---u uuuu pclath pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu pcl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 pc + 2 (2) tblptru pic18f6xj6x pic18f8xj6x pic18f9xj6x --00 0000 --00 0000 --uu uuuu tblptrh pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu tblptrl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu tablat pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu prodh pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu prodl pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu intcon pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 000x 0000 000u uuuu uuuu (3) intcon2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu (3) intcon3 pic18f6xj6x pic18f8xj6x pic18f9xj6x 1100 0000 1100 0000 uuuu uuuu (3) indf0 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a postinc0 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a postdec0 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a preinc0 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a plusw0 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a fsr0h pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- xxxx ---- uuuu ---- uuuu fsr0l pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu wreg pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu indf1 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a postinc1 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a postdec1 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a preinc1 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a plusw1 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a fsr1h pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- xxxx ---- uuuu ---- uuuu fsr1l pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu bsr pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- 0000 ---- 0000 ---- uuuu indf2 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a postinc2 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a postdec2 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a preinc2 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a plusw2 pic18f6xj6x pic18f8xj6x pic18f9xj6x n/a n/a n/a fsr2h pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- xxxx ---- uuuu ---- uuuu fsr2l pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. pic18f97j60 family ds39762a-page 60 advance information ? 2006 microchip technology inc. status pic18f6xj6x pic18f8xj6x pic18f9xj6x ---x xxxx ---u uuuu ---u uuuu tmr0h pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu tmr0l pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu t0con pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu osccon pic18f6xj6x pic18f8xj6x pic18f9xj6x 0--- q-00 0--- q-00 u--- q-uu econ1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 00-- 0000 00-- uuuu uu-- wdtcon pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- ---0 ---- ---0 ---- ---u rcon (4) pic18f6xj6x pic18f8xj6x pic18f9xj6x 0--1 1100 0--q qquu u--u qquu tmr1h pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu tmr1l pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu t1con pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 u0uu uuuu uuuu uuuu tmr2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu pr2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 1111 1111 t2con pic18f6xj6x pic18f8xj6x pic18f9xj6x -000 0000 -000 0000 -uuu uuuu ssp1buf pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu ssp1add pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu ssp1stat pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu ssp1con1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu ssp1con2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu adresh pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu adresl pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu adcon0 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0-00 0000 0-00 0000 u-uu uuuu adcon1 pic18f6xj6x pic18f8xj6x pic18f9xj6x --00 0000 --00 0000 --uu uuuu adcon2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0-00 0000 0-00 0000 u-uu uuuu ccpr1h pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu ccpr1l pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu ccp1con pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu ccpr2h pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu ccpr2l pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu ccp2con pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu ccpr3h pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu ccpr3l pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu ccp3con pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eccp1as pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu cvrcon pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu cmcon pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0111 0000 0111 uuuu uuuu tmr3h pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu tmr3l pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu t3con pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 uuuu uuuu uuuu uuuu table 4-2: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. ? 2006 microchip technology inc. advance information ds39762a-page 61 pic18f97j60 family pspcon pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 ---- 0000 ---- uuuu ---- spbrg1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu rcreg1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu txreg1 pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu txsta1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0010 0000 0010 uuuu uuuu rcsta1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 000x 0000 000x uuuu uuuu eecon2 pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- ---- ---- ---- ---- ---- eecon1 pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 x00- ---0 x00- ---u uuu- ipr3 pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu pir3 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu (3) pie3 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu ipr2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1-11 1111 1-11 uuuu u-uu pir2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0-00 0000 0-00 uuuu u-uu (3) pie2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0-00 0000 0-00 uuuu u-uu ipr1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu pir1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu (3) pie1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu memcon pic18f6xj6x pic18f8xj6x pic18f9xj6x 0-00 --00 0-00 --00 u-uu --uu osctune pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 ---- 0000 ---- uuuu ---- trisj pic18f6xj6x pic18f8xj6x pic18f9xj6x --11 ---- --11 ---- --uu ---- pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu trish pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu trisg pic18f6xj6x pic18f8xj6x pic18f9xj6x ---1 ---- ---1 ---- ---u ---- pic18f6xj6x pic18f8xj6x pic18f9xj6x ---1 1111 ---1 1111 ---u uuuu pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu trisf pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 111- 1111 111- uuuu uuu- pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu trise pic18f6xj6x pic18f8xj6x pic18f9xj6x --11 1111 --11 1111 --uu uuuu pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu trisd pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- -111 ---- -111 ---- -uuu pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu trisc pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu trisb pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu trisa pic18f6xj6x pic18f8xj6x pic18f9xj6x --11 1111 --11 1111 --uu uuuu latj pic18f6xj6x pic18f8xj6x pic18f9xj6x --xx ---- --uu ---- --uu ---- pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu lath pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu table 4-2: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. pic18f97j60 family ds39762a-page 62 advance information ? 2006 microchip technology inc. latg pic18f6xj6x pic18f8xj6x pic18f9xj6x ---x ---- ---u ---- ---u ---- pic18f6xj6x pic18f8xj6x pic18f9xj6x ---x xxxx ---u uuuu ---u uuuu pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu latf pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxx- uuuu uuu- uuuu uuu- pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu late pic18f6xj6x pic18f8xj6x pic18f9xj6x --xx xxxx --uu uuuu --uu uuuu pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu latd pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- -xxx ---- -uuu ---- -uuu pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu latc pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu latb pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu lata pic18f6xj6x pic18f8xj6x pic18f9xj6x 00xx xxxx 00uu uuuu uuuu uuuu portj pic18f6xj6x pic18f8xj6x pic18f9xj6x --xx ---- --uu ---- --uu ---- pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu porth pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu portg pic18f6xj6x pic18f8xj6x pic18f9xj6x ---x ---- ---u ---- ---u ---- pic18f6xj6x pic18f8xj6x pic18f9xj6x ---x xxxx ---u uuuu ---u uuuu pic18f6xj6x pic18f8xj6x pic18f9xj6x 111x xxxx 111u uuuu uuuu uuuu portf pic18f6xj6x pic18f8xj6x pic18f9xj6x x000 000- x000 000- uuuu uuu- pic18f6xj6x pic18f8xj6x pic18f9xj6x x000 000- x000 000- uuuu uuu- porte pic18f6xj6x pic18f8xj6x pic18f9xj6x --xx xxxx --uu uuuu --uu uuuu pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu portd pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- -xxx ---- -uuu ---- -uuu pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu portc pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu portb pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu porta pic18f6xj6x pic18f8xj6x pic18f9xj6x 0-0x 0000 0-0u 0000 u-uu uuuu spbrgh1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu baudcon1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0100 0-00 01-0 0-00 uu-u u-uu spbrgh2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu baudcon2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0100 0-00 01-0 0-00 uu-u u-uu erdpth pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 1010 ---0 1010 ---u uuuu erdptl pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 0101 1111 0101 uuuu uuuu eccp1del pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu tmr4 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu pr4 pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 1111 1111 t4con pic18f6xj6x pic18f8xj6x pic18f9xj6x -000 0000 -000 0000 -uuu uuuu ccpr4h pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu ccpr4l pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu table 4-2: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. ? 2006 microchip technology inc. advance information ds39762a-page 63 pic18f97j60 family ccp4con pic18f6xj6x pic18f8xj6x pic18f9xj6x --00 0000 --00 0000 --uu uuuu ccpr5h pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu ccpr5l pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu ccp5con pic18f6xj6x pic18f8xj6x pic18f9xj6x --00 0000 --00 0000 --uu uuuu spbrg2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu rcreg2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu txreg2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu txsta2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0010 0000 0010 uuuu uuuu rcsta2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 000x 0000 000x uuuu uuuu eccp3as pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eccp3del pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eccp2as pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eccp2del pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu ssp2buf pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu ssp2add pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu ssp2stat pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu ssp2con1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu ssp2con2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu edata pic18f6xj6x pic18f8xj6x pic18f9xj6x xxxx xxxx uuuu uuuu uuuu uuuu eir pic18f6xj6x pic18f8xj6x pic18f9xj6x -000 0-00 -000 0-00 -uuu u-uu econ2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 100- ---- 100- ---- uuu- ---- estat pic18f6xj6x pic18f8xj6x pic18f9xj6x -0-0 -000 -0-0 -000 -u-u -uuu eie pic18f6xj6x pic18f8xj6x pic18f9xj6x -000 0-00 -000 0-00 -uuu u-uu edmacsh pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu edmacsl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu edmadsth pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---u uuuu edmadstl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu edmandh pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---u uuuu edmandl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu edmasth pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---u uuuu edmastl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu erxwrpth pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---u uuuu erxwrptl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu erxrdpth pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0101 ---0 0101 ---u uuuu erxrdptl pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1010 1111 1010 uuuu uuuu erxndh pic18f6xj6x pic18f8xj6x pic18f9xj6x ---1 1111 ---1 1111 ---u uuuu erxndl pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1111 1111 1111 uuuu uuuu erxsth pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0101 ---0 0101 ---u uuuu erxstl pic18f6xj6x pic18f8xj6x pic18f9xj6x 1111 1010 1111 1010 uuuu uuuu table 4-2: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. pic18f97j60 family ds39762a-page 64 advance information ? 2006 microchip technology inc. etxndh pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---u uuuu etxndl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu etxsth pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---u uuuu etxstl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu ewrpth pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---u uuuu ewrptl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu epktcnt pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu erxfcon pic18f6xj6x pic18f8xj6x pic18f9xj6x 1010 0001 1010 0001 uuuu uuuu epmoh pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---u uuuu epmol pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu epmcsh pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu epmcsl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu epmm7 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu epmm6 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu epmm5 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu epmm4 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu epmm3 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu epmm2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu epmm1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu epmm0 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eht7 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eht6 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eht5 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eht4 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eht3 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eht2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eht1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eht0 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu mirdh pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu mirdl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu miwrh pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu miwrl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu miregadr pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---u uuuu micmd pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- --00 ---- --00 ---- --uu micon pic18f6xj6x pic18f8xj6x pic18f9xj6x 0--- ---- 0--- ---- u--- ---- mamxflh pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0110 0000 0110 uuuu uuuu mamxfll pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu maclcon2 pic18f6xj6x pic18f8xj6x pic18f9xj6x --11 0111 --11 0111 --uu uuuu maclcon1 pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- 1111 ---- 1111 ---- uuuu table 4-2: initialization conditi ons for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. ? 2006 microchip technology inc. advance information ds39762a-page 65 pic18f97j60 family maipgh pic18f6xj6x pic18f8xj6x pic18f9xj6x -000 0000 -000 0000 -uuu uuuu maipgl pic18f6xj6x pic18f8xj6x pic18f9xj6x -000 0000 -000 0000 -uuu uuuu mabbipg pic18f6xj6x pic18f8xj6x pic18f9xj6x -000 0000 -000 0000 -uuu uuuu macon4 pic18f6xj6x pic18f8xj6x pic18f9xj6x -000 --00 -000 --00 -uuu --uu macon3 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu macon1 pic18f6xj6x pic18f8xj6x pic18f9xj6x ---0 0000 ---0 0000 ---u uuuu epaush pic18f6xj6x pic18f8xj6x pic18f9xj6x 0001 0000 0001 0000 000u uuuu epausl pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu eflocon pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- -000 ---- -000 ---- -uuu mistat pic18f6xj6x pic18f8xj6x pic18f9xj6x ---- 0000 ---- 0000 ---- uuuu maadr2 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu maadr1 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu maadr4 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu maadr3 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu maadr6 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu maadr5 pic18f6xj6x pic18f8xj6x pic18f9xj6x 0000 0000 0000 0000 uuuu uuuu table 4-2: initialization conditions for all registers (continued) register applicable devices power-on reset, brown-out reset mclr resets, wdt reset, reset instruction, stack resets wake-up via wdt or interrupt legend: u = unchanged, x = unknown, - = unimplemented bit, read as ? 0 ?, q = value depends on condition. shaded cells indicate conditions do not apply for the designated device. note 1: when the wake-up is due to an interrupt and the giel or gieh bit is set, the tosu, tosh and tosl are updated with the current value of the pc. the stkptr is modified to point to the next location in the hardware stack. 2: when the wake-up is due to an interrupt and the giel or gieh bit is set, the pc is loaded with the interrupt vector (0008h or 0018h). 3: one or more bits in the intconx or pirx registers will be affected (to cause wake-up). 4: see table 4-1 for reset value for specific condition. pic18f97j60 family ds39762a-page 66 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 67 pic18f97j60 family 5.0 memory organization there are two types of memory in pic18 flash microcontroller devices: ? program memory ? data ram as harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. additional detailed information on the operation of the flash program memory is provided in section 6.0 ?flash program memory? . 5.1 program memory organization pic18 microcontrollers implement a 21-bit program counter which is capable of addressing a 2-mbyte program memory space. accessing a location between the upper boundary of the physically implemented memory and the 2-mbyte address will return all ? 0 ?s (a nop instruction). the entire pic18f97j60 family offers three sizes of on-chip flash program memory, from 64 kbytes (up to 32,764 single-word instructions) to 128 kbytes (65,532 single-word instructions). the program memory maps for individual family members are shown in figure 5-1. figure 5-1: memory maps for pic18f97j60 family devices note: sizes of memory areas are not to scale. sizes of program memory areas ar e enhanced to show detail. unimplemented read as ? 0 ? unimplemented read as ? 0 ? unimplemented read as ? 0 ? 000000h 1fffffh 01ffffh pic18fx6j60 pic18fx6j65 pic18fx7j60 00ffffh 017fffh pc<20:0> stack level 1 ? stack level 31 ? ? call, callw, rcall, return, retfie, retlw, 21 user memory space on-chip memory on-chip memory on-chip memory addulnk, subulnk config. words config. words config. words pic18f97j60 family ds39762a-page 68 advance information ? 2006 microchip technology inc. 5.1.1 hard memory vectors all pic18 devices have a total of three hard-coded return vectors in their program memory space. the reset vector address is the default value to which the program counter returns on all device resets; it is located at 0000h. pic18 devices also have two interrupt vector addresses for the handling of high priority and low priority interrupts. the high priority interrupt vector is located at 0008h and the low priority interrupt vector is at 0018h. their locations in relation to the program memory map are shown in figure 5-2. figure 5-2: hard vector and configuration word locations for pic18f97j60 family devices 5.1.2 flash configuration words because the pic18f97j60 family devices do not have persistent configuration memory, the top four words of on-chip program memory are reserved for configuration information. on reset, the configuration information is copied into the configuration registers. the configuration words are stored in their program memory location in numerical order, starting with the lower byte of config1 at the lowest address and end- ing with the upper byte of config4. for these devices, only configuration words, config1 through config3, are used; config4 is reserved. the actual addresses of the flash configuration word for devices in the pic18f97j60 family are shown in table 5-1. their location in the memory map is shown with the other memory vectors in figure 5-2. additional details on the device configuration words are provided in section 24.1 ?configuration bits? . table 5-1: flash configuration word for pic18f97j60 family devices reset vector low priority interrupt vector 0000h 0018h on-chip program memory high priority interrupt vector 0008h 1fffffh (top of memory) (top of memory-7) flash configuration words read ? 0 ? legend: (top of memory) represents upper boundary of on-chip program memory space (see figure 5-1 for device-specific values). shaded area represents unimplemented memory. areas are not shown to scale. device program memory (kbytes) configuration word addresses pic18f66j60 64 fff8h to ffffh PIC18F86J60 pic18f96j60 pic18f66j65 96 17ff8h to 17fffh pic18f86j65 pic18f96j65 pic18f67j60 128 1fff8h to 1ffffh pic18f87j60 pic18f97j60 ? 2006 microchip technology inc. advance information ds39762a-page 69 pic18f97j60 family 5.1.3 pic18f9xj60/9xj65 program memory modes the 100-pin devices in this family can address up to a total of 2 mbytes of program memory. this is achieved through the external memory bus. there are two distinct operating modes available to the controllers: ? microcontroller (mc) ? extended microcontroller (emc) the program memory mode is determined by setting the emb configuration bits (config3l<5:4>), as shown in register 5-1. (see also section 24.1 ?configuration bits? for additional details on the device configuration bits.) the program memory modes operate as follows: ?the microcontroller mode accesses only on-chip flash memory. attempts to read above the top of on-chip memory causes a read of all ? 0 ?s (a nop instruction). the microcontroller mode is also the only operating mode available to 64-pin and 80-pin devices. ?the extended microcontroller mode allows access to both internal and external program memories as a single block. the device can access its entire on-chip program memory. above this, the device accesses external program memory up to the 2-mbyte program space limit. execution automatically switches between the two memories as required. the setting of the emb configuration bits also controls the address bus width of the external memory bus. this is covered in more detail in section 7.0 ?external memory bus? . in all modes, the microcontroller has complete access to data ram. figure 5-3 compares the memory maps of the different program memory modes. the differences between on-chip and external memory access limitations are more fully explained in table 5-2. register 5-1: config3l: co nfiguration register 3 low r/wo-1 r/wo-1 r/wo-1 r/wo-1 r/wo-1 u-0 u-0 u-0 wait (1) bw (1) emb1 (1) emb0 (1) eashft (1) ? ? ? bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7 wait: external bus wait enable bit (1) 1 = wait states for operations on external memory bus disabled 0 = wait states for operations on external memory bus enabled and selected by memcon<5:4> bit 6 bw: data bus width select bit (1) 1 = 16-bit data width mode 0 = 8-bit data width mode bit 5-4 emb1:emb0: external memory bus configuration bits (1) 11 = microcontroller mode, external bus disabled 10 = extended microcontroller mode,12-bit address mode 01 = extended microcontroller mode,16-bit address mode 00 = extended microcontroller mode, 20-bit address mode bit 3 eashft: external address bus shift enable bit (1) 1 = address shifting enabled; address on external bus is offset to start at 000000h 0 = address shifting disabled; address on external bus reflects the pc value bit 2-0 unimplemented: read as ? 0 ? note 1: implemented on 100-pin devices only. pic18f97j60 family ds39762a-page 70 advance information ? 2006 microchip technology inc. 5.1.4 extended microcontroller mode and address shifting by default, devices in extended microcontroller mode directly present the program counter value on the external address bus for those addresses in the range of the external memory space. in practical terms, this means addresses in the external memory device below the top of on-chip memory are unavailable. to avoid this, the extended microcontroller mode implements an address shifting option to enable auto- matic address translation. in this mode, addresses presented on the external bus are shifted down by the size of the on-chip program memory and are remapped to start at 0000h. this allows the complete use of the external memory device?s memory space. figure 5-3: memory maps for pic18f97j60 family program memory modes table 5-2: memory access for pic18f9xj 60/9xj65 program memory modes external memory on-chip program memory microcontroller mode (1) 000000h on-chip program memory 1fffffh reads ? 0 ?s external on-chip memory memory (top of memory) (top of memory) + 1 legend: (top of memory) represents upper boundary of on-chip program memory space (see figure 5-1 for device-specific values). shaded areas represent unimplem ented or inaccessible areas depending on the mode. note 1: this mode is the only available mode on 64-pin and 80-pin devices and the default on 100-pin devices. 2: these modes are only ava ilable on 100-pin devices. extended microcontroller mode (2) 000000h 1fffffh (top of memory) (top of memory) + 1 external memory on-chip program memory 000000h 1fffffh (top of memory) (top of memory) + 1 no access space on-chip memory space external on-chip memory memory space mapped to external memory space space space mapped to external memory space (top of memory) extended microcontroller mode with address shifting (2) 1fffffh ? operating mode internal program memory external program memory execution from table read from table write to execution from table read from table write to microcontroller yes yes yes no access no access no access extended microcontroller yes yes yes yes yes yes ? 2006 microchip technology inc. advance information ds39762a-page 71 pic18f97j60 family 5.1.5 program counter the program counter (pc) specifies the address of the instruction to fetch for execution. the pc is 21 bits wide and is contained in three separate 8-bit registers. the low byte, known as the pcl register, is both readable and writable. the high byte, or pch register, contains the pc<15:8> bits; it is not directly readable or writable. updates to the pch register are performed through the pclath register. the upper byte is called pcu. this register contains the pc<20:16> bits; it is also not directly readable or writable. updates to the pcu register are performed through the pclatu register. the contents of pclath and pclatu are transferred to the program counter by any operation that writes to the pcl. similarly, the upper two bytes of the program counter are transferred to pclath and pclatu by an operation that reads pcl. this is useful for computed offsets to the pc (see section 5.1.8.1 ?computed goto? ). the pc addresses bytes in the program memory. to prevent the pc from becoming misaligned with word instructions, the least significant bit of pcl is fixed to a value of ? 0 ?. the pc increments by 2 to address sequential instructions in the program memory. the call , rcall , goto and program branch instructions write to the program counter directly. for these instructions, the contents of pclath and pclatu are not transferred to the program counter. 5.1.6 return address stack the return address stack allows any combination of up to 31 program calls and interrupts to occur. the pc is pushed onto the stack when a call or rcall instruction is executed, or an interrupt is acknowledged. the pc value is pulled off the stack on a return, retlw or a retfie instruction (and on addulnk and subulnk instructions if the extended instruction set is enabled). pclatu and pclath are not affected by any of the return or call instructions. the stack operates as a 31-word by 21-bit ram and a 5-bit stack pointer, stkptr. the stack space is not part of either program or data space. the stack pointer is readable and writable and the address on the top of the stack is readable and writable through the top-of-stack special function registers. data can also be pushed to, or popped from the stack, using these registers. a call type instruction causes a push onto the stack. the stack pointer is first incremented and the location pointed to by the stack pointer is written with the contents of the pc (already pointing to the instruction following the call ). a return type instruction causes a pop from the stack. the contents of the location pointed to by the stkptr are transferred to the pc and then the stack pointer is decremented. the stack pointer is initialized to ? 00000 ? after all resets. there is no ram associated with the location corresponding to a stack pointer value of ? 00000 ?; this is only a reset value. status bits indicate if the stack is full, has overflowed or has underflowed. 5.1.6.1 top-of-stack access only the top of the return address stack (tos) is read- able and writable. a set of three registers, tosu:tosh:tosl, holds the contents of the stack location pointed to by the stkptr register (figure 5-4). this allows users to implement a software stack if necessary. after a call, rcall or interrupt (and addulnk and subulnk instructions if the extended instruction set is enabled), the software can read the pushed value by reading the tosu:tosh:tosl registers. these values can be placed on a user-defined software stack. at return time, the software can return these values to tosu:tosh:tosl and do a return. the user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. figure 5-4: return address stack and associated registers 00011 001a34h 11111 11110 11101 00010 00001 00000 00010 return address stack <20:0> to p - o f - st a c k 000d58h tosl tosh tosu 34h 1ah 00h stkptr<4:0> top-of-stack registers stack pointer pic18f97j60 family ds39762a-page 72 advance information ? 2006 microchip technology inc. 5.1.6.2 return stack pointer (stkptr) the stkptr register (register 5-2) contains the stack pointer value, the stkful (stack full) status bit and the stkunf (stack underflow) status bit. the value of the stack pointer can be 0 through 31. the stack pointer increments before values are pushed onto the stack and decrements after values are popped off the stack. on reset, the stack pointer value will be zero. the user may read and write the stack pointer value. this feature can be used by a real-time operating system (rtos) for return stack maintenance. after the pc is pushed onto the stack 31 times (without popping any values off the stack), the stkful bit is set. the stkful bit is cleared by software or by a por. the action that takes place when the stack becomes full depends on the state of the stvren (stack over- flow reset enable) configuration bit. (refer to section 24.1 ?configuration bits? for a description of the device configuration bits.) if stvren is set (default), the 31st push will push the (pc + 2) value onto the stack, set the stkful bit and reset the device. the stkful bit will remain set and the stack pointer will be set to zero. if stvren is cleared, the stkful bit will be set on the 31st push and the stack pointer will increment to 31. any additional pushes will not overwrite the 31st push and the stkptr will remain at 31. when the stack has been popped enough times to unload the stack, the next pop returns a value of zero to the pc and sets the stkunf bit, while the stack pointer remains at zero. the stkunf bit will remain set until cleared by software or until a por occurs. 5.1.6.3 push and pop instructions since the top-of-stack is readable and writable, the ability to push values onto the stack and pull values off the stack, without disturbing normal program execu- tion, is a desirable feature. the pic18 instruction set includes two instructions, push and pop , that permit the tos to be manipulated under software control. tosu, tosh and tosl can be modified to place data or a return address on the stack. the push instruction places the current pc value onto the stack. this increments the stack pointer and loads the current pc value onto the stack. the pop instruction discards the current tos by decrementing the stack pointer. the previous value pushed onto the stack then becomes the tos value. note: returning a value of zero to the pc on an underflow has the effect of vectoring the program to the reset vector, where the stack conditions can be verified and appropriate actions can be taken. this is not the same as a reset, as the contents of the sfrs are not affected. register 5-2: stkptr: stack pointer register r/c-0 r/c-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 stkful (1) stkunf (1) ? sp4 sp3 sp2 sp1 sp0 bit 7 bit 0 legend: c = clearable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 stkful: stack full flag bit (1) 1 = stack became full or overflowed 0 = stack has not become full or overflowed bit 6 stkunf: stack underflow flag bit (1) 1 = stack underflow occurred 0 = stack underflow did not occur bit 5 unimplemented: read as ? 0 ? bit 4-0 sp4:sp0: stack pointer location bits note 1: bit 7 and bit 6 are cleared by user software or by a por. ? 2006 microchip technology inc. advance information ds39762a-page 73 pic18f97j60 family 5.1.6.4 stack full and underflow resets device resets on stack overflow and stack underflow conditions are enabled by setting the stvren bit in configuration register 1l. when stvren is set, a full or underflow condition will set the appropriate stkful or stkunf bit and then cause a device reset. when stvren is cleared, a full or underflow condition will set the appropriate stkful or stkunf bit, but not cause a device reset. the stkful or stkunf bit is cleared by user software or a power-on reset. 5.1.7 fast register stack a fast register stack is provided for the status, wreg and bsr registers to provide a ?fast return? option for interrupts. this stack is only one level deep and is neither readable nor writable. it is loaded with the current value of the corresponding register when the processor vectors for an interrupt. all interrupt sources will push values into the stack registers. the values in the registers are then loaded back into the working registers if the retfie, fast instruction is used to return from the interrupt. if both low and high priority interrupts are enabled, the stack registers cannot be used reliably to return from low priority interrupts. if a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. in these cases, users must save the key registers in software during a low priority interrupt. if interrupt priority is not used, all interrupts may use the fast register stack for returns from interrupt. if no interrupts are used, the fast register stack can be used to restore the status, wreg and bsr registers at the end of a subroutine call. to use the fast register stack for a subroutine call, a call label, fast instruction must be executed to save the status, wreg and bsr registers to the fast register stack. a return, fast instruction is then executed to restore these registers from the fast register stack. example 5-1 shows a source code example that uses the fast register stack during a subroutine call and return. example 5-1: fast register stack code example 5.1.8 look-up tables in program memory there may be programming situations that require the creation of data structures, or look-up tables, in program memory. for pic18 devices, look-up tables can be implemented in two ways: ? computed goto ? table reads 5.1.8.1 computed goto a computed goto is accomplished by adding an offset to the program counter. an example is shown in example 5-2. a look-up table can be formed with an addwf pcl instruction and a group of retlw nn instructions. the w register is loaded with an offset into the table before executing a call to that table. the first instruction of the called routine is the addwf pcl instruction. the next instruction executed will be one of the retlw nn instructions, that returns the value ? nn ? to the calling function. the offset value (in wreg) specifies the number of bytes that the program counter should advance and should be multiples of 2 (lsb = 0 ). in this method, only one data byte may be stored in each instruction location and room on the return address stack is required. example 5-2: computed goto using an offset value 5.1.8.2 table reads a better method of storing data in program memory allows two bytes of data to be stored in each instruction location. look-up table data may be stored two bytes per program word while programming. the table pointer (tblptr) specifies the byte address and the table latch (tablat) contains the data that is read from the program memory. data is transferred from program memory one byte at a time. table read operation is discussed further in section 6.1 ?table reads and table writes? . call sub1, fast ;status, wreg, bsr ;saved in fast register ;stack ? ? sub1 ? ? return fast ;restore values saved ;in fast register stack movf offset, w call table org nn00h table addwf pcl retlw nnh retlw nnh retlw nnh . . . pic18f97j60 family ds39762a-page 74 advance information ? 2006 microchip technology inc. 5.2 pic18 instruction cycle 5.2.1 clocking scheme the microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (q1, q2, q3 and q4). internally, the program counter is incremented on every q1; the instruction is fetched from the program memory and latched into the instruction register (ir) during q4. the instruction is decoded and executed during the following q1 through q4. the clocks and instruction execution flow are shown in figure 5-5. 5.2.2 instruction flow/pipelining an ?instruction cycle? consists of four q cycles, q1 through q4. the instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ), then two cycles are required to complete the instruction (example 5-3). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3 and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 5-5: clock/ instruction cycle example 5-3: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clko (rc mode) pc pc + 2 pc + 4 fetch inst (pc) execute inst (pc ? 2) fetch inst (pc + 2) execute inst (pc) fetch inst (pc + 4) execute inst (pc + 2) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ?flushed? from the pipeline while the new instruction is being fetched and then executed. t cy 0t cy 1t cy 2t cy 3t cy 4t cy 5 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. bra sub_1 fetch 3 execute 3 4. bsf porta, bit3 (forced nop) fetch 4 flush ( nop ) 5. instruction @ address sub_1 fetch sub_1 execute sub_1 ? 2006 microchip technology inc. advance information ds39762a-page 75 pic18f97j60 family 5.2.3 instructions in program memory the program memory is addressed in bytes. instruc- tions are stored as two bytes or four bytes in program memory. the least significant byte of an instruction word is always stored in a program memory location with an even address (lsb = 0 ). to maintain alignment with instruction boundaries, the pc increments in steps of 2 and the lsb will always read ? 0 ? (see section 5.1.5 ?program counter? ). figure 5-6 shows an example of how instruction words are stored in the program memory. the call and goto instructions have the absolute program memory address embedded into the instruction. since instructions are always stored on word boundaries, the data contained in the instruction is a word address. the word address is written to pc<20:1> which accesses the desired byte address in program memory. instruction #2 in figure 5-6 shows how the instruction, goto 0006h , is encoded in the program memory. program branch instructions, which encode a relative address offset, operate in the same manner. the offset value stored in a branch instruction represents the number of single-word instructions that the pc will be offset by. section 25.0 ?instruction set summary? provides further details of the instruction set. figure 5-6: instructions in program memory 5.2.4 two-word instructions the standard pic18 instruction set has four two-word instructions: call , movff , goto and lsfr . in all cases, the second word of the instructions always has ? 1111 ? as its four most significant bits; the other 12 bits are literal data, usually a data memory address. the use of ? 1111 ? in the 4 msbs of an instruction specifies a special form of nop . if the instruction is executed in proper sequence ? immediately after the first word ? the data in the second word is accessed and used by the instruction sequence. if the first word is skipped for some reason and the second word is executed by itself, a nop is executed instead. this is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the pc. example 5-4 shows how this works. example 5-4: two-word instructions word address lsb = 1 lsb = 0 program memory byte locations 000000h 000002h 000004h 000006h instruction 1: movlw 055h 0fh 55h 000008h instruction 2: goto 0006h efh 03h 00000ah f0h 00h 00000ch instruction 3: movff 123h, 456h c1h 23h 00000eh f4h 56h 000010h 000012h 000014h note: see section 5.5 ?program memory and the extended instruction set? for information on two-word instructions in the extended instruction set. case 1: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; no, skip this word 1111 0100 0101 0110 ; execute this word as a nop 0010 0100 0000 0000 addwf reg3 ; continue code case 2: object code source code 0110 0110 0000 0000 tstfsz reg1 ; is ram location 0? 1100 0001 0010 0011 movff reg1, reg2 ; yes, execute this word 1111 0100 0101 0110 ; 2nd word of instruction 0010 0100 0000 0000 addwf reg3 ; continue code pic18f97j60 family ds39762a-page 76 advance information ? 2006 microchip technology inc. 5.3 data memory organization the data memory in pic18 devices is implemented as static ram. each register in the data memory has a 12-bit address, allowing up to 4096 bytes of addressable memory. the memory space is divided into 16 banks that contain 256 bytes each. all of the pic18f97j60 family devices implement all available banks and pro- vide 3808 bytes of data memory available to the user. figure 5-7 shows the data memory organization for the devices. the data memory contains special function registers (sfrs) and general purpose registers (gprs). the sfrs are used for control and status of the controller and peripheral functions, while gprs are used for data storage and scratchpad operations in the user?s application. any read of an unimplemented location will read as ? 0 ?s. the instruction set and architecture allow operations across all banks. the entire data memory may be accessed by direct, indirect or indexed addressing modes. addressing modes are discussed later in this section. to ensure that commonly used registers (most sfrs and select gprs) can be accessed in a single cycle, pic18 devices implement an access bank. this is a 256-byte memory space that provides fast access to the majority of sfrs and the lower portion of gpr bank 0 without using the bsr. section 5.3.2 ?access bank? provides a detailed description of the access ram. 5.3.1 bank select register large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. ideally, this means that an entire address does not need to be provided for each read or write operation. for pic18 devices, this is accom- plished with a ram banking scheme. this divides the memory space into 16 contiguous banks of 256 bytes. depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit bank pointer. most instructions in the pic18 instruction set make use of the bank pointer, known as the bank select register (bsr). this sfr holds the 4 most significant bits of a location?s address; the instruction itself includes the 8 least significant bits. only the four lower bits of the bsr are implemented (bsr3:bsr0). the upper four bits are unused; they will always read ? 0 ? and cannot be written to. the bsr can be loaded directly by using the movlb instruction. the value of the bsr indicates the bank in data memory. the 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank?s lower boundary. the relationship between the bsr?s value and the bank division in data memory is shown in figure 5-8. since up to 16 registers may share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. for example, writing what should be program data to an 8-bit address of f9h, while the bsr is 0fh, will end up resetting the program counter. while any bank can be selected, only those banks that are actually implemented can be read or written to. writes to unimplemented banks are ignored, while reads from unimplemented banks will return ? 0 ?s. even so, the status register will still be affected as if the operation was successful. the data memory map in figure 5-7 indicates which banks are implemented. in the core pic18 instruction set, only the movff instruction fully specifies the 12-bit address of the source and target registers. this instruction ignores the bsr completely when it executes. all other instructions include only the low-order address as an operand and must use either the bsr or the access bank to locate their target registers. note: the operation of some aspects of data memory are changed when the pic18 extended instruction set is enabled. see section 5.6 ?data memory and the extended instruction set? for more information. ? 2006 microchip technology inc. advance information ds39762a-page 77 pic18f97j60 family figure 5-7: data memory map for pic18f97j60 family devices bank 0 bank 1 bank 14 bank 15 data memory map bsr<3:0> = 0000 = 0001 = 1111 060h 05fh f60h fffh 00h 5fh 60h ffh access bank when a = 0 : the bsr is ignored and the access bank is used. the first 96 bytes are general purpose ram (from bank 0). the remaining 160 bytes are special function registers (from bank 15). when a = 1 : the bsr specifies the bank used by the instruction. f5fh f00h effh 1ffh 100h 0ffh 000h access ram ffh 00h ffh 00h ffh 00h gpr gpr sfr access ram high access ram low bank 2 = 0010 (sfrs) 2ffh 200h bank 3 ffh 00h gpr ffh = 0011 = 1101 gpr gpr gpr gpr gpr gpr gpr gpr gpr gpr gpr 4ffh 400h 5ffh 500h 3ffh 300h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h 00h gpr gpr = 0110 = 0111 = 1010 = 1100 = 1000 = 0101 = 1001 = 1011 = 0100 bank 4 bank 5 bank 6 bank 7 bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 = 1110 6ffh 600h 7ffh 700h 8ffh 800h 9ffh 900h affh a00h bffh b00h cffh c00h dffh d00h e00h ethernet sfr e7fh e80h pic18f97j60 family ds39762a-page 78 advance information ? 2006 microchip technology inc. figure 5-8: use of the bank select register (direct addressing) 5.3.2 access bank while the use of the bsr with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. otherwise, data may be read from or written to the wrong location. this can be disastrous if a gpr is the intended target of an operation, but an sfr is written to instead. verifying and/or changing the bsr for each read or write to data memory can become very inefficient. to streamline access for the most commonly used data memory locations, the data memory is configured with an access bank, which allows users to access a mapped block of memory without specifying a bsr. the access bank consists of the first 96 bytes of memory (00h-5fh) in bank 0 and the last 160 bytes of memory (60h-ffh) in bank 15. the lower block is known as the ?access ram? and is composed of gprs. the upper block is where the device?s sfrs are mapped. these two areas are mapped contiguously in the access bank and can be addressed in a linear fashion by an 8-bit address (figure 5-7). the access bank is used by core pic18 instructions that include the access ram bit (the ?a? parameter in the instruction). when ?a? is equal to ? 1 ?, the instruction uses the bsr and the 8-bit address included in the opcode for the data memory address. when ?a? is ? 0 ?, however, the instruction is forced to use the access bank address map; the current value of the bsr is ignored entirely. using this ?forced? addressing allows the instruction to operate on a data address in a single cycle without updating the bsr first. for 8-bit addresses of 60h and above, this means that users can evaluate and operate on sfrs more efficiently. the access ram below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. access ram also allows for faster and more code efficient context saving and switching of variables. the mapping of the access bank is slightly different when the extended instruction set is enabled (xinst configuration bit = 1 ). this is discussed in more detail in section 5.6.3 ?mapping the access bank in indexed literal offset mode? . 5.3.3 general purpose register file pic18 devices may have banked memory in the gpr area. this is data ram which is available for use by all instructions. gprs start at the bottom of bank 0 (address 000h) and grow upwards towards the bottom of the sfr area. gprs are not initialized by a power-on reset and are unchanged on all other resets. note 1: the access ram bit of the instruction can be used to force an override of the selected bank (bsr<3:0>) to the registers of the access bank. 2: the movff instruction embeds the entire 12-bit address in the instruction. data memory bank select (2) 7 0 from opcode (2) 0000 000h 100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh 00h ffh bank 3 through bank 13 0010 11111111 7 0 bsr (1) 11111111 ? 2006 microchip technology inc. advance information ds39762a-page 79 pic18f97j60 family 5.3.4 special function registers the special function registers (sfrs) are registers used by the cpu and peripheral modules for controlling the desired operation of the device. these registers are implemented as static ram. the main group of sfrs start at the top of data memory (fffh) and extend downward to occupy more than the top half of bank 15 (f60h to fffh). these sfrs can be classified into two sets: those associated with the ?core? device functionality (alu, resets and interrupts) and those related to the peripheral functions. the reset and interrupt registers are described in their respective chapters, while the alu?s status register is described later in this section. registers related to the operation of the peripheral features are described in the chapter for that peripheral. the sfrs are typically distributed among the peripherals whose functions they control. unused sfr locations are unimplemented and read as ? 0 ?s. a list of sfrs is given in table 5-3; a full description is provided in table 5-5. table 5-3: special function register map for pic18f97j60 family devices address name address name address name address name address name fffh tosu fdfh indf2 (1) fbfh ccpr1h f9fh ipr1 f7fh spbrgh1 ffeh tosh fdeh postinc2 (1) fbeh ccpr1l f9eh pir1 f7eh baudcon1 ffdh tosl fddh postdec2 (1) fbdh ccp1con f9dh pie1 f7dh spbrgh2 ffch stkptr fdch preinc2 (1) fbch ccpr2h f9ch memcon (3) f7ch baudcon2 ffbh pclatu fdbh plusw2 (1) fbbh ccpr2l f9bh osctune f7bh erdpth ffah pclath fdah fsr2h fbah ccp2con f9ah trisj (3) f7ah erdptl ff9h pcl fd9h fsr2l fb9h ccpr3h f99h trish (3) f79h eccp1del ff8h tblptru fd8h status fb8h ccpr3l f98h trisg f78h tmr4 ff7h tblptrh fd7h tmr0h fb7h ccp3con f97h trisf f77h pr4 ff6h tblptrl fd6h tmr0l fb6h eccp1as f96h trise f76h t4con ff5h tablat fd5h t0con fb5h cvrcon f95h trisd f75h ccpr4h ff4h prodh fd4h ? (2) fb4h cmcon f94h trisc f74h ccpr4l ff3h prodl fd3h osccon fb3h tmr3h f93h trisb f73h ccp4con ff2h intcon fd2h econ1 fb2h tmr3l f92h trisa f72h ccpr5h ff1h intcon2 fd1h wdtcon fb1h t3con f91h latj (3) f71h ccpr5l ff0h intcon3 fd0h rcon fb0h pspcon f90h lath (3) f70h ccp5con fefh indf0 (1) fcfh tmr1h fafh spbrg1 f8fh latg f6fh spbrg2 feeh postinc0 (1) fceh tmr1l faeh rcreg1 f8eh latf f6eh rcreg2 fedh postdec0 (1) fcdh t1con fadh txreg1 f8dh late f6dh txreg2 fech preinc0 (1) fcch tmr2 fach txsta1 f8ch latd f6ch txsta2 febh plusw0 (1) fcbh pr2 fabh rcsta1 f8bh latc f6bh rcsta2 feah fsr0h fcah t2con faah ? (2) f8ah latb f6ah eccp3as fe9h fsr0l fc9h ssp1buf fa9h ? (2) f89h lata f69h eccp3del fe8h wreg fc8h ssp1add fa8h ? (2) f88h portj (3) f68h eccp2as fe7h indf1 (1) fc7h ssp1stat fa7h eecon2 (1) f87h porth (3) f67h eccp2del fe6h postinc1 (1) fc6h ssp1con1 fa6h eecon1 f86h portg f66h ssp2buf fe5h postdec1 (1) fc5h ssp1con2 fa5h ipr3 f85h portf f65h ssp2add fe4h preinc1 (1) fc4h adresh fa4h pir3 f84h porte f64h ssp2stat fe3h plusw1 (1) fc3h adresl fa3h pie3 f83h portd f63h ssp2con1 fe2h fsr1h fc2h adcon0 fa2h ipr2 f82h portc f62h ssp2con2 fe1h fsr1l fc1h adcon1 fa1h pir2 f81h portb f61h edata fe0h bsr fc0h adcon2 fa0h pie2 f80h porta f60h eir note 1: this is not a physical register. 2: unimplemented registers are read as ? 0 ?. 3: this register is not available on 64-pin devices. pic18f97j60 family ds39762a-page 80 advance information ? 2006 microchip technology inc. 5.3.5 ethernet sfrs in addition to the standard sfr set in bank 15, members of the pic18f97j60 family have a second set of sfrs. this group, associated exclusively with the ethernet module, occupies the top half of bank 14 (e80h to effh). a complete list of ethernet sfrs is given in table 5-4. all sfrs are fully described in table 5-5 note: to improve performance, frequently accessed ethernet registers are located in the standard sfr bank (f60h through fffh). table 5-4: ethernet sfr map for pic18f97j60 family devices address name address name address name address name effh ? (1) edfh ? (1) ebfh ? (1) e9fh ? (1) efeh econ2 edeh ? (1) ebeh ? (1) e9eh ? (1) efdh estat eddh ? (1) ebdh ? (1) e9dh ? (1) efch ? (1) edch ? (1) ebch ? (1) e9ch ? (1) efbh eie edbh ? (1) ebbh ? (1) e9bh ? (1) efah ? (1) edah ? (1) ebah ? (1) e9ah ? (1) ef9h ? (2) ed9h epktcnt eb9h mirdh e99h epaush ef8h ? (2) ed8h erxfcon eb8h mirdl e98h epausl ef7h edmacsh ed7h ? (1) eb7h miwrh e97h eflocon ef6h edmacsl ed6h ? (1) eb6h miwrl e96h ? (2) ef5h edmadsth ed5h epmoh eb5h ? (1) e95h ? (2) ef4h edmadstl ed4h epmol eb4h miregadr e94h ? (2) ef3h edmandh ed3h ? (2) eb3h ? (2) e93h ? (2) ef2h edmandl ed2h ? (2) eb2h micmd e92h ? (2) ef1h edmasth ed1h epmcsh eb1h micon e91h ? (2) ef0h edmastl ed0h epmcsl eb0h ? (1) e90h ? (2) eefh erxwrpth ecfh epmm7 eafh ? (2) e8fh ? (2) eeeh erxwrptl eceh epmm6 eaeh ? (1) e8eh ? (2) eedh erxrdpth ecdh epmm5 eadh ? (1) e8dh ? (2) eech erxrdptl ecch epmm4 each ? (1) e8ch ? (2) eebh erxndh ecbh epmm3 eabh mamxflh e8bh ? (2) eeah erxndl ecah epmm2 eaah mamxfll e8ah mistat ee9h erxsth ec9h epmm1 ea9h maclcon2 e89h ? (1) ee8h erxstl ec8h epmm0 ea8h maclcon1 e88h ? (1) ee7h etxndh ec7h eht7 ea7h maipgh e87h ? (1) ee6h etxndl ec6h eht6 ea6h maipgl e86h ? (1) ee5h etxsth ec5h eht5 ea5h ? (2) e85h maadr2 ee4h etxstl ec4h eht4 ea4h mabbipg e84h maadr1 ee3h ewrpth ec3h eht3 ea3h macon4 e83h maadr4 ee2h ewrptl ec2h eht2 ea2h macon3 e82h maadr3 ee1h ? (1) ec1h eht1 ea1h ? (1) e81h maadr6 ee0h ? (1) ec0h eht0 ea0h macon1 e80h maadr5 note 1: reserved register location; do not modify. 2: unimplemented registers are read as ? 0 ?. ? 2006 microchip technology inc. advance information ds39762a-page 81 pic18f97j60 family table 5-5: register file summary (pic18f97j60 family) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 values on por, bor details on page: tosu ? ? ? top-of-stack register upper byte (tos<20:16>) ---0 0000 59, 71 tosh top-of-stack register high byte (tos<15:8>) 0000 0000 59, 71 tosl top-of-stack register low byte (tos<7:0>) 0000 0000 59, 71 stkptr stkful (1) stkunf (1) ? sp4 sp3 sp2 sp1 sp0 00-0 0000 59, 72 pclatu ? ?bit 21 (2) holding register for pc<20:16> ---0 0000 59, 71 pclath holding register for pc<15:8> 0000 0000 59, 71 pcl pc low byte (pc<7:0>) 0000 0000 59, 71 tblptru ? ? bit 21 program memory table pointer upper byte (tblptr<20:16>) --00 0000 59, 98 tblptrh program memory table pointer high byte (tblptr<15:8>) 0000 0000 59, 98 tblptrl program memory table pointer low byte (tblptr<7:0>) 0000 0000 59, 98 tablat program memory table latch 0000 0000 59, 98 prodh product register high byte xxxx xxxx 59, 117 prodl product register low byte xxxx xxxx 59, 117 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 0000 000x 59, 121 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 1111 1111 59, 122 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 1100 0000 59, 123 indf0 uses contents of fsr0 to address data memory ? value of fsr0 not changed (not a physical register) n/a 59, 89 postinc0 uses contents of fsr0 to address data memory ? value of fsr0 post-incremented (not a physical register) n/a 59, 90 postdec0 uses contents of fsr0 to address data memory ? value of fsr0 post-decremented (not a physical register) n/a 59, 90 preinc0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) n/a 59, 90 plusw0 uses contents of fsr0 to address data memory ? value of fsr0 pre-incremented (not a physical register) ? value of fsr0 offset by w n/a 59, 90 fsr0h ? ? ? ? indirect data memory address pointer 0 high byte ---- xxxx 59, 89 fsr0l indirect data memory address pointer 0 low byte xxxx xxxx 59, 90 wreg working register xxxx xxxx 59 indf1 uses contents of fsr1 to address data memory ? value of fsr1 not changed (not a physical register) n/a 59, 89 postinc1 uses contents of fsr1 to address data memory ? value of fsr1 post-incremented (not a physical register) n/a 59, 90 postdec1 uses contents of fsr1 to address data memory ? value of fsr1 post-decremented (not a physical register) n/a 59, 90 preinc1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) n/a 59, 90 plusw1 uses contents of fsr1 to address data memory ? value of fsr1 pre-incremented (not a physical register) ? value of fsr1 offset by w n/a 59, 90 fsr1h ? ? ? ? indirect data memory address pointer 1 high byte ---- xxxx 59, 89 fsr1l indirect data memory address pointer 1 low byte xxxx xxxx 59, 89 bsr ? ? ? ? bank select register ---- 0000 59, 89 indf2 uses contents of fsr2 to address data memory ? value of fsr2 not changed (not a physical register) n/a 59, 89 postinc2 uses contents of fsr2 to address data memory ? value of fsr2 post-incremented (not a physical register) n/a 59, 90 postdec2 uses contents of fsr2 to address data memory ? value of fsr2 post-decremented (not a physical register) n/a 59, 90 preinc2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) n/a 59, 90 plusw2 uses contents of fsr2 to address data memory ? value of fsr2 pre-incremented (not a physical register) ? value of fsr2 offset by w n/a 59, 90 fsr2h ? ? ? ? indirect data memory address pointer 2 high byte ---- xxxx 59, 89 fsr2l indirect data memory address pointer 2 low byte xxxx xxxx 59, 89 legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?, q = value depends on condition, r = reserved bit, do not modify. shaded cells are unimplemented, read as ? 0 ?. note 1: bit 7 and bit 6 are cleared by user software or by a por. 2: bit 21 of the pc is only available in serial programming modes. 3: reset value is ? 0 ? when two-speed start-up is enabled and ? 1 ? if disabled. 4: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. 5: these bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ? 0 ?. reset values shown apply only to 100-pin devices. 6: these bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and rea d as ? 0 ?. reset values are shown for 100-pin devices. 7: in microcontroller mode, the bits in this register are unwritable and read as ? 0 ?. 8: pllen is only available when either ecpll or hspll oscillator mode is selected; otherwise, read as ? 0 ?. 9: implemented in 100-pin devices in microcontroller mode only. pic18f97j60 family ds39762a-page 82 advance information ? 2006 microchip technology inc. status ? ? ?novzdcc ---x xxxx 60, 87 tmr0h timer0 register high byte 0000 0000 60, 163 tmr0l timer0 register low byte xxxx xxxx 60, 163 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 1111 1111 60, 163 osccon idlen ? ? ?osts (3) ? scs1 scs0 0--- q-00 60, 43 econ1 txrst rxrst dmast csumen txrts rxen ? ? 0000 00-- 60, 211 wdtcon ? ? ? ? ? ? ?swdten --- ---0 60, 353 rcon ipen ? ?ri to pd por bor 0--1 1100 60, 54, 133 tmr1h timer1 register high byte xxxx xxxx 60, 167 tmr1l timer1 register low byte xxxx xxxx 60, 167 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 0000 0000 60, 167 tmr2 timer2 register 0000 0000 60, 173 pr2 timer2 period register 1111 1111 60, 173 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 -000 0000 60, 173 ssp1buf mssp1 receive buffer/transmit register xxxx xxxx 60, 265 ssp1add mssp1 address register (i 2 c? slave mode), mssp1 baud rate reload register (i 2 c master mode) 0000 0000 60, 265 ssp1stat smp cke d/a psr/w ua bf 0000 0000 60, 256, 266 ssp1con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 60, 257, 267 ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 60, 268 gcen ackstat admsk5 (4) admsk4 (4) admsk3 (4) admsk2 (4) admsk1 (4) sen adresh a/d result register high byte xxxx xxxx 60, 333 adresl a/d result register low byte xxxx xxxx 60, 333 adcon0 adcal ? chs3 chs2 chs1 chs0 go/done adon 0-00 0000 60, 325 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 --00 0000 60, 326 adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 0-00 0000 60, 327 ccpr1h capture/compare/pwm register 1 high byte xxxx xxxx 60, 185 ccpr1l capture/compare/pwm register 1 low byte xxxx xxxx 60, 185 ccp1con p1m1 p1m0 dc1b1 dc1b0 ccp1m3 ccp1m2 ccp1m1 ccp1m0 0000 0000 60, 189 ccpr2h capture/compare/pwm register 2 high byte xxxx xxxx 60, 185 ccpr2l capture/compare/pwm register 2 low byte xxxx xxxx 60, 185 ccp2con p2m1 p2m0 dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 0000 0000 60, 189 ccpr3h capture/compare/pwm register 3 high byte xxxx xxxx 60, 185 ccpr3l capture/compare/pwm register 3 low byte xxxx xxxx 60, 185 ccp3con p3m1 p3m0 dc3b1 dc3b0 ccp3m3 ccp3m2 ccp3m1 ccp3m0 0000 0000 60, 189 eccp1as eccp1ase eccp1as2 eccp1as1 eccp1as0 pss1ac1 pss1ac0 pss1bd1 pss1bd0 0000 0000 60, 201 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 0000 0000 60, 341 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 0000 0111 60, 335 tmr3h timer3 register high byte xxxx xxxx 60, 175 tmr3l timer3 register low byte xxxx xxxx 60, 175 table 5-5: register file summary (pic18f97j60 family) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 values on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?, q = value depends on condition, r = reserved bit, do not modify. shaded cells are unimplemented, read as ? 0 ?. note 1: bit 7 and bit 6 are cleared by user software or by a por. 2: bit 21 of the pc is only available in serial programming modes. 3: reset value is ? 0 ? when two-speed start-up is enabled and ? 1 ? if disabled. 4: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. 5: these bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ? 0 ?. reset values shown apply only to 100-pin devices. 6: these bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and rea d as ? 0 ?. reset values are shown for 100-pin devices. 7: in microcontroller mode, the bits in this register are unwritable and read as ? 0 ?. 8: pllen is only available when either ecpll or hspll oscillator mode is selected; otherwise, read as ? 0 ?. 9: implemented in 100-pin devices in microcontroller mode only. ? 2006 microchip technology inc. advance information ds39762a-page 83 pic18f97j60 family t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 0000 0000 60, 175 pspcon (5) ibf obf ibov pspmode ? ? ? ? 0000 ---- 61, 161 spbrg1 eusart1 baud rate generator register low byte 0000 0000 61, 306 rcreg1 eusart1 receive register 0000 0000 61, 313 txreg1 eusart1 transmit register xxxx xxxx 61, 315 txsta1 csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 61, 306 rcsta1 spen rx9 sren cren adden ferr oerr rx9d 0000 000x 61, 306 eecon2 program memory control register (not a physical register) ---- ---- 61, 96 eecon1 ? ? ? free wrerr wren wr ? ---0 x00- 61, 97 ipr3 ssp2ip (5) bcl2ip (5) rc2ip (6) tx2ip (6) tmr4ip ccp5ip ccp4ip ccp3ip 1111 1111 61, 132 pir3 ssp2if (5) bcl2if (5) rc2if (6) tx2if (6) tmr4if ccp5if ccp4if ccp3if 0000 0000 61, 126 pie3 ssp2ie (5) bcl2ie (5) rc2ie (6) tx2ie (6) tmr4ie ccp5ie ccp4ie ccp3ie 0000 0000 61, 129 ipr2 oscfip cmip ethip r bcl1ip ? tmr3ip ccp2ip 1111 1-11 61, 131 pir2 oscfif cmif ethif r bcl1if ? tmr3if ccp2if 0000 0-00 61, 125 pie2 oscfie cmie ethie r bcl1ie ? tmr3ie ccp2ie 0000 0-00 61, 128 ipr1 pspip (9) adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 1111 1111 61, 130 pir1 pspif (9) adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 0000 0000 61, 124 pie1 pspie (9) adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 0000 0000 61, 127 memcon (5,7) ebdis ?wait1wait0 ? ?wm1wm0 0-00 --00 61, 106 osctune ppst1 pllen (8) ppst0 ppre ? ? ? ? 0000 ---- 61, 41 trisj (6) trisj7 (5) trisj6 (5) trisj5 (5) trisj4 (5) trisj3 (5) trisj2 (5) trisj1 (5) trisj0 (5) 1111 1111 61, 159 trish (6) trish7 (6) trish6 (6) trish5 (6) trish4 (6) trish3 (6) trish2 (6) trish1 (6) trish0 (6) 1111 1111 61, 157 trisg trisg7 (5) trisg6 (5) trisg5 (5) trisg4 trisg3 (6) trisg2 (6) trisg1 (6) trisg0 (6) 1111 1111 61, 155 trisf trisf7 trisf6 trisf5 trisf 4 trisf3 trisf2 trisf1 trisf0 (5) 1111 1111 61, 152 trise trise7 (6) trise6 (6) trise5 trise4 trise3 trise2 trise1 trise0 1111 1111 61, 150 trisd trisd7 (5) trisd6 (5) trisd5 (5) trisd4 (5) trisd3 (5) trisd2 trisd1 trisd0 1111 1111 61, 147 trisc trisc7 trisc6 trisc5 trisc 4 trisc3 trisc2 trisc1 trisc0 1111 1111 61, 143 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 1111 1111 61, 140 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 --11 1111 61, 137 latj (6) latj7 (5) latj6 (5) latj5 (6) latj4 (6) latj3 (5) latj2 (5) latj1 (5) latj0 (5) xxxx xxxx 61, 159 lath (6) lath7 (6) lath6 (6) lath5 (6) lath4 (6) lath3 (6) lath2 (6) lath1 (6) lath0 (6) xxxx xxxx 61, 157 latg latg7 (5) latg6 (5) latg5 (5) latg4 latg3 (6) latg2 (6) latg1 (6) latg0 (6) xxxx xxxx 62, 155 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 (5) xxxx xxxx 62, 152 late late7 (6) late6 (6) late5 late4 late3 late2 late1 late0 xxxx xxxx 62, 150 latd latd7 (5) latd6 (5) latd5 (5) latd4 (5) latd3 (5) latd2 latd1 latd0 xxxx xxxx 62, 147 latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 xxxx xxxx 62, 143 latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 xxxx xxxx 62, 140 lata rdpu repu lata5 lata4 lata3 lata2 lata1 lata0 00xx xxxx 62, 137 portj (6) rj7 (5) rj6 (5) rj5 (6) rj4 (6) rj3 (5) rj2 (5) rj1 (5) rj0 (5) xxxx xxxx 62, 159 porth (6) rh7 (6) rh6 (6) rh5 (6) rh4 (6) rh3 (6) rh2 (6) rh1 (6) rh0 (6) 0000 xxxx 62, 157 portg rg7 (5) rg6 (5) rg5 (5) rg4 rg3 (6) rg2 (6) rg1 (6) rg0 (6) 111x xxxx 62, 155 table 5-5: register file summary (pic18f97j60 family) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 values on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?, q = value depends on condition, r = reserved bit, do not modify. shaded cells are unimplemented, read as ? 0 ?. note 1: bit 7 and bit 6 are cleared by user software or by a por. 2: bit 21 of the pc is only available in serial programming modes. 3: reset value is ? 0 ? when two-speed start-up is enabled and ? 1 ? if disabled. 4: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. 5: these bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ? 0 ?. reset values shown apply only to 100-pin devices. 6: these bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and rea d as ? 0 ?. reset values are shown for 100-pin devices. 7: in microcontroller mode, the bits in this register are unwritable and read as ? 0 ?. 8: pllen is only available when either ecpll or hspll oscillator mode is selected; otherwise, read as ? 0 ?. 9: implemented in 100-pin devices in microcontroller mode only. pic18f97j60 family ds39762a-page 84 advance information ? 2006 microchip technology inc. portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 (5) 0000 0000 62, 152 porte re7 (6) re6 (6) re5 re4 re3 re2 re1 re0 xxxx xxxx 62, 150 portd rd7 (5) rd6 (5) rd5 (5) rd4 (5) rd3 (5) rd2 rd1 rd0 xxxx xxxx 62, 147 portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx 62, 143 portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx 62, 140 porta rjpu (6) ? ra5 ra4 ra3 ra2 ra1 ra0 0-0x 0000 62, 137 spbrgh1 eusart1 baud rate generator register high byte 0000 0000 62, 306 baudcon1 abdovf rcidl rxdtp txckp brg16 ? wue abden 0100 0-00 62, 304 spbrgh2 eusart2 baud rate generator register high byte 0000 0000 62, 306 baudcon2 abdovf rcidl rxdtp txckp brg16 ? wue abden 0100 0-00 62, 304 erdpth ? ? ? buffer read pointer high byte ---0 0101 62, 209 erdptl buffer read pointer low byte 1111 1010 62, 209 eccp1del p1rsen p1dc6 p1dc5 p1dc4 p1dc3 p1dc2 p1dc1 p1dc0 0000 0000 62, 200 tmr4 timer4 register 0000 0000 62, 179 pr4 timer4 period register 1111 1111 62, 179 t4con ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 -000 0000 62, 179 ccpr4h capture/compare/pwm register 4 high byte xxxx xxxx 62, 185 ccpr4l capture/compare/pwm register 4 low byte xxxx xxxx 62, 185 ccp4con ? ? dc4b1 dc4b0 ccp4m3 ccp4m2 ccp4m1 ccp4m0 --00 0000 63, 181 ccpr5h capture/compare/pwm register 5 high byte xxxx xxxx 63, 185 ccpr5l capture/compare/pwm register 5 low byte xxxx xxxx 63, 185 ccp5con ? ? dc5b1 dc5b0 ccp5m3 ccp5m2 ccp5m1 ccp5m0 --00 0000 63, 181 spbrg2 eusart2 baud rate generator register low byte 0000 0000 63, 306 rcreg2 eusart2 receive register 0000 0000 63, 313 txreg2 eusart2 transmit register 0000 0000 63, 315 txsta2 csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 63, 302 rcsta2 spen rx9 sren cren adden ferr oerr rx9d 0000 000x 63, 303 eccp3as eccp3ase eccp3as2 eccp3as1 eccp3as0 pss3ac1 pss3ac0 pss3bd1 pss3bd0 0000 0000 63, 201 eccp3del p3rsen p3dc6 p3dc5 p3dc4 p3dc3 p3dc2 p3dc1 p3dc0 0000 0000 63, 200 eccp2as eccp2ase eccp2as2 eccp2as1 eccp2as0 pss2ac1 pss2ac0 pss2bd1 pss2bd0 0000 0000 63, 201 eccp2del p2rsen p2dc6 p2dc5 p2dc4 p2dc3 p2dc2 p2dc1 p2dc0 0000 0000 63, 200 ssp2buf mssp2 receive buffer/transmit register xxxx xxxx 63, 265 ssp2add mssp2 address register (i 2 c? slave mode), mssp2 baud rate reload register (i 2 c master mode) 0000 0000 63, 265 ssp2stat smp cke d/a psr/w ua bf 0000 0000 63, 256 ssp2con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 0000 0000 63, 257, 267 ssp2con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 63, 268 gcen ackstat admsk5 (4) admsk4 (4) admsk3 (4) admsk2 (4) admsk1 (4) sen edata ethernet transmit/receive buffer register (edata<7:0>) xxxx xxxx 63, 211 eir ? pktif dmaif linkif txif ? txerif rxerif -000 0-00 63, 227 econ2 autoinc pktdec ethen ? ? ? ? ? 100- ---- 63, 212 table 5-5: register file summary (pic18f97j60 family) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 values on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?, q = value depends on condition, r = reserved bit, do not modify. shaded cells are unimplemented, read as ? 0 ?. note 1: bit 7 and bit 6 are cleared by user software or by a por. 2: bit 21 of the pc is only available in serial programming modes. 3: reset value is ? 0 ? when two-speed start-up is enabled and ? 1 ? if disabled. 4: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. 5: these bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ? 0 ?. reset values shown apply only to 100-pin devices. 6: these bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and rea d as ? 0 ?. reset values are shown for 100-pin devices. 7: in microcontroller mode, the bits in this register are unwritable and read as ? 0 ?. 8: pllen is only available when either ecpll or hspll oscillator mode is selected; otherwise, read as ? 0 ?. 9: implemented in 100-pin devices in microcontroller mode only. ? 2006 microchip technology inc. advance information ds39762a-page 85 pic18f97j60 family estat ?bufer ?latecol ? rxbusy txabrt phyrdy -0-0 -000 63, 212 eie ? pktie dmaie linkie txie ? txerie rxerie -000 0-00 63, 226 edmacsh dma checksum register high byte 0000 0000 63, 253 edmacsl dma checksum register low byte 0000 0000 63, 253 edmadsth ? ? ? dma destination register high byte ---0 0000 63, 253 edmadstl dma destination register low byte 0000 0000 63, 253 edmandh ? ? ? dma end register high byte ---0 0000 63, 253 edmandl dma end register low byte 0000 0000 63, 253 edmasth ? ? ? dma start register high byte ---0 0000 63, 253 edmastl dma start register low byte 0000 0000 63, 253 erxwrpth ? ? ? receive buffer write pointer high byte ---0 0000 63, 241 erxwrptl receive buffer write pointer low byte 0000 0000 63, 241 erxrdpth ? ? ? receive buffer read pointer high byte ---0 0101 63, 241 erxrdptl receive buffer read pointer low byte 1111 1010 63, 241 erxndh ? ? ? receive end register high byte ---1 1111 63, 241 erxndl receive end register low byte 1111 1111 63, 241 erxsth ? ? ? receive start register high byte ---0 0101 63, 241 erxstl receive start register low byte 1111 1010 63, 241 etxndh ? ? ? transmit end register high byte ---0 0000 64, 241 etxndl transmit end register low byte 0000 0000 64, 241 etxsth ? ? ? transmit start register high byte ---0 0000 64, 241 etxstl transmit start register low byte 0000 0000 64, 241 ewrpth ? ? ? buffer write pointer high byte ---0 0000 64, 209 ewrptl buffer write pointer low byte 0000 0000 64, 209 epktcnt ethernet packet count register 0000 0000 64, 241 erxfcon ucen andor crcen pmen mpen hten mcen bcen 1010 0001 64, 246 epmoh ? ? ? pattern match offset register high byte ---0 0000 64, 249 epmol pattern match offset register low byte 0000 0000 64, 249 epmcsh pattern match checksum register high byte 0000 0000 64, 249 epmcsl pattern match checksum register low byte 0000 0000 64, 249 epmm7 pattern match mask register byte 7 0000 0000 64, 249 epmm6 pattern match mask register byte 6 0000 0000 64, 249 epmm5 pattern match mask register byte 5 0000 0000 64, 249 epmm4 pattern match mask register byte 4 0000 0000 64, 249 epmm3 pattern match mask register byte 3 0000 0000 64, 249 epmm2 pattern match mask register byte 2 0000 0000 64, 249 epmm1 pattern match mask register byte 1 0000 0000 64, 249 epmm0 pattern match mask register byte 0 0000 0000 64, 249 eht7 hash table register byte 7 0000 0000 64, 245 eht6 hash table register byte 6 0000 0000 64, 245 eht5 hash table register byte 5 0000 0000 64, 245 table 5-5: register file summary (pic18f97j60 family) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 values on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?, q = value depends on condition, r = reserved bit, do not modify. shaded cells are unimplemented, read as ? 0 ?. note 1: bit 7 and bit 6 are cleared by user software or by a por. 2: bit 21 of the pc is only available in serial programming modes. 3: reset value is ? 0 ? when two-speed start-up is enabled and ? 1 ? if disabled. 4: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. 5: these bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ? 0 ?. reset values shown apply only to 100-pin devices. 6: these bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and rea d as ? 0 ?. reset values are shown for 100-pin devices. 7: in microcontroller mode, the bits in this register are unwritable and read as ? 0 ?. 8: pllen is only available when either ecpll or hspll oscillator mode is selected; otherwise, read as ? 0 ?. 9: implemented in 100-pin devices in microcontroller mode only. pic18f97j60 family ds39762a-page 86 advance information ? 2006 microchip technology inc. eht4 hash table register byte 4 0000 0000 64, 245 eht3 hash table register byte 3 0000 0000 64, 245 eht2 hash table register byte 2 0000 0000 64, 245 eht1 hash table register byte 1 0000 0000 64, 245 eht0 hash table register byte 0 0000 0000 64, 245 mirdh mii read data register high byte 0000 0000 64, 217 mirdl mii read data register low byte 0000 0000 64, 217 miwrh mii write data register high byte 0000 0000 64, 217 miwrl mii write data register low byte 0000 0000 64, 217 miregadr ? ? ? mii address register ---0 0000 64, 217 micmd ? ? ? ? ? ? miiscan miird ---- --00 64, 216 micon rstmii ? ? ? ? ? ? ? 0--- ---- 64, 215 mamxflh maximum frame length register high byte 0000 0110 64, 241 mamxfll maximum frame length register low byte 0000 0000 64, 241 maclcon2 ? ? collision window register --11 0111 64, 241 maclcon1 ? ? ? ? retransmission maximum register ---- 1111 64, 241 maipgh ? non back-to-back inter-packet gap register high byte -000 0000 65, 241 maipgl ? non back-to-back inter-packet gap register low byte -000 0000 65, 241 mabbipg ? back-to-back inter-packet gap transmit register -000 0000 65, 232 macon4 ? defer bpen nobkoff ? ?r r -000 --00 65, 215 macon3 padcfg2 padcfg1 padcfg0 txcrcen phdrlen hfrmen frmlnen fuldpx 0000 0000 65, 214 macon1 ? ? ? r txpaus rxpaus passall marxen ---0 0000 65, 213 epaush pause timer value register high byte 0001 0000 65, 244 epausl pause timer value register low byte 0000 0000 65, 244 eflocon ? ? ? ? ? fuldpxs fcen1 fcen0 ---- -000 65, 244 mistat ? ? ? ? r nvalid scan busy ---- 0000 65, 216 maadr2 mac address register byte 2 (maadr<39:32>), oui byte 2 0000 0000 65, 231 maadr1 mac address register byte 1 (maadr<47:40>), oui byte 1 0000 0000 65, 231 maadr4 mac address register byte 4 (maadr<23:16>) 0000 0000 65, 231 maadr3 mac address register byte 3 (maadr<31:24>), oui byte 3 0000 0000 65, 231 maadr6 mac address register byte 6 (maadr<7:0>) 0000 0000 65, 231 maadr5 mac address register byte 5 (maadr<15:8>) 0000 0000 65, 231 table 5-5: register file summary (pic18f97j60 family) (continued) file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 values on por, bor details on page: legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?, q = value depends on condition, r = reserved bit, do not modify. shaded cells are unimplemented, read as ? 0 ?. note 1: bit 7 and bit 6 are cleared by user software or by a por. 2: bit 21 of the pc is only available in serial programming modes. 3: reset value is ? 0 ? when two-speed start-up is enabled and ? 1 ? if disabled. 4: alternate names and definitions for these bits when the mssp module is operating in i 2 c? slave mode. 5: these bits and/or registers are only available in 100-pin devices; otherwise, they are unimplemented and read as ? 0 ?. reset values shown apply only to 100-pin devices. 6: these bits and/or registers are only available in 80-pin and 100-pin devices; in 64-pin devices, they are unimplemented and rea d as ? 0 ?. reset values are shown for 100-pin devices. 7: in microcontroller mode, the bits in this register are unwritable and read as ? 0 ?. 8: pllen is only available when either ecpll or hspll oscillator mode is selected; otherwise, read as ? 0 ?. 9: implemented in 100-pin devices in microcontroller mode only. ? 2006 microchip technology inc. advance information ds39762a-page 87 pic18f97j60 family 5.3.6 status register the status register, shown in register 5-3, contains the arithmetic status of the alu. the status register can be the operand for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc, c, ov or n bits, then the write to these five bits is disabled. these bits are set or cleared according to the device logic. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will set the z bit but leave the other bits unchanged. the status register then reads back as ? 000u u1uu ?. it is recom- mended, therefore, that only bcf , bsf , swapf , movff and movwf instructions are used to alter the status register because these instructions do not affect the z, c, dc, ov or n bits in the status register. for other instructions not affecting any status bits, see the instruction set summaries in table 25-2 and table 25-3. note: the c and dc bits operate as a borrow and digit borro w bit respectively, in subtraction. register 5-3: status register u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ?nov zdc (1) c (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 n: negative bit this bit is used for signed arithmetic (2?s complement). it indicates whether the result was negative (alu msb = 1 ). 1 = result was negative 0 = result was positive bit 3 ov: overflow bit this bit is used for signed arithmetic (2?s complement). it indicates an overflow of the 7-bit magnitude which causes the sign bit (bit 7 of the result) to change state. 1 = overflow occurred for signed arithmetic (in this arithmetic operation) 0 = no overflow occurred bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is non-zero bit 1 dc: digit carry/borrow bit (1) for addwf , addlw , sublw and subwf instructions: 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (2) for addwf , addlw , sublw and subwf instructions: 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the 2?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. 2: for borrow , the polarity is reversed. a subtraction is executed by adding the 2?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high or low-order bit of the source register. pic18f97j60 family ds39762a-page 88 advance information ? 2006 microchip technology inc. 5.4 data addressing modes while the program memory can be addressed in only one way ? through the program counter ? information in the data memory space can be addressed in several ways. for most instructions, the addressing mode is fixed. other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. the addressing modes are: ? inherent ? literal ?direct ?indirect an additional addressing mode, indexed literal offset, is available when the extended instruction set is enabled (xinst configuration bit = 1 ). its operation is discussed in greater detail in section 5.6.1 ?indexed addressing with literal offset? . 5.4.1 inherent and literal addressing many pic18 control instructions do not need any argument at all. they either perform an operation that globally affects the device, or they operate implicitly on one register. this addressing mode is known as inherent addressing. examples include sleep , reset and daw . other instructions work in a similar way, but require an additional explicit argument in the opcode. this is known as literal addressing mode because they require some literal value as an argument. examples include addlw and movlw , which respectively, add or move a literal value to the w register. other examples include call and goto , which include a 20-bit program memory address. 5.4.2 direct addressing direct addressing mode specifies all or part of the source and/or destination address of the operation within the opcode itself. the options are specified by the arguments accompanying the instruction. in the core pic18 instruction set, bit-oriented and byte-oriented instructions use some version of direct addressing by default. all of these instructions include some 8-bit literal address as their least significant byte. this address specifies either a register address in one of the banks of data ram ( section 5.3.3 ?general purpose register file? ), or a location in the access bank ( section 5.3.2 ?access bank? ) as the data source for the instruction. the access ram bit ?a? determines how the address is interpreted. when ?a? is ? 1 ?, the contents of the bsr ( section 5.3.1 ?bank select register? ) are used with the address to determine the complete 12-bit address of the register. when ?a? is ? 0 ?, the address is interpreted as being a register in the access bank. addressing that uses the access ram is sometimes also known as direct forced addressing mode. a few instructions, such as movff , include the entire 12-bit address (either source or destination) in their opcodes. in these cases, the bsr is ignored entirely. the destination of the operation?s results is determined by the destination bit ?d?. when ?d? is ? 1 ?, the results are stored back in the source register, overwriting its origi- nal contents. when ?d? is ? 0 ?, the results are stored in the w register. instructions without the ?d? argument have a destination that is implicit in the instruction. their destination is either the target register being operated on or the w register. 5.4.3 indirect addressing indirect addressing mode allows the user to access a location in data memory without giving a fixed address in the instruction. this is done by using file select registers (fsrs) as pointers to the locations to be read or written to. since the fsrs are themselves located in ram as special function registers, they can also be directly manipulated under program control. this makes fsrs very useful in implementing data structures, such as tables and arrays in data memory. the registers for indirect addressing are also implemented with indirect file operands (indfs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. this allows for efficient code using loops, such as the example of clearing an entire ram bank in example 5-5. it also enables users to perform indexed addressing and other stack pointer operations for program memory in data memory. example 5-5: how to clear ram (bank 1) using indirect addressing note: the execution of some instructions in the core pic18 instruction set are changed when the pic18 extended instruction set is enabled. see section 5.6 ?data memory and the extended instruction set? for more information. lfsr fsr0, 100h ; next clrf postinc0 ; clear indf ; register then ; inc pointer btfss fsr0h, 1 ; all done with ; bank1? bra next ; no, clear next continue ; yes, continue ? 2006 microchip technology inc. advance information ds39762a-page 89 pic18f97j60 family 5.4.3.1 fsr registers and the indf operand at the core of indirect addressing are three sets of registers: fsr0, fsr1 and fsr2. each represents a pair of 8-bit registers: fsrnh and fsrnl. the four upper bits of the fsrnh register are not used, so each fsr pair holds a 12-bit value. this represents a value that can address the entire range of the data memory in a linear fashion. the fsr register pairs, then, serve as pointers to data memory locations. indirect addressing is accomplished with a set of indirect file operands: indf0 through indf2. these can be thought of as ?virtual? regi sters; they are mapped in the sfr space but are not physically implemented. reading or writing to a particular indf register actually accesses its corresponding fsr register pair. a read from indf1, for example, reads the data at the address indicated by fsr1h:fsr1l. instructions t hat use the indf registers as operands actually use the contents of their corresponding fsr as a pointer to the instruction?s target. the indf operand is just a convenient way of using the pointer. because indirect addressing uses a full 12-bit address, data ram banking is not necessary. thus, the current contents of the bsr and access ram bit have no effect on determining the target address. figure 5-9: indirect addressing fsr1h:fsr1l 0 7 data memory 000h 100h 200h 300h f00h e00h fffh bank 0 bank 1 bank 2 bank 14 bank 15 bank 3 through bank 13 addwf, indf1, 1 0 7 using an instruction with one of the indirect addressing registers as the operand.... ...uses the 12-bit address stored in the fsr pair associated with that register.... ...to determine the data memory location to be used in that operation. in this case, the fsr1 pair contains fcch. this means the contents of location fcch will be added to that of the w register and stored back in fcch. xxxx 1111 11001100 pic18f97j60 family ds39762a-page 90 advance information ? 2006 microchip technology inc. 5.4.3.2 fsr registers and postinc, postdec, preinc and plusw in addition to the indf operand, each fsr register pair also has four additional indirect operands. like indf, these are ?virtual? registers that cannot be indirectly read or written to. accessing these registers actually accesses the associated fsr register pair, but also performs a specific action on its stored value. they are: ? postdec: accesses the fsr value, then automatically decrements it by ? 1 ? afterwards ? postinc: accesses the fsr value, then automatically increments it by ? 1 ? afterwards ? preinc: increments the fsr value by ? 1 ?, then uses it in the operation ? plusw: adds the signed value of the w register (range of -128 to 127) to that of the fsr and uses the new value in the operation in this context, accessing an indf register uses the value in the fsr registers without changing them. similarly, accessing a plusw register gives the fsr value offset by the value in the w register; neither value is actually changed in the operation. accessing the other virtual registers changes the value of the fsr registers. operations on the fsrs with postdec, postinc and preinc affect the entire register pair; that is, roll- overs of the fsrnl register from ffh to 00h carry over to the fsrnh register. on the other hand, results of these operations do not change the value of any flags in the status register (e.g., z, n, ov, etc.). the plusw register can be used to implement a form of indexed addressing in the data memory space. by manipulating the value in the w register, users can reach addresses that are fixed offsets from pointer addresses. in some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. 5.4.3.3 operations by fsrs on fsrs indirect addressing operations that target other fsrs or virtual registers represent special cases. for example, using an fsr to point to one of the virtual registers will not result in successful operations. as a specific case, assume that the fsr0h:fsr0l pair contains fe7h, the address of indf1. attempts to read the value of the indf1, using indf0 as an operand, will return 00h. attempts to write to indf1, using indf0 as the operand, will result in a nop . on the other hand, using the virtual registers to write to an fsr pair may not occur as planned. in these cases, the value will be written to the fsr pair but without any incrementing or decrementing. thus, writing to indf2 or postdec2 will write the same value to the fsr2h:fsr2l pair. since the fsrs are physical registers mapped in the sfr space, they can be manipulated through all direct operations. users should proceed cautiously when working on these registers, particularly if their code uses indirect addressing. similarly, operations by indirect addressing are gener- ally permitted on all other sfrs. users should exercise the appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 5.5 program memory and the extended instruction set the operation of program memory is unaffected by the use of the extended instruction set. enabling the extended instruction set adds five additional two-word commands to the existing pic18 instruction set: addfsr , callw , movsf , movss and subfsr . these instructions are executed as described in section 5.2.4 ?two-word instructions? . 5.6 data memory and the extended instruction set enabling the pic18 extended instruction set (xinst configuration bit = 1 ) significantly changes certain aspects of data memory and its addressing. specifically, the use of the access bank for many of the core pic18 instructions is different. this is due to the introduction of a new addressing mode for the data memory space. this mode also alters the behavior of indirect addressing using fsr2 and its associated operands. what does not change is just as important. the size of the data memory space is unchanged, as well as its linear addressing. the sfr map remains the same. core pic18 instructions can still operate in both direct and indirect addressing mode; inherent and literal instructions do not change at all. indirect addressing with fsr0 and fsr1 also remains unchanged. ? 2006 microchip technology inc. advance information ds39762a-page 91 pic18f97j60 family 5.6.1 indexed addressing with literal offset enabling the pic18 extended instruction set changes the behavior of indirect addressing using the fsr2 register pair and its associated file operands. under the proper conditions, instructions that use the access bank ? that is, most bit-oriented and byte-oriented instructions ? can invoke a form of indexed addressing using an offset specified in the instruction. this special addressing mode is known as indexed addressing with literal offset, or indexed literal offset mode. when using the extended instruction set, this addressing mode requires the following: ? the use of the access bank is forced (?a? = 0 ); and ? the file address argument is less than or equal to 5fh. under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the bsr in direct addressing) or as an 8-bit address in the access bank. instead, the value is interpreted as an offset value to an address pointer specified by fsr2. the offset and the contents of fsr2 are added to obtain the target address of the operation. 5.6.2 instructions affected by indexed literal offset mode any of the core pic18 instructions that can use direct addressing are potentially affected by the indexed literal offset addressing mode. this includes all byte-oriented and bit-oriented instructions, or almost half of the standard pic18 instruction set. instructions that only use inherent or literal addressing modes are unaffected. additionally, byte-oriented and bit-oriented instructions are not affected if they use the access bank (access ram bit is ? 1 ?) or include a file address of 60h or above. instructions meeting these criteria will continue to execute as before. a comparison of the different possible addressing modes when the extended instruction set is enabled is shown in figure 5-10. those who desire to use byte-oriented or bit-oriented instructions in the indexed literal offset mode should note the changes to assembler syntax for this mode. this is described in more detail in section 25.2.1 ?extended instruction syntax? . pic18f97j60 family ds39762a-page 92 advance information ? 2006 microchip technology inc. figure 5-10: comparing addressing options for bit-oriented and byte-oriented instructions (extended instruction set enabled) example instruction: addwf, f, d, a (opcode: 0010 01da ffff ffff ) when a = 0 and f 60h: the instruction executes in direct forced mode. ?f? is interpreted as a location in the access ram between 060h and fffh. this is the same as locations f60h to fffh (bank 15) of data memory. locations below 060h are not available in this addressing mode. when a = 0 and f 5fh: the instruction executes in indexed literal offset mode. ?f? is interpreted as an offset to the address value in fsr2. the two are added together to obtain the address of the target register for the instruction. the address can be anywhere in the data memory space. note that in this mode, the correct syntax is now: addwf [k], d where ?k? is the same as ?f?. when a = 1 (all values of f): the instruction executes in direct mode (also known as direct long mode). ?f? is interpreted as a location in one of the 16 banks of the data memory space. the bank is designated by the bank select register (bsr). the address can be in any implemented bank in the data memory space. 000h 060h 100h f00h f40h fffh valid range 00h 60h ffh data memory access ram bank 0 bank 1 through bank 14 bank 15 sfrs 000h 060h 100h f00h f40h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs fsr2h fsr2l ffffffff 001001da ffffffff 001001da 000h 060h 100h f00h f40h fffh data memory bank 0 bank 1 through bank 14 bank 15 sfrs for ?f? bsr 00000000 ? 2006 microchip technology inc. advance information ds39762a-page 93 pic18f97j60 family 5.6.3 mapping the access bank in indexed literal offset mode the use of indexed literal offset addressing mode effectively changes how the lower part of access ram (00h to 5fh) is mapped. rather than containing just the contents of the bottom part of bank 0, this mode maps the contents from bank 0 and a user-defined ?window? that can be located anywhere in the data memory space. the value of fsr2 establishes the lower boundary of the addresses mapped into the window, while the upper boundary is defined by fsr2 plus 95 (5fh). addresses in the access ram above 5fh are mapped as previously described (see section 5.3.2 ?access bank? ). an example of access bank remapping in this addressing mode is shown in figure 5-11. remapping of the access bank applies only to opera- tions using the indexed literal offset mode. operations that use the bsr (access ram bit is ? 1 ?) will continue to use direct addressing as before. any indirect or indexed operation that explicitly uses any of the indirect file operands (including fsr2) will continue to operate as standard indirect addressing. any instruction that uses the access bank, but includes a register address of greater than 05fh, will use direct addressing and the normal access bank map. 5.6.4 bsr in indexed literal offset mode although the access bank is remapped when the extended instruction set is enabled, the operation of the bsr remains unchanged. direct addressing, using the bsr to select the data memory bank, operates in the same manner as previously described. figure 5-11: remapping the access bank with indexed literal offset addressing data memory 000h 100h 200h f60h f00h fffh bank 1 bank 15 bank 2 through bank 14 sfrs 05fh addwf f, d, a fsr2h:fsr2l = 120h locations in the region from the fsr2 pointer (120h) to the pointer plus 05fh (17fh) are mapped to the bottom of the access ram (000h-05fh). special function regis- ters at f60h through fffh are mapped to 60h through ffh, as usual. bank 0 addresses below 5fh are not available in this mode. they can still be addressed by using the bsr. access bank 00h ffh bank 0 sfrs bank 1 ?window? not accessible window example situation: 120h 17fh 5fh 60h pic18f97j60 family ds39762a-page 94 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 95 pic18f97j60 family 6.0 flash program memory the flash program memory is readable, writable and erasable during normal operation over the entire v dd range. a read from program memory is executed on one byte at a time. a write to program memory is executed on blocks of 64 bytes at a time. program memory is erased in blocks of 1024 bytes at a time. a bulk erase operation may not be issued from user code. writing or erasing program memory will cease instruction fetches until the operation is complete. the program memory cannot be accessed during the write or erase, therefore, code cannot execute. an internal programming timer terminates program memory writes and erases. a value written to program memory does not need to be a valid instruction. executing a program memory location that forms an invalid instruction results in a nop . 6.1 table reads and table writes in order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data ram: ? table read ( tblrd ) ? table write ( tblwt ) the program memory space is 16 bits wide, while the data ram space is 8 bits wide. table reads and table writes move data between these two memory spaces through an 8-bit register (tablat). table read operations retrieve data from program memory and place it into the data ram space. figure 6-1 shows the operation of a table read with program memory and data ram. table write operations store data from the data memory space into holding registers in program memory. the procedure to write the contents of the holding registers into program memory is detailed in section 6.5 ?writing to flash program memory? . figure 6-2 shows the operation of a table write with program memory and data ram. table operations work with byte entities. a table block containing data, rather than program instructions, is not required to be word-aligned. therefore, a table block can start and end at any byte address. if a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. figure 6-1: table read operation table pointer (1) table latch (8-bit) program memory tblptrh tblptrl tablat tblptru instruction: tblrd * note 1: table pointer register points to a byte in program memory. program memory (tblptr) pic18f97j60 family ds39762a-page 96 advance information ? 2006 microchip technology inc. figure 6-2: table write operation 6.2 control registers several control registers are used in conjunction with the tblrd and tblwt instructions. these include the: ? eecon1 register ? eecon2 register ? tablat register ? tblptr registers 6.2.1 eecon1 and eecon2 registers the eecon1 register (register 6-1) is the control register for memory accesses. the eecon2 register is not a physical register; it is used exclusively in the memory write and erase sequences. reading eecon2 will read all ? 0 ?s. the free bit, when set, will allow a program memory erase operation. when free is set, the erase operation is initiated on the next wr command. when free is clear, only writes are enabled. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the wrerr bit is set in hardware when the wr bit is set, and cleared when the internal programming timer expires and the write operation is complete. the wr control bit initiates write operations. the bit cannot be cleared, only set, in software; it is cleared in hardware at the completion of the write operation. table pointer (1) table latch (8-bit) tblptrh tblptrl tablat program memory (tblptr) tblptru instruction: tblwt * note 1: table pointer actually points to one of 64 holding registers, the address of which is determined by tblptrl<5:0>. the process for physically writing data to the program memory array is discussed in section 6.5 ?writing to flash program memory? . holding registers program memory note: during normal operation, the wrerr is read as ? 1 ?. this can indicate that a write operation was prematurely terminated by a reset, or a write operation was attempted improperly. ? 2006 microchip technology inc. advance information ds39762a-page 97 pic18f97j60 family register 6-1: eecon1: eeprom control register 1 u-0 u-0 u-0 r/w-0 r/w-x r/w-0 r/s-0 u-0 ? ? ? free wrerr wren wr ? bit 7 bit 0 legend: s = settable bit r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 free: flash row erase enable bit 1 = erase the program memory row addressed by tblptr on the next wr command (cleared by completion of erase operation) 0 = perform write-only bit 3 wrerr: flash program error flag bit 1 = a write operation is prematurely terminated (any reset during self-timed programming in normal operation, or an improper write attempt) 0 = the write operation completed bit 2 wren: flash program write enable bit 1 = allows write cycles to flash program memory 0 = inhibits write cycles to flash program memory bit 1 wr: write control bit 1 = initiates a program memory erase cycle or write cycle. (the operation is self-timed and the bit is cleared by hardware once write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle complete bit 0 unimplemented: read as ? 0 ? pic18f97j60 family ds39762a-page 98 advance information ? 2006 microchip technology inc. 6.2.2 table latch register (tablat) the table latch (tablat) is an 8-bit register mapped into the sfr space. the table latch register is used to hold 8-bit data during data transfers between program memory and data ram. 6.2.3 table pointer register (tblptr) the table pointer (tblptr) register addresses a byte within the program memory. the tblptr is comprised of three sfr registers: table pointer upper byte, table pointer high byte and table pointer low byte (tblptru:tblptrh:tblptrl). these three regis- ters join to form a 22-bit wide pointer. the low-order 21 bits allow the device to address up to 2 mbytes of program memory space. the 22nd bit allows access to the device id and configuration bits. the table pointer register, tblptr, is used by the tblrd and tblwt instructions. these instructions can update the tblptr in one of four ways based on the table operation. these operations are shown in table 6-1. the table operations on the tblptr only affect the low-order 21 bits. 6.2.4 table pointer boundaries tblptr is used in reads, writes and erases of the flash program memory. when a tblrd is executed, all 22 bits of the tblptr determine which byte is read from program memory into tablat. when a tblwt is executed, the six lsbs of the table pointer register (tblptr<5:0>) determine which of the 64 program memory holding registers is written to. when the timed write to program memory begins (via the wr bit), the 15 msbs of the tblptr (tblptr<20:6>) determine which program memory block of 64 bytes is written to. for more detail, see section 6.5 ?writing to flash program memory? . when an erase of program memory is executed, the 11 msbs of the table pointer register (tblptr<20:10>) point to the 1024-byte block that will be erased. the least significant bits (tblptr<9:0>) are ignored. figure 6-3 describes the relevant boundaries of tblptr based on flash program memory operations. table 6-1: table pointer operations with tblrd and tblwt instructions figure 6-3: table pointer boundaries based on operation example operation on table pointer tblrd* tblwt* tblptr is not modified tblrd*+ tblwt*+ tblptr is incremented after the read/write tblrd*- tblwt*- tblptr is decremented after the read/write tblrd+* tblwt+* tblptr is incremented before the read/write 21 16 15 87 0 table write table read ? tblptr<21:0> tblptrl tblptrh tblptru tblptr<20:6> table erase tblptr<20:10> ? 2006 microchip technology inc. advance information ds39762a-page 99 pic18f97j60 family 6.3 reading the flash program memory the tblrd instruction is used to retrieve data from program memory and places it into data ram. table reads from program memory are performed one byte at a time. tblptr points to a byte address in program space. executing tblrd places the byte pointed to into tablat. in addition, tblptr can be modified automatically for the next table read operation. the internal program memory is typically organized by words. the least significant bit of the address selects between the high and low bytes of the word. figure 6-4 shows the interface between the internal program memory and the tablat. figure 6-4: reads from flash program memory example 6-1: reading a flash program memory word (even byte address) program memory (odd byte address) tblrd tablat tblptr = xxxxx1 fetch instruction register (ir) read register tblptr = xxxxx0 movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the word movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl read_word tblrd*+ ; read into tablat and increment movf tablat, w ; get data movwf word_even tblrd*+ ; read into tablat and increment movfw tablat, w ; get data movf word_odd pic18f97j60 family ds39762a-page 100 advance information ? 2006 microchip technology inc. 6.4 erasing flash program memory the minimum erase block is 1024 bytes. only through the use of an external programmer, or through icsp control, can larger blocks of program memory be bulk erased. word erase in the flash array is not supported. when initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased. the most significant 11 bits of the tblptr<20:10> point to the block being erased. tblptr<9:0> are ignored. the eecon1 register commands the erase operation. the wren bit must be set to enable write operations. the free bit is set to select an erase operation. for protection, the write initiate sequence for eecon2 must be used. a long write is necessary for erasing the internal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. 6.4.1 flash program memory erase sequence the sequence of events for erasing a block of internal program memory location is: 1. load table pointer register with address of row being erased. 2. set the eecon1 register for the erase operation: ? set wren bit to enable writes; ? set free bit to enable the erase. 3. disable interrupts. 4. write 55h to eecon2. 5. write 0aah to eecon2. 6. set the wr bit. this will begin the row erase cycle. 7. the cpu will stall for duration of the erase (about 2 ms using internal timer). 8. re-enable interrupts. example 6-2: erasing a flash program memory row movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl erase_row bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts required movlw 55h sequence movwf eecon2 ; write 55h movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts ? 2006 microchip technology inc. advance information ds39762a-page 101 pic18f97j60 family 6.5 writing to flash program memory the minimum programming block is 32 words or 64 bytes. word or byte programming is not supported. table writes are used internally to load the holding registers needed to program the flash memory. there are 64 holding registers used by the table writes for programming. since the table latch (tablat) is only a single byte, the tblwt instruction may need to be executed 64 times for each programming operation. all of the table write operations will essentially be short writes because only the holding registers are writte n. at the end of updating the 64 holding registers, the eecon1 register must be written to in order to st art the programming operation with a long write. the long write is necessary for programming the internal flash. instruction execution is halted while in a long write cycle. the long write will be terminated by the internal programming timer. the eeprom on-chip timer controls the write time. the write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. figure 6-5: table writes to flash program memory 6.5.1 flash program memory write sequence the sequence of events for programming an internal program memory location should be: 1. if the section of program memory to be written to has been programmed previously, then the memory will need to be erased before the write occurs (see 6.4.1 ?flash program memory erase sequence? ). 2. write the 64 bytes into the holding registers with auto-increment. 3. set the wren bit to enable byte writes. 4. disable interrupts. 5. write 55h to eecon2. 6. write aah to eecon2. 7. set the wr bit. this will begin the write cycle. 8. the cpu will stall for duration of the write (about 2 ms using internal timer). 9. re-enable interrupts. 10. verify the memory (table read). an example of the required code is shown in example 6-3. note 1: unlike previous picmicro devices, members of the pic18f97j60 family do not reset the holding registers after a write occurs. the holding registers must be cleared or overwritten before a programming sequence. 2: to maintain the endurance of the program memory cells, each flash byte should not be programmed more than one time between erase operations. before attempting to modify the contents of the target cell a second time, a row erase of the target row, or a bulk erase of the entire memory, must be performed. tablat tblptr = xxxx3f tblptr = xxxxx1 tblptr = xxxxx0 write register tblptr = xxxxx2 program memory holding register holding register holding register holding register 8 8 8 8 note: before setting the wr bit, the table pointer address needs to be within the intended address range of the 64 bytes in the holding register. pic18f97j60 family ds39762a-page 102 advance information ? 2006 microchip technology inc. example 6-3: writing to flash program memory movlw code_addr_upper ; load tblptr with the base movwf tblptru ; address of the memory block movlw code_addr_high movwf tblptrh movlw code_addr_low movwf tblptrl erase_block bsf eecon1, wren ; enable write to memory bsf eecon1, free ; enable row erase operation bcf intcon, gie ; disable interrupts movlw 55h movwf eecon2 ; write 55h movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start erase (cpu stall) bsf intcon, gie ; re-enable interrupts movlw d'16' movwf write_counter ; need to write 16 blocks of 64 to write ; one erase block of 1024 restart_buffer movlw d'64' movwf counter movlw buffer_addr_high ; point to buffer movwf fsr0h movlw buffer_addr_low movwf fsr0l fill_buffer ... ; read the new data from i2c, spi, ; psp, usart, etc. write_buffer movlw d?64 ; number of bytes in holding register movwf counter write_byte_to_hregs movff postinc0, wreg ; get low byte of buffer data movwf tablat ; present data to table latch tblwt+* ; write data, perform a short write ; to internal tblwt holding register. decfsz counter ; loop until buffers are full bra write_word_to_hregs program_memory bsf eecon1, wren ; enable write to memory bcf intcon, gie ; disable interrupts movlw 55h required movwf eecon2 ; write 55h sequence movlw 0aah movwf eecon2 ; write 0aah bsf eecon1, wr ; start program (cpu stall) bsf intcon, gie ; re-enable interrupts bcf eecon1, wren ; disable write to memory decfsz write_counter ; done with one write cycle bra restart_buffer ; if not done replacing the erase block ? 2006 microchip technology inc. advance information ds39762a-page 103 pic18f97j60 family 6.5.2 write verify depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. this should be used in applications where excessive writes can stress bits near the specification limit. 6.5.3 unexpected termination of write operation if a write is terminated by an unplanned event, such as loss of power or an unexpected reset, the memory location just programmed should be verified and repro- grammed if needed. if the write operation is interrupted by a mclr reset, or a wdt time-out reset during normal operation, the user can check the wrerr bit and rewrite the location(s) as needed. 6.5.4 protection against spurious writes to protect against spurious writes to flash program memory, the write initiate sequence must also be followed. see section 24.0 ?special features of the cpu? for more detail. 6.6 flash program operation during code protection see section 24.6 ?program verification and code protection? for details on code protection of flash program memory. table 6-2: registers associated with program flash memory name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page tblptru ? ? bit 21 program memory table pointer upper byte (tblptr<20:16>) 59 tbpltrh program memory table pointer high byte (tblptr<15:8>) 59 tblptrl program memory table pointer low byte (tblptr<7:0>) 59 tablat program memory table latch 59 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 eecon2 eeprom control register 2 (not a physical register) 61 eecon1 ? ? ? free wrerr wren wr ?61 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used during flash/eeprom access. pic18f97j60 family ds39762a-page 104 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 105 pic18f97j60 family 7.0 external memory bus the external memory bus allows the device to access external memory devices (such as flash, eprom, sram, etc.) as program or data memory. it supports both 8 and 16-bit data width modes and three address widths of up to 20 bits. the bus is implemented with 28 pins, multiplexed across four i/o ports. three ports (portd, porte and porth) are multiplexed with the address/data bus for a total of 20 available lines, while portj is multiplexed with the bus control signals. a list of the pins and their functions is provided in table 7-1. table 7-1: pic18f96j60/96j65/97j60 external bus ? i/o port functions note: the external memory bus is not implemented on 64-pin and 80-pin devices. name port bit external memory bus function rd0/ad0 portd 0 address bit 0 or data bit 0 rd1/ad1 portd 1 address bit 1 or data bit 1 rd2/ad2 portd 2 address bit 2 or data bit 2 rd3/ad3 portd 3 address bit 3 or data bit 3 rd4/ad4 portd 4 address bit 4 or data bit 4 rd5/ad5 portd 5 address bit 5 or data bit 5 rd6/ad6 portd 6 address bit 6 or data bit 6 rd7/ad7 portd 7 address bit 7 or data bit 7 re0/ad8 porte 0 address bit 8 or data bit 8 re1/ad9 porte 1 address bit 9 or data bit 9 re2/ad10 porte 2 address bit 10 or data bit 10 re3/ad11 porte 3 address bit 11 or data bit 11 re4/ad12 porte 4 address bit 12 or data bit 12 re5/ad13 porte 5 address bit 13 or data bit 13 re6/ad14 porte 6 address bit 14 or data bit 14 re7/ad15 porte 7 address bit 15 or data bit 15 rh0/a16 porth 0 address bit 16 rh1/a17 porth 1 address bit 17 rh2/a18 porth 2 address bit 18 rh3/a19 porth 3 address bit 19 rj0/ale portj 0 address latch enable (ale) control pin rj1/oe portj 1 output enable (oe ) control pin rj2/wrl portj 2 write low (wrl ) control pin rj3/wrh portj 3 write high (wrh ) control pin rj4/ba0 portj 4 byte address bit 0 (ba0) rj5/ce portj 5 chip enable (ce ) control pin rj6/lb portj 6 lower byte enable (lb ) control pin rj7/ub portj 7 upper byte enable (ub ) control pin note: for the sake of clarity, only i/o port and external bus assignments are shown here. one or more additional multiplexed features may be available on some pins. pic18f97j60 family ds39762a-page 106 advance information ? 2006 microchip technology inc. 7.1 external memory bus control the operation of the interface is controlled by the memcon register (register 7-1). this register is available in all program memory operating modes except microcontroller mode. in this mode, the register is disabled and cannot be written to. the ebdis bit (memcon<7>) controls the operation of the bus and related port functions. clearing ebdis enables the interface and disables the i/o functions of the ports, as well as any other functions multiplexed to those pins. setting the bit enables the i/o ports and other functions, but allows the interface to override everything else on the pins when an external memory operation is required. by default, the external bus is always enabled and disables all other i/o. the operation of the ebdis bit is also influenced by the program memory mode being used. this is discussed in more detail in section 7.5 ?program memory modes and the external memory bus? . the wait bits allow for the addition of wait states to external memory operations. the use of these bits is discussed in section 7.3 ?wait states? . the wm bits select the particular operating mode used when the bus is operating in 16-bit data width mode. these operating modes are discussed in more detail in section 7.6 ?16-bit data width modes? . the wm bits have no effect when an 8-bit data width mode is selected. register 7-1: memcon: external memory bus control register r/w-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ebdis ?wait1wait0 ? ?wm1wm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ebdis : external bus disable bit 1 = external bus enabled when microcontroller accesses external memory; otherwise, all external bus drivers are mapped as i/o ports 0 = external bus always enabled, i/o ports are disabled bit 6 unimplemented: read as ? 0 ? bit 5-4 wait1:wait0: table reads and writes bus cycle wait count bits 11 = table reads and writes will wait 0 t cy 10 = table reads and writes will wait 1 t cy 01 = table reads and writes will wait 2 t cy 00 = table reads and writes will wait 3 t cy bit 3-2 unimplemented: read as ? 0 ? bit 1-0 wm1:wm0: tblwt operation with 16-bit data bus width select bits 1x = word write mode: wrh active when tablat is written to and tblptr contains an odd address. when tblptr contains an even address, writing to tablat loads a holding latch with the value written. 01 = byte select mode: tablat data copied on both msb and lsb, wrh and (ub or lb ) will activate 00 = byte write mode: tablat data copied on both msb and lsb, wrh or wrl will activate ? 2006 microchip technology inc. advance information ds39762a-page 107 pic18f97j60 family 7.2 address and data width the pic18f97j60 family of devices can be indepen- dently configured for different address and data widths on the same memory bus. both address and data width are set by configuration bits in the config3l register. as configuration bits, this means that these options can only be configured by programming the device and are not controllable in software. the bw bit selects an 8-bit or 16-bit data bus width. setting this bit (default) selects a data width of 16 bits. the emb1:emb0 bits determine both the program memory operating mode and the address bus width. the available options are 20-bit, 16-bit and 12-bit, as well as the default microcontroller mode (external bus disabled). selecting a 16-bit or 12-bit width makes a corresponding number of high-order lines available for i/o functions. these pins are no longer affected by the setting of the ebdis bit. for example, selecting a 16-bit address mode (emb1:emb0 = 01 ) disables a19:a16 and allows the porth<3:0> bits to function without interruptions from the bus. using the smaller address widths allows users to tailor the memory bus to the size of the external memory space for a particular design while freeing up pins for dedicated i/o operation. because the emb bits have the effect of disabling pins for memory bus operations, it is important to always select an address width at least equal to the data width. if a 12-bit address width is used with a 16-bit data width, the upper four bits of data will not be available on the bus. all combinations of address and data widths require multiplexing of address and data information on the same lines. the address and data multiplexing, as well as i/o ports made available by the use of smaller address widths, are summarized in table 7-2. 7.2.1 address shifting on the external bus by default, the address presented on the external bus is the value of the pc. in practical terms, this means that addresses in the external memory device below the top of on-chip memory are unavailable to the micro- controller. to access these physical locations, the glue logic between the microcontroller and the external memory must somehow translate addresses. to simplify the interface, the external bus offers an extension of extended microcontroller mode that automatically performs address shifting. this feature is controlled by the eashft configuration bit. setting this bit offsets addresses on the bus by the size of the microcontroller?s on-chip program memory and sets the bottom address at 0000h. this allows the device to use the entire range of physical addresses of the external memory. 7.2.2 21-bit addressing as an extension of 20-bit address width operation, the external memory bus can also fully address a 2-mbyte memory space. this is done by using the bus address bit 0 (ba0) control line as the least significant bit of the address. the ub and lb control signals may also be used with certain memory devices to select the upper and lower bytes within a 16-bit wide data word. this addressing mode is available in both 8-bit data width and certain 16-bit data width modes. additional details are provided in section 7.6.3 ?16-bit byte select mode? and section 7.7 ?8-bit data width mode? . table 7-2: address and data lines for different address and data widths data width address width multiplexed data and address lines (and corresponding ports) address-only lines (and corresponding ports) ports available for i/o 8-bit 12-bit ad7:ad0 (portd<7:0>) ad11:ad8 (porte<3:0>) porte<7:4>, all of porth 16-bit ad15:ad8 (porte<7:0>) all of porth 20-bit a19:a16, ad15:ad8 (porth<3:0>, porte<7:0>) ? 16-bit 16-bit ad15:ad0 (portd<7:0>, porte<7:0>) ? all of porth 20-bit a19:a16 (porth<3:0>) ? pic18f97j60 family ds39762a-page 108 advance information ? 2006 microchip technology inc. 7.3 wait states while it may be assumed that external memory devices will operate at the microcontroller clock rate, this is often not the case. in fact, many devices require longer times to write or retrieve data than the time allowed by the execution of table read or table write operations. to compensate for this, the external memory bus can be configured to add a fixed delay to each table opera- tion using the bus. wait states are enabled by setting the wait configuration bit. when enabled, the amount of delay is set by the wait1:wait0 bits (memcon<5:4>). the delay is based on multiples of microcontroller instruction cycle time and are added following the instruction cycle when the table operation is executed. the range is from no delay to 3 t cy (default value). 7.4 port pin weak pull-ups with the exception of the upper address lines, a19:a16, the pins associated with the external memory bus are equipped with weak pull-ups. the pull-ups are controlled by the upper three bits of the portg register. they are named rdpu, repu and rjpu and control pull-ups on portd, porte and portj, respectively. setting one of these bits enables the corresponding pull-ups for that port. all pull-ups are disabled by default on all device resets. 7.5 program memory modes and the external memory bus the pic18f97j60 family of devices is capable of operating in one of two program memory modes, using combinations of on-chip and external program memory. the functions of the multiplexed port pins depend on the program memory mode selected, as well as the setting of the ebdis bit. in microcontroller mode, the bus is not active and the pins have their port functions only. writes to the memcom register are not permitted. the reset value of ebdis (? 0 ?) is ignored and the emb pins behave as i/o ports. in extended microcontroller mode, the external program memory bus shares i/o port functions on the pins. when the device is fetching or doing table read/table write operations on the external program memory space, the pins will have the external bus function. if the device is fetching and accessing internal program memory locations only, the ebdis control bit will change the pins from external memory to i/o port functions. when ebdis = 0 , the pins function as the external bus. when ebdis = 1 , the pins function as i/o ports. if the device fetches or accesses external memory while ebdis = 1 , the pins will switch to the external bus. if the ebdis bit is set by a program executing from external memory, the action of setting the bit will be delayed until the program branches into the internal memory. at that time, the pins will change from external bus to i/o ports. if the device is executing out of internal memory when ebdis = 0 , the memory bus address/data and control pins will not be active. they will go to a state where the active address/data pins are tri-state; the ce , oe , wrh , wrl , ub and lb signals are ? 1 ? and ale and ba0 are ? 0 ?. note that only those pins associated with the current address width are forced to tri-state; the other pins continue to function as i/o. in the case of 16-bit address width, for example, only ad<15:0> (portd and porte) are affected; a19:a16 (porth<3:0>) continue to function as i/o. in all external memory modes, the bus takes priority over any other peripherals that may share pins with it. this includes the parallel slave port and serial com- munication modules which would otherwise take priority over the i/o port. 7.6 16-bit data width modes in 16-bit data width mode, the external memory interface can be connected to external memories in three different configurations: ? 16-bit byte write ? 16-bit word write ? 16-bit byte select the configuration to be used is determined by the wm1:wm0 bits in the memcon register (memcon<1:0>). these three different configurations allow the designer maximum flexibility in using both 8-bit and 16-bit devices with 16-bit data. for all 16-bit data width modes, the address latch enable (ale) pin indicates that the address bits, ad<15:0>, are available on the external memory inter- face bus. following the address latch, the output enable signal (oe ) will enable both bytes of program memory at once to form a 16-bit instruction word. the chip enable signal (ce ) is active at any time that the microcontroller accesses external memory, whether reading or writing. it is inactive (asserted high) whenever the device is in sleep mode. in byte select mode, jedec standard flash memories will require ba0 for the byte address line and one i/o line to select between byte and word mode. the other 16-bit data width modes do not need ba0. jedec standard, static ram memories will use the ub or lb signals for byte selection. ? 2006 microchip technology inc. advance information ds39762a-page 109 pic18f97j60 family 7.6.1 16-bit byte write mode figure 7-1 shows an example of 16-bit byte write mode for pic18f97j60 family devices. this mode is used for two separate 8-bit memories connected for 16-bit operation. this generally includes basic eprom and flash devices. it allows table writes to byte-wide external memories. during a tblwt instruction cycle, the tablat data is presented on the upper and lower bytes of the ad15:ad0 bus. the appropriate wrh or wrl control line is strobed on the lsb of the tblptr. figure 7-1: 16-bit byte write mode example ad<7:0> a<19:16> (1) ale d<15:8> 373 a pic18f97j60 family ds39762a-page 110 advance information ? 2006 microchip technology inc. 7.6.2 16-bit word write mode figure 7-2 shows an example of 16-bit word write mode for pic18f97j60 devices. this mode is used for word-wide memories which include some of the eprom and flash type memories. this mode allows opcode fetches and table reads from all forms of 16-bit memory, and table writes to any type of word-wide external memories. this method makes a distinction between tblwt cycles to even or odd addresses. during a tblwt cycle to an even address (tblptr<0> = 0 ), the tablat data is transferred to a holding latch and the external address data bus is tri-stated for the data portion of the bus cycle. no write signals are activated. during a tblwt cycle to an odd address (tblptr<0> = 1 ), the tablat data is presented on the upper byte of the ad15:ad0 bus. the contents of the holding latch are presented on the lower byte of the ad15:ad0 bus. the wrh signal is strobed for each write cycle; the wrl pin is unused. the signal on the ba0 pin indicates the lsb of the tblptr but it is left unconnected. instead, the ub and lb signals are active to select both bytes. the obvious limitation to this method is that the table write must be done in pairs on a specific word boundary to correctly write a word location. figure 7-2: 16-bit word write mode example ad<7:0> pic18f97j60 ad<15:8> ale 373 a<20:1> 373 oe wrh a<19:16> (1) a ? 2006 microchip technology inc. advance information ds39762a-page 111 pic18f97j60 family 7.6.3 16-bit byte select mode figure 7-3 shows an example of 16-bit byte select mode. this mode allows table write operations to word-wide external memories with byte selection capability. this generally includes both word-wide flash and sram devices. during a tblwt cycle, the tablat data is presented on the upper and lower byte of the ad15:ad0 bus. the wrh signal is strobed for each write cycle; the wrl pin is not used. the ba0 or ub /lb signals are used to select the byte to be written based on the least significant bit of the tblptr register. flash and sram devices use different control signal combinations to implement byte select mode. jedec standard flash memories require that a controller i/o port pin be connected to the memory?s byte/word pin to provide the select signal. they also use the ba0 signal from the controller as a byte address. jedec standard, static ram memories, on the other hand, use the ub or lb signals to select the byte. figure 7-3: 16-bit byte select mode example ad<7:0> pic18f97j60 ad<15:8> ale 373 a<20:1> 373 oe wrh a<19:16> (2) ba0 jedec word a pic18f97j60 family ds39762a-page 112 advance information ? 2006 microchip technology inc. 7.6.4 16-bit mode timing the presentation of control signals on the external memory bus is different for the various operating modes. typical signal timing diagrams are shown in figure 7-4 and figure 7-5. figure 7-4: external me mory bus timing for tblrd (extended microcontroller mode) figure 7-5: external memory bus timing for sleep (extended microcontroller mode) q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe ad<15:0> ce opcode fetch opcode fetch opcode fetch tblrd * tblrd cycle 1 addlw 55h from 000100h q2 q1 q3 q4 0ch cf33h tblrd 92h from 199e67h 9256h from 000104h memory cycle instruction execution inst(pc ? 2) tblrd cycle 2 movlw 55h from 000102h movlw q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe 3aaah ad<15:0> 00h 00h ce opcode fetch opcode fetch sleep sleep from 007554h q1 bus inactive 0003h 3aabh 0e55h memory cycle instruction execution inst(pc ? 2) sleep mode, movlw 55h from 007556h ? 2006 microchip technology inc. advance information ds39762a-page 113 pic18f97j60 family 7.7 8-bit data width mode in 8-bit data width mode, the external memory bus operates only in multiplexed mode; that is, data shares the eight least significant bits of the address bus. figure 7-6 shows an example of 8-bit multiplexed mode for 100-pin devices. this mode is used for a single 8-bit memory connected for 16-bit operation. the instructions will be fetched as two 8-bit bytes on a shared data/address bus. the two bytes are sequentially fetched within one instruction cycle (t cy ). therefore, the designer must choose external memory devices accord- ing to timing calculations based on 1/2 t cy (2 times the instruction rate). for proper memory speed selection, glue logic propagation delay times must be considered, along with setup and hold times. the address latch enable (ale) pin indicates that the address bits, ad<15:0>, are available on the external memory interface bus. the output enable signal (oe ) will enable one byte of program memory for a portion of the instruction cycle, then ba0 will change and the second byte will be enabled to form the 16-bit instruc- tion word. the least significant bit of the address, ba0, must be connected to the memory devices in this mode. the chip enable signal (ce ) is active at any time that the microcontroller accesses external memory, whether reading or writing. it is inactive (asserted high) whenever the device is in sleep mode. this process generally includes basic eprom and flash devices. it allows table writes to byte-wide external memories. during a tblwt instruction cycle, the tablat data is presented on the upper and lower bytes of the ad15:ad0 bus. the appropriate level of the ba0 control line is strobed on the lsb of the tblptr. figure 7-6: 8-bit multiplexed mode example ad<7:0> a<19:16> (1) ale d<15:8> 373 a<19:0> a pic18f97j60 family ds39762a-page 114 advance information ? 2006 microchip technology inc. 7.7.1 8-bit mode timing the presentation of control signals on the external memory bus is different for the various operating modes. typical signal timing diagrams are shown in figure 7-7 and figure 7-8. figure 7-7: external me mory bus timing for tblrd (extended microcontroller mode) figure 7-8: external memory bus timing for sleep (extended microcontroller mode) q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe ad<7:0> ce opcode fetch opcode fetch opcode fetch tblrd * tblrd cycle 1 addlw 55h from 000100h q2 q1 q3 q4 0ch 33h tblrd 92h from 199e67h 92h from 000104h memory cycle instruction execution inst(pc ? 2) tblrd cycle 2 movlw 55h from 000102h movlw ad<15:8> cfh q2 q1 q3 q4 q2 q1 q3 q4 a<19:16> ale oe aah ad<7:0> 00h 00h ce opcode fetch opcode fetch sleep sleep from 007554h q1 bus inactive 00h abh 55h memory cycle instruction execution inst(pc ? 2) sleep mode, movlw 55h from 007556h ad<15:8> 3ah 3ah 03h 0eh ba0 ? 2006 microchip technology inc. advance information ds39762a-page 115 pic18f97j60 family 7.8 operation in power-managed modes in alternate power-managed run modes, the external bus continues to operate normally. if a clock source with a lower speed is selected, bus operations will run at that speed. in these cases, excessive access times for the external memory may result if wait states have been enabled and added to external memory operations. if operations in a lower power run mode are anticipated, user applications should provide memory access time adjustments at the lower clock speeds. in sleep and idle modes, the microcontroller core does not need to access data; bus operations are suspended. the state of the external bus is frozen, with the address/data pins and most of the control pins holding at the same state they were in when the mode was invoked. the only potential changes are the ce , lb and ub pins, which are held at logic high. pic18f97j60 family ds39762a-page 116 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 117 pic18f97j60 family 8.0 8 x 8 hardware multiplier 8.1 introduction all pic18 devices include an 8 x 8 hardware multiplier as part of the alu. the multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, prodh:prodl. the multiplier?s operation does not affect any flags in the status register. making multiplication a hardware operation allows it to be completed in a single instruction cycle. this has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the pic18 devices to be used in many applica- tions previously reserved for digital signal processors. a comparison of various hardware and software multiply operations, along with the savings in memory and execution time, is shown in table 8-1. 8.2 operation example 8-1 shows the instruction sequence for an 8 x 8 unsigned multiplication. only one instruction is required when one of the arguments is already loaded in the wreg register. example 8-2 shows the sequence to do an 8 x 8 signed multiplication. to account for the sign bits of the argu- ments, each argument?s most significant bit (msb) is tested and the appropriate subtractions are done. example 8-1: 8 x 8 unsigned multiply routine example 8-2: 8 x 8 signed multiply routine table 8-1: performance comparison for various multiply operations movf arg1, w ; mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl movf arg1, w mulwf arg2 ; arg1 * arg2 -> ; prodh:prodl btfsc arg2, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg1 movf arg2, w btfsc arg1, sb ; test sign bit subwf prodh, f ; prodh = prodh ; - arg2 routine multiply method program memory (words) cycles (max) time @ 40 mhz @ 10 mhz @ 4 mhz 8 x 8 unsigned without hardware multiply 13 69 6.9 s27.6 s69 s hardware multiply 1 1 100 ns 400 ns 1 s 8 x 8 signed without hardware multiply 33 91 9.1 s36.4 s91 s hardware multiply 6 6 600 ns 2.4 s6 s 16 x 16 unsigned without hardware multiply 21 242 24.2 s96.8 s 242 s hardware multiply 28 28 2.8 s 11.2 s28 s 16 x 16 signed without hardware multiply 52 254 25.4 s 102.6 s 254 s hardware multiply 35 40 4.0 s16.0 s40 s pic18f97j60 family ds39762a-page 118 advance information ? 2006 microchip technology inc. example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. equation 8-1 shows the algorithm that is used. the 32-bit result is stored in four registers (res3:res0). equation 8-1: 16 x 16 unsigned multiplication algorithm example 8-3: 16 x 16 unsigned multiply routine example 8-4 shows the sequence to do a 16 x 16 signed multiply. equation 8-2 shows the algorithm used. the 32-bit result is stored in four registers (res3:res0). to account for the sign bits of the arguments, the msb for each argument pair is tested and the appropriate subtractions are done. equation 8-2: 16 x 16 signed multiplication algorithm example 8-4: 16 x 16 signed multiply routine res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) movf arg1l, w mulwf arg2l ; arg1l * arg2l-> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h-> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l-> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; res3:res0 = arg1h:arg1l ? arg2h:arg2l = (arg1h ? arg2h ? 2 16 ) + (arg1h ? arg2l ? 2 8 ) + (arg1l ? arg2h ? 2 8 ) + (arg1l ? arg2l) + (-1 ? arg2h<7> ? arg1h:arg1l ? 2 16 ) + (-1 ? arg1h<7> ? arg2h:arg2l ? 2 16 ) movf arg1l, w mulwf arg2l ; arg1l * arg2l -> ; prodh:prodl movff prodh, res1 ; movff prodl, res0 ; ; movf arg1h, w mulwf arg2h ; arg1h * arg2h -> ; prodh:prodl movff prodh, res3 ; movff prodl, res2 ; ; movf arg1l, w mulwf arg2h ; arg1l * arg2h -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; movf arg1h, w ; mulwf arg2l ; arg1h * arg2l -> ; prodh:prodl movf prodl, w ; addwf res1, f ; add cross movf prodh, w ; products addwfc res2, f ; clrf wreg ; addwfc res3, f ; ; btfss arg2h, 7 ; arg2h:arg2l neg? bra sign_arg1 ; no, check arg1 movf arg1l, w ; subwf res2 ; movf arg1h, w ; subwfb res3 ; sign_arg1 btfss arg1h, 7 ; arg1h:arg1l neg? bra cont_code ; no, done movf arg2l, w ; subwf res2 ; movf arg2h, w ; subwfb res3 ; cont_code : ? 2006 microchip technology inc. advance information ds39762a-page 119 pic18f97j60 family 9.0 interrupts members of the pic18f97j60 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. the high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. high priority interrupt events will interrupt any low priority interrupts that may be in progress. there are thirteen registers which are used to control interrupt operation. these registers are: ? rcon ?intcon ? intcon2 ? intcon3 ? pir1, pir2, pir3 ? pie1, pie2, pie3 ? ipr1, ipr2, ipr3 it is recommended that the microchip header files supplied with mplab ? ide be used for the symbolic bit names in these registers. this allows the assembler/compiler to automatically take care of the placement of these bits within the specified register. in general, interrupt sources have three bits to control their operation. they are: ? flag bit to indicate that an interrupt event occurred ? enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set ? priority bit to select high priority or low priority the interrupt priority feature is enabled by setting the ipen bit (rcon<7>). when interrupt priority is enabled, there are two bits which enable interrupts globally. setting the gieh bit (intcon<7>) enables all interrupts that have the priority bit set (high priority). setting the giel bit (intcon<6>) enables all interrupts that have the priority bit cleared (low priority). when the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 0008h or 0018h, depending on the priority bit setting. individual interrupts can be disabled through their corresponding enable bits. when the ipen bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with picmicro ? mid-range devices. in compatibility mode, the interrupt priority bits for each source have no effect. intcon<6> is the peie bit which enables/disables all peripheral interrupt sources. intcon<7> is the gie bit which enables/disables all interrupt sources. all interrupts branch to address 0008h in compatibility mode. when an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. if the ipen bit is cleared, this is the gie bit. if interrupt priority levels are used, this will be either the gieh or giel bit. high priority interrupt sources can interrupt a low priority interrupt. low priority interrupts are not processed while high priority interrupts are in progress. the return address is pushed onto the stack and the pc is loaded with the interrupt vector address (0008h or 0018h). once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. the interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. the ?return from interrupt? instruction, retfie , exits the interrupt routine and sets the gie bit (gieh or giel if priority levels are used) which re-enables interrupts. for external interrupt events, such as the int pins or the portb input change interrupt, the interrupt latency will be three to four instruction cycles. the exact latency is the same for one or two-cycle instructions. individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the gie bit. note: do not use the movff instruction to modify any of the interrupt control registers while any interrupt is enabled. doing so may cause erratic microcontroller behavior. pic18f97j60 family ds39762a-page 120 advance information ? 2006 microchip technology inc. figure 9-1: pic18f97j60 family interrupt logic tmr0ie gie/gieh peie/giel wake-up if in interrupt to cpu vector to location 0008h int2if int2ie int2ip int1if int1ie int1ip tmr0if tmr0ie tmr0ip rbif rbie rbip ipen tmr0if tmr0ip int1if int1ie int1ip int2if int2ie int2ip rbif rbie rbip int0if int0ie peie/giel interrupt to cpu vector to location ipen ipen 0018h pir1<7:0> pie1<7:0> ipr1<7:0> high priority interrupt generation low priority interrupt generation idle or sleep modes gie/gieh int3if int3ie int3ip int3if int3ie int3ip pir2<7:5,3,1:0> pie2<7:5,3,1:0> ipr2<7:5,3,1:0> pir3<7:0> pie3<7:0> ipr3<7:0> pir1<7:0> pie1<7:0> ipr1<7:0> pir2<7:5,3,1:0> pie2<7:5,3,1:0> ipr2<7: 5, 3, 1 :0> pir3<7:0> pie3<7:0> ipr3<7 :0 > ipen ? 2006 microchip technology inc. advance information ds39762a-page 121 pic18f97j60 family 9.1 intcon registers the intcon registers are readable and writable registers which contain various enable, priority and flag bits. note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. register 9-1: intcon: interrupt control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gie/gieh: global interrupt enable bit when ipen = 0 : 1 = enables all unmasked interrupts 0 = disables all interrupts when ipen = 1 : 1 = enables all high priority interrupts 0 = disables all interrupts bit 6 peie/giel: peripheral interrupt enable bit when ipen = 0 : 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts when ipen = 1 : 1 = enables all low priority peripheral interrupts 0 = disables all low priority peripheral interrupts bit 5 tmr0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 overflow interrupt 0 = disables the tmr0 overflow interrupt bit 4 int0ie: int0 external interrupt enable bit 1 = enables the int0 external interrupt 0 = disables the int0 external interrupt bit 3 rbie: rb port change interrupt enable bit 1 = enables the rb port change interrupt 0 = disables the rb port change interrupt bit 2 tmr0if: tmr0 overflow interrupt flag bit 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 int0if: int0 external interrupt flag bit 1 = the int0 external interrupt occurred (must be cleared in software) 0 = the int0 external interrupt did not occur bit 0 rbif: rb port change interrupt flag bit (1) 1 = at least one of the rb7:rb4 pins changed state (must be cleared in software) 0 = none of the rb7:rb4 pins have changed state note 1: a mismatch condition will continue to set this bit. reading portb will end the mismatch condition and allow the bit to be cleared. pic18f97j60 family ds39762a-page 122 advance information ? 2006 microchip technology inc. register 9-2: intcon2: interrupt control register 2 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rbpu : portb pull-up enable bit 1 = all portb pull-ups are disabled 0 = portb pull-ups are enabled by individual port latch values bit 6 intedg0: external interrupt 0 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 5 intedg1: external interrupt 1 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 4 intedg2: external interrupt 2 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 3 intedg3: external interrupt 3 edge select bit 1 = interrupt on rising edge 0 = interrupt on falling edge bit 2 tmr0ip: tmr0 overflow interrupt priority bit 1 = high priority 0 = low priority bit 1 int3ip: int3 external interrupt priority bit 1 = high priority 0 = low priority bit 0 rbip: rb port change interrupt priority bit 1 = high priority 0 = low priority note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. ? 2006 microchip technology inc. advance information ds39762a-page 123 pic18f97j60 family register 9-3: intcon3: interrupt control register 3 r/w-1 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 int2ip: int2 external interrupt priority bit 1 = high priority 0 = low priority bit 6 int1ip: int1 external interrupt priority bit 1 = high priority 0 = low priority bit 5 int3ie: int3 external interrupt enable bit 1 = enables the int3 external interrupt 0 = disables the int3 external interrupt bit 4 int2ie: int2 external interrupt enable bit 1 = enables the int2 external interrupt 0 = disables the int2 external interrupt bit 3 int1ie: int1 external interrupt enable bit 1 = enables the int1 external interrupt 0 = disables the int1 external interrupt bit 2 int3if: int3 external interrupt flag bit 1 = the int3 external interrupt occurred (must be cleared in software) 0 = the int3 external interrupt did not occur bit 1 int2if: int2 external interrupt flag bit 1 = the int2 external interrupt occurred (must be cleared in software) 0 = the int2 external interrupt did not occur bit 0 int1if: int1 external interrupt flag bit 1 = the int1 external interrupt occurred (must be cleared in software) 0 = the int1 external interrupt did not occur note: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. pic18f97j60 family ds39762a-page 124 advance information ? 2006 microchip technology inc. 9.2 pir registers the pir registers contain the individual flag bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt request (flag) registers (pir1, pir2, pir3). note 1: interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie (intcon<7>). 2: user software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. register 9-4: pir1: peripheral interrupt request (flag) register 1 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 pspif (1) adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pspif: parallel slave port read/write interrupt flag bit (1) 1 = a read or a write operation has taken place (must be cleared in software) 0 = no read or write has occurred bit 6 adif: a/d converter interrupt flag bit 1 = an a/d conversion completed (must be cleared in software) 0 = the a/d conversion is not complete bit 5 rc1if: eusart1 receive interrupt flag bit 1 = the eusart1 receive buffer, rcreg1, is full (cleared when rcreg1 is read) 0 = the eusart1 receive buffer is empty bit 4 tx1if: eusart1 transmit interrupt flag bit 1 = the eusart1 transmit buffer, txreg1, is empty (cleared when txreg1 is written) 0 = the eusart1 transmit buffer is full bit 3 ssp1if: master synchronous serial port 1 interrupt flag bit 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 2 ccp1if: eccp1 interrupt flag bit capture mode: 1 = a tmr1 register capture occurred (must be cleared in software) 0 = no tmr1 register capture occurred compare mode: 1 = a tmr1 register compare match occurred (must be cleared in software) 0 = no tmr1 register compare match occurred pwm mode: unused in this mode. bit 1 tmr2if: tmr2 to pr2 match interrupt flag bit 1 = tmr2 to pr2 match occurred (must be cleared in software) 0 = no tmr2 to pr2 match occurred bit 0 tmr1if: tmr1 overflow interrupt flag bit 1 = tmr1 register overflowed (must be cleared in software) 0 = tmr1 register did not overflow note 1: implemented in 100-pin devices in microcontroller mode only. ? 2006 microchip technology inc. advance information ds39762a-page 125 pic18f97j60 family register 9-5: pir2: peripheral interrupt request (flag) register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 oscfif cmif ethif r bcl1if ? tmr3if ccp2if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 oscfif: oscillator fail interrupt flag bit 1 = system oscillator failed, clock input has changed to intrc (must be cleared in software) 0 = system clock operating bit 6 cmif: comparator interrupt flag bit 1 = comparator input has changed (must be cleared in software) 0 = comparator input has not changed bit 5 ethif: ethernet module interrupt flag bit 1 = an ethernet module interrupt event has occurred; query eir register to resolve source 0 = no ethernet interrupt event has occurred bit 4 reserved: maintain as ? 0 ? bit 3 bcl1if: bus collision interrupt flag bit (mssp1 module) 1 = a bus collision occurred (must be cleared in software) 0 = no bus collision occurred bit 2 unimplemented: read as ? 0 ? bit 1 tmr3if: tmr3 overflow interrupt flag bit 1 = tmr3 register overflowed (must be cleared in software) 0 = tmr3 register did not overflow bit 0 ccp2if: eccp2 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. pic18f97j60 family ds39762a-page 126 advance information ? 2006 microchip technology inc. register 9-6: pir3: peripheral interrupt request (flag) register 3 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ssp2if (1) bcl2if (1) rc2if (2) tx2if (2) tmr4if ccp5if ccp4if ccp3if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ssp2if: master synchronous serial port 2 interrupt flag bit (1) 1 = the transmission/reception is complete (must be cleared in software) 0 = waiting to transmit/receive bit 6 bcl2if: bus collision interrupt flag bit (mssp2 module) (1) 1 = a bus collision occurred (must be cleared in software) 0 = no bus collision occurred bit 5 rc2if: eusart2 receive interrupt flag bit (2) 1 = the eusart2 receive buffer, rcreg2, is full (cleared when rcreg2 is read) 0 = the eusart2 receive buffer is empty bit 4 tx2if: eusart2 transmit interrupt flag bit (2) 1 = the eusart2 transmit buffer, txreg2, is empty (cleared when txreg2 is written) 0 = the eusart2 transmit buffer is full bit 3 tmr4if: tmr4 to pr4 match interrupt flag bit 1 = tmr4 to pr4 match occurred (must be cleared in software) 0 = no tmr4 to pr4 match occurred bit 2 ccp5if: ccp5 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. bit 1 ccp4if: ccp4 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. bit 0 ccp3if: eccp3 interrupt flag bit capture mode: 1 = a tmr1/tmr3 register capture occurred (must be cleared in software) 0 = no tmr1/tmr3 register capture occurred compare mode: 1 = a tmr1/tmr3 register compare match occurred (must be cleared in software) 0 = no tmr1/tmr3 register compare match occurred pwm mode: unused in this mode. note 1: implemented in 100-pin devices only. 2: implemented in 80-pin and 100-pin devices only. ? 2006 microchip technology inc. advance information ds39762a-page 127 pic18f97j60 family 9.3 pie registers the pie registers contain the individual enable bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt enable registers (pie1, pie2, pie3). when ipen = 0 , the peie bit must be set to enable any of these peripheral interrupts. register 9-7: pie1: peripheral interrupt enable register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pspie (1) adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pspie: parallel slave port read/write interrupt enable bit (1) 1 = enabled 0 = disabled bit 6 adie: a/d converter interrupt enable bit 1 = enabled 0 =disabled bit 5 rc1ie: eusart1 receive interrupt enable bit 1 = enabled 0 =disabled bit 4 tx1ie: eusart1 transmit interrupt enable bit 1 = enabled 0 =disabled bit 3 ssp1ie: master synchronous serial port 1 interrupt enable bit 1 = enabled 0 = disabled bit 2 ccp1ie: eccp1 interrupt enable bit 1 = enabled 0 =disabled bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enabled 0 = disabled bit 0 tmr1ie: tmr1 overflow interrupt enable bit 1 = enabled 0 =disabled note 1: implemented in 100-pin devices in microcontroller mode only. pic18f97j60 family ds39762a-page 128 advance information ? 2006 microchip technology inc. register 9-8: pie2: peripheral interrupt enable register 2 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 oscfie cmie ethie r bcl1ie ? tmr3ie ccp2ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 oscfie: oscillator fail interrupt enable bit 1 = enabled 0 =disabled bit 6 cmie: comparator interrupt enable bit 1 = enabled 0 = disabled bit 5 ethie: ethernet module interrupt enable bit 1 = enabled 0 = disabled bit 4 reserved: maintain as ? 0 ? bit 3 bcl1ie: bus collision interrupt enable bit (mssp1 module) 1 = enabled 0 =disabled bit 2 unimplemented: read as ? 0 ? bit 1 tmr3ie: tmr3 overflow interrupt enable bit 1 = enabled 0 =disabled bit 0 ccp2ie: eccp2 interrupt enable bit 1 = enabled 0 =disabled ? 2006 microchip technology inc. advance information ds39762a-page 129 pic18f97j60 family register 9-9: pie3: peripheral interrupt enable register 3 r/w-0 r/w-0 r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ssp2ie (1) bcl2ie (1) rc2ie (2) tx2ie (2) tmr4ie ccp5ie ccp4ie ccp3ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ssp2ie: master synchronous serial port 2 interrupt enable bit (1) 1 = enabled 0 =disabled bit 6 bcl2ie: bus collision interrupt enable bit (mssp2 module) (1) 1 = enabled 0 =disabled bit 5 rc2ie: eusart2 receive interrupt enable bit (2) 1 = enabled 0 =disabled bit 4 tx2ie: eusart2 transmit interrupt enable bit (2) 1 = enabled 0 =disabled bit 3 tmr4ie: tmr4 to pr4 match interrupt enable bit 1 = enabled 0 =disabled bit 2 ccp5ie: ccp5 interrupt enable bit 1 = enabled 0 =disabled bit 1 ccp4ie: ccp4 interrupt enable bit 1 = enabled 0 =disabled bit 0 ccp3ie: eccp3 interrupt enable bit 1 = enabled 0 =disabled note 1: implemented in 100-pin devices only. 2: implemented in 80-pin and 100-pin devices only. pic18f97j60 family ds39762a-page 130 advance information ? 2006 microchip technology inc. 9.4 ipr registers the ipr registers contain the individual priority bits for the peripheral interrupts. due to the number of peripheral interrupt sources, there are three peripheral interrupt priority registers (ipr1, ipr2, ipr3). using the priority bits requires that the interrupt priority enable (ipen) bit be set. register 9-10: ipr1: peripheral interrupt priority register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 pspip (1) adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pspip: parallel slave port read/write interrupt priority bit (1) 1 = high priority 0 = low priority bit 6 adip: a/d converter interrupt priority bit 1 = high priority 0 = low priority bit 5 rc1ip: eusart1 receive interrupt priority bit 1 = high priority 0 = low priority bit 4 tx1ip: eusart1 transmit interrupt priority bit 1 = high priority 0 = low priority bit 3 ssp1ip: master synchronous serial port 1 interrupt priority bit 1 = high priority 0 = low priority bit 2 ccp1ip: eccp1 interrupt priority bit 1 = high priority 0 = low priority bit 1 tmr2ip: tmr2 to pr2 match interrupt priority bit 1 = high priority 0 = low priority bit 0 tmr1ip: tmr1 overflow interrupt priority bit 1 = high priority 0 = low priority note 1: implemented in 100-pin devices in microcontroller mode only. ? 2006 microchip technology inc. advance information ds39762a-page 131 pic18f97j60 family register 9-11: ipr2: peripheral interrupt priority register 2 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 u-0 r/w-1 r/w-1 oscfip cmip ethip r bcl1ip ? tmr3ip ccp2ip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 oscfip: oscillator fail interrupt priority bit 1 = high priority 0 = low priority bit 6 cmip: comparator interrupt priority bit 1 = high priority 0 = low priority bit 5 ethip: ethernet module interrupt priority bit 1 = high priority 0 = low priority bit 4 reserved: maintain as ? 1 ? bit 3 bcl1ip: bus collision interrupt priority bit (mssp1 module) 1 = high priority 0 = low priority bit 2 unimplemented: read as ? 0 ? bit 1 tmr3ip: tmr3 overflow interrupt priority bit 1 = high priority 0 = low priority bit 0 ccp2ip: eccp2 interrupt priority bit 1 = high priority 0 = low priority pic18f97j60 family ds39762a-page 132 advance information ? 2006 microchip technology inc. register 9-12: ipr3: peripheral interrupt priority register 3 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ssp2ip (1) bcl2ip (1) rc2ip (2) tx2ip (2) tmr4ip ccp5ip ccp4ip ccp3ip bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ssp2ip: master synchronous serial port 2 interrupt priority bit (1) 1 = high priority 0 = low priority bit 6 bcl2ip: bus collision interrupt priority bit (mssp2 module) (1) 1 = high priority 0 = low priority bit 5 rc2ip: eusart2 receive interrupt priority bit (2) 1 = high priority 0 = low priority bit 4 tx2ip: eusart2 transmit interrupt priority bit (2) 1 = high priority 0 = low priority bit 3 tmr4ie: tmr4 to pr4 interrupt priority bit 1 = high priority 0 = low priority bit 2 ccp5ip: ccp5 interrupt priority bit 1 = high priority 0 = low priority bit 1 ccp4ip: ccp4 interrupt priority bit 1 = high priority 0 = low priority bit 0 ccp3ip: eccp3 interrupt priority bit 1 = high priority 0 = low priority note 1: implemented in 100-pin devices only. 2: implemented in 80-pin and 100-pin devices only. ? 2006 microchip technology inc. advance information ds39762a-page 133 pic18f97j60 family 9.5 rcon register the rcon register contains bits used to determine the cause of the last reset or wake-up from idle or sleep modes. rcon also contains the bit that enables interrupt priorities (ipen). register 9-13: rcon: reset control register r/w-0 u-0 u-0 r/w-1 r-1 r-1 r/w-0 r/w-0 ipen ? ?ri to pd por bor bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ipen: interrupt priority enable bit 1 = enable priority levels on interrupts 0 = disable priority levels on interrupts (pic16cxxx compatibility mode) bit 6-5 unimplemented: read as ? 0 ? bit 4 ri : reset instruction flag bit for details of bit operation, see register 4-1. bit 3 to : watchdog timer time-out flag bit for details of bit operation, see register 4-1. bit 2 pd : power-down detection flag bit for details of bit operation, see register 4-1. bit 1 por : power-on reset status bit (2) for details of bit operation, see register 4-1. bit 0 bor : brown-out reset status bit for details of bit operation, see register 4-1. pic18f97j60 family ds39762a-page 134 advance information ? 2006 microchip technology inc. 9.6 intx pin interrupts external interrupts on the rb0/int0/flt0, rb1/int1, rb2/int2 and rb3/int3 pins are edge-triggered. if the corresponding intedgx bit in the intcon2 register is set (= 1 ), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. when a valid edge appears on the rbx/intx pin, the corresponding flag bit, intxif, is set. this interrupt can be disabled by clearing the corresponding enable bit, intxie. flag bit, intxif, must be cleared in software in the interrupt service routine before re-enabling the interrupt. all external interrupts (int0, int1, int2 and int3) can wake-up the processor from the power-managed modes if bit intxie was set prior to going into the power-managed modes. if the global interrupt enable bit, gie, is set, the processor will branch to the interrupt vector following wake-up. interrupt priority for int1, int2 and int3 is determined by the value contained in the interrupt priority bits, int1ip (intcon3<6>), int2ip (intcon3<7>) and int3ip (intcon2<1>). there is no priority bit associated with int0. it is always a high priority interrupt source. 9.7 tmr0 interrupt in 8-bit mode (which is the default), an overflow in the tmr0 register (ffh 00h) will set flag bit, tmr0if. in 16-bit mode, an overflow in the tmr0h:tmr0l register pair (ffffh 0000h) will set tmr0if. the interrupt can be enabled/disabled by setting/clearing enable bit, tmr0ie (intcon<5>). interr upt priority for timer0 is determined by the value contained in the interrupt priority bit, tmr0ip (intcon2<2>). see section 11.0 ?timer0 module? for further details on the timer0 module. 9.8 portb interrupt-on-change an input change on portb<7:4> sets flag bit, rbif (intcon<0>). the interrupt can be enabled/disabled by setting/clearing enable bit, rbie (intcon<3>). interrupt priority for portb interrupt-on-change is determined by the value contained in the interrupt priority bit, rbip (intcon2<0>). 9.9 context saving during interrupts during interrupts, the return pc address is saved on the stack. additionally, the wreg, status and bsr registers are saved on the fast return stack. if a fast return from interrupt is not used (see section 5.3 ?data memory organization? ), the user may need to save the wreg, status and bsr registers on entry to the interrupt service routine. depending on the user?s application, other registers may also need to be saved. example 9-1 saves and restores the wreg, status and bsr registers during an interrupt service routine. example 9-1: saving status, wreg and bsr registers in ram movwf w_temp ; w_temp is in virtual bank movff status, status_temp ; status_temp located anywhere movff bsr, bsr_temp ; bsr_tmep located anywhere ; ; user isr code ; movff bsr_temp, bsr ; restore bsr movf w_temp, w ; restore wreg movff status_temp, status ; restore status ? 2006 microchip technology inc. advance information ds39762a-page 135 pic18f97j60 family 10.0 i/o ports depending on the device selected and features enabled, there are up to nine ports available. some pins of the i/o ports are multiplexed with an alternate function from the peripheral features on the device. in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has three registers for its operation. these registers are: ? tris register (data direction register) ? port register (reads the levels on the pins of the device) ? lat register (output latch) the data latch (lat register) is useful for read-modify-write operations on the value that the i/o pins are driving. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 10-1. figure 10-1: generic i/o port operation 10.1 i/o port pin capabilities when developing an application, the capabilities of the port pins must be considered. outputs on some pins have higher output drive strength than others. similarly, some pins can tolerate higher than v dd input levels. 10.1.1 pin output drive the output pin drive strengths vary for groups of pins intended to meet the needs for a variety of applications. portb and portc are designed to drive higher loads, such as leds. the external memory interface ports (portd, porte and portj) are designed to drive medium loads. all other ports are designed for small loads, typically indication only. table 10-1 sum- marizes the output capabilities. refer to section 27.0 ?electrical characteristics? for more details. table 10-1: output drive levels data bus wr lat wr tris rd port data latch tris latch rd tris input buffer i/o pin (1) q d ck q d ck en qd en rd lat or port note 1: i/o pins have diode protection to v dd and v ss . port drive description porta (1) minimum intended for indication. portf (2) portg (2) porth (3) portd (2) medium sufficient drive levels for external memory interfacing as well as indication. porte portj (3) portb high suitable for direct led drive levels. portc note 1: the exceptions are ra0:ra1, which are capable of directly driving leds. 2: partially implemented on 64-pin and 80-pin devices; fully implemented on 100-pin devices. 3: unimplemented on 64-pin devices. pic18f97j60 family ds39762a-page 136 advance information ? 2006 microchip technology inc. 10.1.2 input pins and voltage considerations the voltage tolerance of pins used as device inputs is dependent on the pin?s input function. pins that are used as digital only inputs are able to handle dc voltages up to 5.5v, a level typical for digital logic circuits. in contrast, pins that also have analog input functions of any kind can only tolerate voltages up to v dd . voltage excursions beyond v dd on these pins should be avoided. table 10-2 summarizes the input capabilities. refer to section 27.0 ?electrical characteristics? for more details. table 10-2: input voltage levels 10.2 porta, trisa and lata registers porta is a 6-bit wide, bidirectional port; it is fully implemented on all devices. the corresponding data direction register is trisa. setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., put the contents of the output latch on the selected pin). reading the porta register reads the status of the pins, whereas writing to it, will write to the port latch. the data latch register (lata) is also memory mapped. read-modify-write operations on the lata register read and write the latched output value for porta. the ra4 pin is multiplexed with the timer0 module clock input to become the ra4/t0cki pin. the other porta pins are multiplexed with the analog v ref + and v ref - inputs. the operation of pins ra5:ra0 as a/d converter inputs is selected by clearing or setting the pcfg3:pcfg0 control bits in the adcon1 register. the ra4/t0cki pin is a schmitt trigger input. all other porta pins have ttl input levels and full cmos output drivers. the trisa register controls the direction of the porta pins, even when they are being used as analog inputs. the user must ensure the bits in the trisa register are maintained set when using them as analog inputs. the ra0 and ra1 pins can also be configured as the outputs for the two ethernet led indicators. when configured, these two pins are the only pins on porta that are capable of high output drive levels. although the port is only six bits wide, porta<7> is implemented as rjpu, the weak pull-up control bit for portj. in a similar fashion, lata<7:6> are imple- mented not as latch bits, but the pull-up control bits, rdpu and repu, for portd and porte. setting these bits enables the pull-ups for the corresponding port. because their port pins are not used, the trisa<7:6> bits are not implemented. example 10-1: initializing porta port or pin tolerated input description porta<5:0> v dd only v dd input levels tolerated. portf<6:1> (1) porth<7:4> (2) portb<7:0> 5.5v tolerates input levels above v dd , useful for most standard logic. portc<7:0> portd<7:0> (1) porte<7:0> portf<7> portg<7:0> (1) porth<3:0> (2) portj<7:0> (2) note 1: partially implemented on 64-pin and 80-pin devices; fully implemented on 100-pin devices. 2: unavailable on 64-pin devices. note: ra5 and ra3:ra0 are configured as analog inputs on any reset and are read as ? 0 ?. ra4 is configured as a digital input. clrf porta ; initialize porta by ; clearing output ; data latches clrf lata ; alternate method ; to clear output ; data latches movlw 07h ; configure a/d movwf adcon1 ; for digital inputs movwf 07h ; configure comparators movwf cmcon ; for digital input movlw 0cfh ; value used to ; initialize data ; direction movwf trisa ; set ra<3:0> as inputs ; ra<5:4> as outputs ? 2006 microchip technology inc. advance information ds39762a-page 137 pic18f97j60 family table 10-3: porta functions table 10-4: summary of registers associated with porta pin name function tris setting i/o i/o type description ra0/leda/an0 ra0 0 o dig lata<0> data output; not affected by analog input. 1 i ttl porta<0> data input; disabled when analog input enabled. leda 0 o dig ethernet leda output; takes priority over digital data. an0 1 i ana a/d input channel 0. default input configuration on por; does not affect digital output. ra1/ledb/an1 ra1 0 o dig lata<1> data output; not affected by analog input. 1 i ttl porta<1> data input; disabled when analog input enabled. ledb 0 o dig ethernet ledb output; takes priority over digital data. an1 1 i ana a/d input channel 1. default input configuration on por; does not affect digital output. ra2/an2/v ref -ra2 0 o dig lata<2> data output; not affected by analog input. disabled when cv ref output enabled. 1 i ttl porta<2> data input. disabled when analog functions enabled; disabled when cv ref output enabled. an2 1 i ana a/d input channel 2 and comparator c2+ input. default input configuration on por; not affected by analog output. v ref - 1 i ana a/d and comparator low reference voltage input. ra3/an3/v ref +ra3 0 o dig lata<3> data output; not affected by analog input. 1 i ttl porta<3> data input; disabled when analog input enabled. an3 1 i ana a/d input channel 3. default input configuration on por. v ref + 1 i ana a/d high reference voltage input. ra4/t0cki ra4 0 o dig lata<4> data output. 1 i st porta<4> data input; default configuration on por. t0cki x i st timer0 clock input. ra5/an4 ra5 0 o dig lata<5> data output; not affected by analog input. 1 i ttl porta<5> data input; disabled when analog input enabled. an4 1 i ana a/d input channel 4. default configuration on por. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porta rjpu (1) ? ra5 ra4 ra3 ra2 ra1 ra0 62 lata rdpu repu lata5 lata4 lata3 lata2 lata1 lata0 62 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 61 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by porta. note 1: implemented in 80-pin and 100-pin devices only. pic18f97j60 family ds39762a-page 138 advance information ? 2006 microchip technology inc. 10.3 portb, trisb and latb registers portb is an 8-bit wide, bidirectional port; it is fully implemented on all devices. the corresponding data direction register is trisb. setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., put the contents of the output latch on the selected pin). all pins on portb are digital only and tolerate voltages up to 5.5v. the data latch register (latb) is also memory mapped. read-modify-write operations on the latb register read and write the latched output value for portb. example 10-2: initializing portb each of the portb pins has a weak internal pull-up. a single control bit can turn on all the pull-ups. this is performed by clearing bit rbpu (intcon2<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on a power-on reset. four of the portb pins (rb7:rb4) have an interrupt-on-change feature. only pins configured as inputs can cause this interrupt to occur (i.e., any rb7:rb4 pin configured as an output is excluded from the interrupt-on-change comparison). the input pins (of rb7:rb4) are compared with the old value latched on the last read of portb. the ?mismatch? outputs of rb7:rb4 are ored together to generate the rb port change interrupt with flag bit, rbif (intcon<0>). this interrupt can wake the device from power-managed modes. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of portb (except with the movff (any), portb instruction). this will end the mismatch condition. b) clear flag bit, rbif. a mismatch condition will continue to set flag bit, rbif. reading portb will end the mismatch condition and allow flag bit rbif to be cleared. the interrupt-on-change feature is recommended for wake-up on key depression operation and operations where portb is only used for the interrupt-on-change feature. polling of portb is not recommended while using the interrupt-on-change feature. for 100-pin devices operating in extended micro- controller mode, rb3 can be configured as the alternate peripheral pin for the eccp2 module and enhanced pwm output 2a by clearing the ccp2mx configuration bit. if the devices are in microcontroller mode, the alternate assignment for eccp2 is re7. as with other eccp2 configurations, the user must ensure that the trisb<3> bit is set appropriately for the intended operation. clrf portb ; initialize portb by ; clearing output ; data latches clrf latb ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisb ; set rb<3:0> as inputs ; rb<5:4> as outputs ; rb<7:6> as inputs ? 2006 microchip technology inc. advance information ds39762a-page 139 pic18f97j60 family table 10-5: portb functions pin name function tris setting i/o i/o type description rb0/int0/flt0 rb0 0 o dig latb<0> data output. 1 i ttl portb<0> data input; weak pull-up when rbpu bit is cleared. int0 1 i st external interrupt 0 input. flt0 1 i st enhanced pwm fault input (eccp1 module); enabled in software. rb1/int1 rb1 0 o dig latb<1> data output. 1 i ttl portb<1> data input; weak pull-up when rbpu bit is cleared. int1 1 i st external interrupt 1 input. rb2/int2 rb2 0 o dig latb<2> data output. 1 i ttl portb<2> data input; weak pull-up when rbpu bit is cleared. int2 1 i st external interrupt 2 input. rb3/int3/ eccp2/p2a rb3 0 o dig latb<3> data output. 1 i ttl portb<3> data input; weak pull-up when rbpu bit is cleared. int3 1 i st external interrupt 3 input. eccp2 (1) 0 o dig ccp2 compare output and ccp2 pwm output; takes priority over port data. 1 i st ccp2 capture input. p2a (1) 0 o dig eccp2 enhanced pwm output, channel a. may be configured for tri-state during enhanced pwm shutdown events. takes priority over port data. rb4/kbi0 rb4 0 o dig latb<4> data output. 1 i ttl portb<4> data input; weak pull-up when rbpu bit is cleared. kbi0 1 i ttl interrupt-on-pin change. rb5/kbi1 rb5 0 o dig latb<5> data output. 1 i ttl portb<5> data input; weak pull-up when rbpu bit is cleared. kbi1 1 i ttl interrupt-on-pin change. rb6/kbi2/pgc rb6 0 o dig latb<6> data output. 1 i ttl portb<6> data input; weak pull-up when rbpu bit is cleared. kbi2 1 i ttl interrupt-on-pin change. pgc x i st serial execution (icsp?) clock input for icsp and icd operation. (2) rb7/kbi3/pgd rb7 0 o dig latb<7> data output. 1 i ttl portb<7> data input; weak pull-up when rbpu bit is cleared. kbi3 1 i ttl interrupt-on-pin change. pgd x o dig serial execution data output for icsp and icd operation. (2) x i st serial execution data input for icsp and icd operation. (2) legend: o = output, i = input, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: alternate assignment for eccp2/p2a when the ccp2mx conf iguration bit is cleared (100-pin devices in extended microcontroller mode). default assignment is rc1. 2: all other pin functions are dis abled when icsp or icd is enabled. pic18f97j60 family ds39762a-page 140 advance information ? 2006 microchip technology inc. table 10-6: summary of registers associated with portb name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 62 latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 62 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 61 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 59 intcon3 int2ip int1ip int3ie int2ie int1ie int3if int2if int1if 59 legend: shaded cells are not used by portb. ? 2006 microchip technology inc. advance information ds39762a-page 141 pic18f97j60 family 10.4 portc, trisc and latc registers portc is an 8-bit wide, bidirectional port; it is fully implemented on all devices. the corresponding data direction register is trisc. setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., put the contents of the output latch on the selected pin). only portc pins, rc2 through rc7, are digital only pins and can tolerate input voltages up to 5.5v. the data latch register (latc) is also memory mapped. read-modify-write operations on the latc register read and write the latched output value for portc. portc is multiplexed with several peripheral functions (table 10-7). the pins have schmitt trigger input buffers. rc1 is normally configured by configuration bit ccp2mx as the default peripheral pin for the eccp2 module and enhanced pwm output p2a (default state, ccp2mx = 1 ). when enabling peripheral functions, care should be taken in defining tris bits for each portc pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the contents of the trisc register are affected by peripheral overrides. reading trisc always returns the current contents, even though a peripheral device may be overriding one or more of the pins. example 10-3: initializing portc note: these pins are configured as digital inputs on any device reset. clrf portc ; initialize portc by ; clearing output ; data latches clrf latc ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisc ; set rc<3:0> as inputs ; rc<5:4> as outputs ; rc<7:6> as inputs pic18f97j60 family ds39762a-page 142 advance information ? 2006 microchip technology inc. table 10-7: portc functions pin name function tris setting i/o i/o type description rc0/t1oso/ t13cki rc0 0 o dig latc<0> data output. 1 i st portc<0> data input. t1oso x o ana timer1 oscillator output; enabled when timer1 oscillator enabled. disables digital i/o. t13cki 1 i st timer1/timer3 counter input. rc1/t1osi/ eccp2/p2a rc1 0 o dig latc<1> data output. 1 i st portc<1> data input. t1osi x i ana timer1 oscillator input; enabled when timer1 oscillator enabled. disables digital i/o. eccp2 (1) 0 o dig ccp2 compare output and ccp2 pwm output; takes priority over port data. 1 i st ccp2 capture input. p2a (1) 0 o dig eccp2 enhanced pwm output, channel a. may be configured for tri-state during enhanced pwm shutdown events. takes priority over port data. rc2/eccp1/ p1a rc2 0 o dig latc<2> data output. 1 i st portc<2> data input. eccp1 0 o dig ccp1 compare output and ccp1 pwm output; takes priority over port data. 1 i st ccp1 capture input. p1a 0 o dig eccp1 enhanced pwm output, channel a. may be configured for tri-state during enhanced pwm shutdown events. takes priority over port data. rc3/sck1/ scl1 rc3 0 o dig latc<3> data output. 1 i st portc<3> data input. sck1 0 o dig spi clock output (mssp1 module); takes priority over port data. 1 i st spi clock input (mssp1 module). scl1 0 odigi 2 c? clock output (mssp1 module); takes priority over port data. 1 isti 2 c clock input (mssp1 module); input type depends on module setting. rc4/sdi1/ sda1 rc4 0 o dig latc<4> data output. 1 i st portc<4> data input. sdi1 1 i st spi data input (mssp1 module). sda1 1 odigi 2 c data output (mssp1 module); takes priority over port data. 1 isti 2 c data input (mssp1 module); input type depends on module setting. rc5/sdo1 rc5 0 o dig latc<5> data output. 1 i st portc<5> data input. sdo1 0 o dig spi data output (mssp1 module); takes priority over port data. rc6/tx1/ck1 rc6 0 o dig latc<6> data output. 1 i st portc<6> data input. tx1 1 o dig synchronous serial data output (eusart1 module); takes priority over port data. ck1 1 o dig synchronous serial data input (eusar t1 module). user must configure as an input. 1 i st synchronous serial clock input (eusart1 module). rc7/rx1/dt1 rc7 0 o dig latc<7> data output. 1 i st portc<7> data input. rx1 1 i st asynchronous serial receive data input (eusart1 module). dt1 1 o dig synchronous serial data output (eusart1 module); takes priority over port data. 1 i st synchronous serial data input (eusar t1 module). user must configure as an input. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: default assignment for eccp2/p2a when ccp2mx configuration bit is set. ? 2006 microchip technology inc. advance information ds39762a-page 143 pic18f97j60 family table 10-8: summary of registers associated with portc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 62 latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 62 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 61 pic18f97j60 family ds39762a-page 144 advance information ? 2006 microchip technology inc. 10.5 portd, trisd and latd registers portd is implemented as a bidirectional port in two ways: ? 64-pin and 80-pin devices: 3 bits (rd<2:0>) ? 100-pin devices: 8 bits (rd<7:0>) the corresponding data direction register is trisd. setting a trisd bit (= 1 ) will make the corresponding portd pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisd bit (= 0 ) will make the corresponding portd pin an output (i.e., put the contents of the output latch on the selected pin). all pins on portd are digital only and tolerate voltages up to 5.5v. the data latch register (latd) is also memory mapped. read-modify-write operations on the latd register read and write the latched output value for portd. all pins on portd are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. on 100-pin devices, portd is multiplexed with the system bus as part of the external memory interface. i/o port and other functions are only available when the interface is disabled, by setting the ebdis bit (memcon<7>). when the interface is enabled, portd is the low-order byte of the multiplexed address/data bus (ad7:ad0). the trisd bits are also overridden. each of the portd pins has a weak internal pull-up. the pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up. a single control bit can turn off all the pull-ups. this is performed by clearing bit, rdpu (lata<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are enabled on all device resets. on 100-pin devices, portd can also be configured to function as an 8-bit wide, parallel microprocessor port by setting the pspmode control bit (pspcon<4>). in this mode, parallel port data takes priority over other digital i/o (but not the external memory interface). when the parallel port is active, the input buffers are ttl. for more information, refer to section 10.11 ?parallel slave port? . example 10-4: initializing portd note: these pins are configured as digital inputs on any device reset. clrf portd ; initialize portd by ; clearing output ; data latches clrf latd ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisd ; set rd<3:0> as inputs ; rd<5:4> as outputs ; rd<7:6> as inputs ? 2006 microchip technology inc. advance information ds39762a-page 145 pic18f97j60 family table 10-9: portd functions pin name function tris setting i/o i/o type description rd0/ad0/psp0 (rd0/p1b) rd0 0 o dig latd<0> data output. 1 i st portd<0> data input. ad0 (1) x o dig external memory interface, address/data bit 0 output. (2) x i ttl external memory interface, data bit 0 input. (2) psp0 (1) x o dig psp read output data (latd<0>); takes priority over port data. x i ttl psp write data input. p1b (3) 0 o dig eccp1 enhanced pwm output, channel b; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. rd1/ad1/psp1 (rd1/eccp3/ p3a) rd1 0 o dig latd<1> data output. 1 i st portd<1> data input. ad1 (1) x o dig external memory interface, address/data bit 1 output. (2) x i ttl external memory interface, data bit 1 input. (2) psp1 (1) x o dig psp read output data (latd<1>); takes priority over port data. x i ttl psp write data input. eccp3 (3) 0 o dig eccp3 compare and pwm output; takes priority over port data. 1 i st eccp3 capture input. p3a (3) 0 o dig eccp3 enhanced pwm output, channel a; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. rd2/ad2/psp2 (rd2/ccp4/ p3d) rd2 0 o dig latd<2> data output. 1 i st portd<2> data input. ad2 (1) x o dig external memory interface, address/data bit 2 output. (2) x i ttl external memory interface, data bit 2 input. (2) psp2 (1) x o dig psp read output data (latd<2>); takes priority over port data. x i ttl psp write data input. ccp4 (3) 0 o dig ccp4 compare output and ccp4 pwm output; takes priority over port data. 1 i st ccp4 capture input. p3d (3) 0 o dig eccp3 enhanced pwm output, channel d; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. rd3/ad3/ psp3 (1) rd3 (1) 0 o dig latd<3> data output. 1 i st portd<3> data input. ad3 (1) x o dig external memory interface, address/data bit 3 output. (2) x i ttl external memory interface, data bit 3 input. (2) psp3 (1) x o dig psp read output data (latd<3>); takes priority over port data. x i ttl psp write data input. legend: o = output, i = input, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: these features or por t pins are implemented only on 100-pin devices. 2: external memory interface i/o takes priority over all other digital and psp i/o. 3: these features are implemented on this pin only on 64-pin devices; for all ot her devices, they ar e multiplexed with re6/rh7 (p1b), rg0 (eccp3/ p3a) or rg3 (ccp4/p3d). pic18f97j60 family ds39762a-page 146 advance information ? 2006 microchip technology inc. rd4/ad4/ psp4/sdo2 (1) rd4 (1) 0 o dig latd<4> data output. 1 i st portd<4> data input. ad4 (1) x o dig external memory interface, address/data bit 4 output. (2) x i ttl external memory interface, data bit 4 input. (2) psp4 (1) x o dig psp read output data (latd<4>); takes priority over port data. x i ttl psp write data input. sdo2 (1) 0 o dig spi data output (mssp2 module); takes priority over port data. rd5/ad5/ psp5/sdi2/ sda2 (1) rd5 (1) 0 o dig latd<5> data output. 1 i st portd<5> data input. ad5 (1) x o dig external memory interface, address/data bit 5 output. (2) x i ttl external memory interface, data bit 5 input. (2) psp5 (1) x o dig psp read output data (latd<5>); takes priority over port data. x i ttl psp write data input. sdi2 (1) 1 i st spi data input (mssp2 module). sda2 (1) 1 odigi 2 c? data output (mssp2 module); takes priority over port data. 1 isti 2 c data input (mssp2 module); input type depends on module setting. rd6/ad6/ psp6/sck2/ scl2 (1) rd6 (1) 0 o dig latd<6> data output. 1 i st portd<6> data input. ad6 (1) x o dig-3 external memory interface, address/data bit 6 output. (1) x i ttl external memory interface, data bit 6 input. (1) psp6 (1) x o dig psp read output data (latd<6>); takes priority over port data. x i ttl psp write data input. sck2 (1) 0 o dig spi clock output (mssp2 module); takes priority over port data. 1 i st spi clock input (mssp2 module). scl2 (1) 0 odigi 2 c clock output (mssp2 module); takes priority over port data. 1 isti 2 c clock input (mssp2 module); input type depends on module setting. rd7/ad7/ psp7/ss2 (1) rd7 (1) 0 o dig latd<7> data output. 1 i st portd<7> data input. ad7 (1) x o dig external memory interface, address/data bit 7 output. (1) x i ttl external memory interface, data bit 7 input. (1) psp7 (1) x o dig psp read output data (latd<7>); takes priority over port data. x i ttl psp write data input. ss2 (1) x i ttl slave select input for mssp (mssp2 module). table 10-9: portd functions (continued) pin name function tris setting i/o i/o type description legend: o = output, i = input, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: these features or port pins ar e implemented only on 100-pin devices. 2: external memory interface i/o takes priority over all other digital and psp i/o. 3: these features are implemented on this pin only on 64-pin devices; for all ot her devices, they ar e multiplexed with re6/rh7 (p1b), rg0 (eccp3/ p3a) or rg3 (ccp4/p3d). ? 2006 microchip technology inc. advance information ds39762a-page 147 pic18f97j60 family table 10-10: summary of registers associated with portd name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portd rd7 (1) rd6 (1) rd5 (1) rd4 (1) rd3 (1) rd2 rd1 rd0 62 latd latd7 (1) latd6 (1) latd5 (1) latd4 (1) latd3 (1) latd2 latd1 latd0 62 trisd trisd7 (1) trisd6 (1) trisd5 (1) trisd4 (1) trisd3 (1) trisd2 trisd1 trisd0 61 lata rdpu repu lata5 lata4 lata3 lata2 lata1 lata0 62 legend: shaded cells are not used by portd. note 1: unimplemented on 64-pin and 80-pin devices; read as ? 0 ?. pic18f97j60 family ds39762a-page 148 advance information ? 2006 microchip technology inc. 10.6 porte, trise and late registers porte is implemented as a bidirectional port in two different ways: ? 64-pin devices: 6 bits wide (re<5:0>) ? 80-pin and 100-pin devices: 8 bits wide (re<7:0>) the corresponding data direction register is trise. setting a trise bit (= 1 ) will make the corresponding porte pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trise bit (= 0 ) will make the corresponding porte pin an output (i.e., put the contents of the output latch on the selected pin). all pins on porte are digital only and tolerate voltages up to 5.5v. the data latch register (late) is also memory mapped. read-modify-write operations on the late register read and write the latched output value for porte. all pins on porte are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. on 100-pin devices, porte is multiplexed with the system bus as part of the external memory interface. i/o port and other functions are only available when the interface is disabled by setting the ebdis bit (memcon<7>). when the interface is enabled, porte is the high-order byte of the multiplexed address/data bus (ad15:ad8). the trise bits are also overridden. each of the porte pins has a weak internal pull-up. the pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up. a single control bit can turn off all the pull-ups. this is performed by clearing bit repu (lata<6>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on any device reset. porte is also multiplexed with enhanced pwm outputs b and c for eccp1 and eccp3 and outputs b, c and d for eccp2. for 80-pin and 100-pin devices, their default assignments are on porte<6:0>. for 64-pin devices, their default assignments are on porte<5:0> and portd<0>. on 80-pin and 100-pin devices, the multiplexing for the outputs of eccp1 and eccp3 is controlled by the eccpmx configuration bit. clearing this bit reassigns the p1b/p1c and p3b/p3c outputs to porth. for 80-pin and 100-pin devices operating in micro- controller mode, pin re7 can be configured as the alternate peripheral pin for the eccp2 module and enhanced pwm output 2a. this is done by clearing the ccp2mx configuration bit. when the parallel slave port is active on portd, three of the porte pins (re0, re1 and re2) are configured as digital control inputs for the port. the control functions are summarized in table 10-11. the reconfig- uration occurs automatically when the pspmode control bit (pspcon<4>) is set. users must still make certain the corresponding trise bits are set to configure these pins as digital inputs. example 10-5: initializing porte note: these pins are configured as digital inputs on any device reset. clrf porte ; initialize porte by ; clearing output ; data latches clrf late ; alternate method ; to clear output ; data latches movlw 03h ; value used to ; initialize data ; direction movwf trise ; set re<1:0> as inputs ; re<7:2> as outputs ? 2006 microchip technology inc. advance information ds39762a-page 149 pic18f97j60 family table 10-11: porte functions pin name function tris setting i/o i/o type description re0/ad8/rd / p2d re0 0 o dig late<0> data output. 1 i st porte<0> data input. ad8 (1) x o dig external memory interface, address/data bit 8 output. (2) x i ttl external memory interface, data bit 8 input. (2) rd (6) 1 i ttl parallel slave port read enable control input. p2d 0 o dig eccp2 enhanced pwm output, channel d; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. re1/ad9/wr / p2c re1 0 o dig late<1> data output. 1 i st porte<1> data input. ad9 (1) x o dig external memory interface, address/data bit 9 output. (2) x i ttl external memory interface, data bit 9 input. (2) wr (6) 1 i ttl parallel slave port write enable control input. p2c 0 o dig eccp2 enhanced pwm output, channel c; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. re2/ad10/cs / p2b re2 0 o dig late<2> data output. 1 i st porte<2> data input. ad10 (1) x o dig external memory interface, address/data bit 10 output. (2) x i ttl external memory interface, data bit 10 input. (2) cs (6) 1 i ttl parallel slave port chip select control input. p2b 0 o dig eccp2 enhanced pwm output, channel b; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. re3/ad11/ p3c re3 0 o dig late<3> data output. 1 i st porte<3> data input. ad11 (1) x o dig external memory interface, address/data bit 11 output. (2) x i ttl external memory interface, data bit 11 input. (2) p3c (3) 0 o dig eccp3 enhanced pwm output, channel c; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. re4/ad12/ p3b re4 0 o dig late<4> data output. 1 i st porte<4> data input. ad12 (1) x o dig external memory interface, address/data bit 12 output. (2) x i ttl external memory interface, data bit 12 input. (2) p3b (3) 0 o dig eccp3 enhanced pwm output, channel b; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. legend: o = output, i = input, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: emb functions implemented on 100-pin devices only. 2: external memory interface i/o takes priority over all other digital and psp i/o. 3: default assignments for p1b/p1c and p3b/p3c when eccpmx configuration bit is se t (80-pin and 100-pin devices). 4: unimplemented on 64-pin devices. 5: alternate assignment for eccp2/p2a when ccp2mx confi guration bit is cleared (80- pin and 100-pin devices in microcontroller mode). 6: unimplemented on 64-pin and 80-pin devices. pic18f97j60 family ds39762a-page 150 advance information ? 2006 microchip technology inc. table 10-12: summary of registers associated with porte re5/ad13/ p1c re5 0 o dig late<5> data output. 1 i st porte<5> data input. ad13 (1) x o dig external memory interface, address/data bit 13 output. (2) x i ttl external memory interface, data bit 13 input. (2) p1c (3) 0 o dig eccp1 enhanced pwm output, channel c; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. re6/ad14/ p1b (4) re6 0 o dig late<6> data output. 1 i st porte<6> data input. ad14 (1) x o dig external memory interface, address/data bit 14 output. (2) x i ttl external memory interface, data bit 14 input. (2) p1b (3) 0 o dig eccp1 enhanced pwm output, channel b; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. re7/ad15/ eccp2/p2a (4) re7 0 o dig late<7> data output. 1 i st porte<7> data input. ad15 (1) x o dig external memory interface, address/data bit 15 output. (2) x i ttl external memory interface, data bit 15 input. (2) eccp2 (5) 0 o dig ccp2 compare output and ccp2 pwm output; takes priority over port data. 1 i st ccp2 capture input. p2a (5) 0 o dig eccp2 enhanced pwm output, channel a; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. table 10-11: porte functions (continued) pin name function tris setting i/o i/o type description legend: o = output, i = input, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: emb functions implemented on 100-pin devices only. 2: external memory interface i/o takes priority over all other digital and psp i/o. 3: default assignments for p1b/p1c and p3b/p3c when eccpmx configuration bit is set (80-pin and 100-pin devices). 4: unimplemented on 64-pin devices. 5: alternate assignment for eccp2/p2a when ccp2mx confi guration bit is cleared (80- pin and 100-pin devices in microcontroller mode). 6: unimplemented on 64-pin and 80-pin devices. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porte re7 (1) re6 (1) re5 re4 re3 re2 re1 re0 62 late late7 (1) late6 (1) late5 late4 late3 late2 late1 late0 62 trise trise7 (1) trise6 (1) trise5 trise4 trise3 trise2 trise1 trise0 61 lata rdpu repu lata5 lata4 lata3 lata2 lata1 lata0 62 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by porte. note 1: unimplemented on 64-pin devices; read as ? 0 ?. ? 2006 microchip technology inc. advance information ds39762a-page 151 pic18f97j60 family 10.7 portf, latf and trisf registers portf is implemented as a bidirectional port in two different ways: ? 64-pin and 80-pin devices: 7 bits wide (rf<7:1>) ? 100-pin devices: 8 bits wide (rf<7:0>) the corresponding data direction register is trisf. setting a trisf bit (= 1 ) will make the corresponding portf pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisf bit (= 0 ) will make the corresponding portf pin an output (i.e., put the contents of the output latch on the selected pin). only pin 7 of portf has no analog input; it is the only pin that can tolerate voltages up to 5.5v. the data latch register (latf) is also memory mapped. read-modify-write operations on the latf register read and write the latched output value for portf. all pins on portf are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. portf is multiplexed with several analog peripheral functions, including the a/d converter and comparator inputs, as well as the comparator outputs. pins rf1 through rf6 may be used as comparator inputs or outputs by setting the appropriate bits in the cmcon register. to use rf6:rf1 as digital inputs, it is also necessary to turn off the comparators. example 10-6: initializing portf note 1: on device resets, pins rf6:rf1 are configured as analog inputs and are read as ? 0 ?. 2: to configure portf as digital i/o, turn off comparators and set adcon1 value. clrf portf ; initialize portf by ; clearing output ; data latches clrf latf ; alternate method ; to clear output ; data latches movlw 07h ; movwf cmcon ; turn off comparators movlw 0fh ; movwf adcon1 ; set portf as digital i/o movlw 0ceh ; value used to ; initialize data ; direction movwf trisf ; set rf3:rf1 as inputs ; rf5:rf4 as outputs ; rf7:rf6 as inputs pic18f97j60 family ds39762a-page 152 advance information ? 2006 microchip technology inc. table 10-13: portf functions table 10-14: summary of registers associated with portf pin name function tris setting i/o i/o type description rf0/an5 (1) rf0 (1) 0 o dig latf<0> data output; not affected by analog input. 1 i st portf<0> data input; disabled when analog input enabled. an5 (1) 1 i ana a/d input channel 5. default configuration on por. rf1/an6/ c2out rf1 0 o dig latf<1> data output; not affected by analog input. 1 i st portf<1> data input; disabled when analog input enabled. an6 1 i ana a/d input channel 6. default configuration on por. c2out 0 o dig comparator 2 output; takes priority over port data. rf2/an7/ c1out rf2 0 o dig latf<2> data output; not affected by analog input. 1 i st portf<2> data input; disabled when analog input enabled. an7 1 i ana a/d input channel 7. default configuration on por. c1out 0 o ttl comparator 1 output; takes priority over port data. rf3/an8 rf3 0 o dig latf<3> data output; not affected by analog input. 1 i st portf<3> data input; disabled when analog input enabled. an8 1 i ana a/d input channel 8 and comparator c2 + input. default input configuration on por; not affected by analog output. rf4/an9 rf4 0 o dig latf<4> data output; not affected by analog input. 1 i st portf<4> data input; disabled when analog input enabled. an9 1 i ana a/d input channel 9 and comparator c2- input. default input configuration on por; does not affect digital output. rf5/an10/ cv ref rf5 0 o dig latf<5> data output; not affected by analog input. disabled when cv ref output enabled. 1 i st portf<5> data input; disabled when analog input enabled. disabled when cv ref output enabled. an10 1 i ana a/d input channel 10 and comparator c1+ input. default input configuration on por. cv ref x o ana comparator voltage reference output. e nabling this feature disables digital i/o. rf6/an11 rf6 0 o dig latf<6> data output; not affected by analog input. 1 i st portf<6> data input; disabled when analog input enabled. an11 1 i ana a/d input channel 11 and comparator c1- input. default input configuration on por; does not affect digital output. rf7/ss1 rf7 0 o dig latf<7> data output. 1 i st portf<7> data input. ss1 1 i ttl slave select input for mssp (mssp1 module). legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, ttl = ttl buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: implemented on 100-pin devices only. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 (1) 62 latf latf7 latf6 latf5 latf4 latf3 latf2 latf1 latf0 (1) 62 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 (1) 61 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 60 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 60 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by portf. note 1: implemented on 100-pin devices only. ? 2006 microchip technology inc. advance information ds39762a-page 153 pic18f97j60 family 10.8 portg, trisg and latg registers depending on the particular device, portg is implemented as a bidirectional port in one of three ways: ? 64-pin devices: 1 bit wide (rg<4>) ? 80-pin devices: 5 bits wide (rg<4:0>) ? 100-pin devices: 8 bits wide (rg<7:0>) the corresponding data direction register is trisg. setting a trisg bit (= 1 ) will make the corresponding portg pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisg bit (= 0 ) will make the corresponding portg pin an output (i.e., put the contents of the output latch on the selected pin). all pins on portg are digital only and tolerate voltages up to 5.5v. the data latch register (latg) is also memory mapped. read-modify-write operations on the latg register read and write the latched output value for portg. portg is multiplexed with eusart2 functions on 80-pin and 100-pin devices (table 10-15). portg pins have schmitt trigger input buffers. when enabling peripheral functions, care should be taken in defining tris bits for each portg pin. some peripherals override the tris bit to make a pin an output, while other peripherals override the tris bit to make a pin an input. the user should refer to the corresponding peripheral section for the correct tris bit settings. the pin override value is not loaded into the tris register. this allows read-modify-write of the tris register without concern due to peripheral overrides. example 10-7: initializing portg clrf portg ; initialize portg by ; clearing output ; data latches clrf latg ; alternate method ; to clear output ; data latches movlw 04h ; value used to ; initialize data ; direction movwf trisg ; set rg1:rg0 as outputs ; rg2 as input ; rg4:rg3 as inputs pic18f97j60 family ds39762a-page 154 advance information ? 2006 microchip technology inc. table 10-15: portg functions pin name function tris setting i/o i/o type description rg0/eccp3/ p3a (1) rg0 (1) 0 o dig latg<0> data output. 1 i st portg<0> data input. eccp3 (1) 0 o dig ccp3 compare and pwm output; takes priority over port data. 1 i st ccp3 capture input. p3a (1) 0 o dig eccp3 enhanced pwm output, channel a; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. rg1/tx2/ ck2 (1) rg1 (1) 0 o dig latg<1> data output. 1 i st portg<1> data input. tx2 (1) 1 o dig synchronous serial data output (eusart2 module); takes priority over port data. ck2 (1) 1 o dig synchronous serial data input (eus art2 module). user must configure as an input. 1 i st synchronous serial clock input (eusart2 module). rg2/rx2/ dt2 (1) rg2 (1) 0 o dig latg<2> data output. 1 i st portg<2> data input. rx2 (1) 1 i st asynchronous serial receive data input (eusart2 module). dt2 (1) 1 o dig synchronous serial data output (eusart2 module); takes priority over port data. 1 i st synchronous serial data input (eusart2 module). user must configure as an input. rg3/ccp4/ p3d (1) rg3 (1) 0 o dig latg<3> data output. 1 i st portg<3> data input. ccp4 (1) 0 o dig ccp4 compare output and ccp4 pwm output; takes priority over port data. 1 i st ccp4 capture input. p3d (1) 0 o dig eccp3 enhanced pwm output, channel d; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. rg4/ccp5/ p1d rg4 0 o dig latg<4> data output. 1 i st portg<4> data input. ccp5 0 o dig ccp5 compare output and ccp5 pwm output; takes priority over port data. 1 i st ccp5 capture input. p1d 0 o dig eccp1 enhanced pwm output, channel d; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. rg5 (2) rg5 (2) 0 o dig latg<0> data output. 1 i st portg<0> data input. rg6 (2) rg6 (2) 0 o dig latg<0> data output. 1 i st portg<0> data input. rg7 (2) rg7 (2) 0 o dig latg<0> data output. 1 i st portg<0> data input. legend: o = output, i = input, dig = digital output, st = schmitt buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: implemented on 80-pin and 100-pin devices only. 2: implemented on 100-pin devices only. ? 2006 microchip technology inc. advance information ds39762a-page 155 pic18f97j60 family table 10-16: summary of registers associated with portg name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portg rg7 (1) rg6 (1) rg5 (1) rg4 rg3 (2) rg2 (2) rg1 (2) rg0 (2) 62 latg latg7 (1) latg6 (1) latg5 (1) latg4 latg3 (2) latg2 (2) latg1 (2) latg0 (2) 62 trisg trisg7 (1) trisg6 (1) trisg5 (1) trisg4 trisg3 (2) trisg2 (2) trisg1 (2) trisg0 (2) 61 note 1: implemented on 100-pin devices only. 2: implemented on 80-pin and 100-pin devices only. pic18f97j60 family ds39762a-page 156 advance information ? 2006 microchip technology inc. 10.9 porth, lath and trish registers porth is an 8-bit wide, bidirectional i/o port; it is fully implemented on 80-pin and 100-pin devices. the corresponding data direction register is trish. setting a trish bit (= 1 ) will make the corresponding porth pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trish bit (= 0 ) will make the corresponding porth pin an output (i.e., put the contents of the output latch on the selected pin). porth<3:0> pins are digital only and tolerate voltages up to 5.5v. the data latch register (lath) is also memory mapped. read-modify-write operations on the lath register read and write the latched output value for porth. all pins on porth are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. when the external memory interface is enabled, four of the porth pins function as the high-order address lines for the interface. the address output from the interface takes priority over other digital i/o. the corresponding trish bits are also overridden. porth pins, rh4 through rh7, are multiplexed with analog converter inputs. the operation of these pins as analog inputs is selected by clearing or setting the pcfg3:pcfg0 control bits in the adcon1 register. porth can also be configured as the alternate enhanced pwm output channels b and c for the eccp1 and eccp3 modules. this is done by clearing the eccpmx configuration bit. example 10-8: initializing porth note: porth is available only on 80-pin and 100-pin devices. clrf porth ; initialize porth by ; clearing output ; data latches clrf lath ; alternate method ; to clear output ; data latches movlw 0fh ; configure porth as movwf adcon1 ; digital i/o movlw 0cfh ; value used to ; initialize data ; direction movwf trish ; set rh3:rh0 as inputs ; rh5:rh4 as outputs ; rh7:rh6 as inputs ? 2006 microchip technology inc. advance information ds39762a-page 157 pic18f97j60 family table 10-17: porth functions table 10-18: summary of registers associated with porth pin name function tris setting i/o i/o type description rh0/a16 rh0 0 o dig lath<0> data output. 1 i st porth<0> data input. a16 (1) x o dig external memory interface, address line 16. takes priority over port data. rh1/a17 rh1 0 o dig lath<1> data output. 1 i st porth<1> data input. a17 (1) x o dig external memory interface, address line 17. takes priority over port data. rh2/a18 rh2 0 o dig lath<2> data output. 1 i st porth<2> data input. a18 (1) x o dig external memory interface, address line 18. takes priority over port data. rh3/a19 rh3 0 o dig lath<3> data output. 1 i st porth<3> data input. a19 (1) x o dig external memory interface, address line 19. takes priority over port data. rh4/an12/p3c rh4 0 o dig lath<4> data output. 1 i st porth<4> data input. an12 i ana a/d input channel 12. default input configuration on por; does not affect digital output. p3c (2) 0 o dig eccp3 enhanced pwm output, channel c; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. rh5/an13/p3b rh5 0 o dig lath<5> data output. 1 i st porth<5> data input. an13 i ana a/d input channel 13. default input configuration on por; does not affect digital output. p3b (2) 0 o dig eccp3 enhanced pwm output, channel b; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. rh6/an14/p1c rh6 0 o dig lath<6> data output. 1 i st porth<6> data input. an14 i ana a/d input channel 14. default input configuration on por; does not affect digital output. p1c (2) 0 o dig eccp1 enhanced pwm output, channel c; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. rh7/an15/p1b rh7 0 o dig lath<7> data output. 1 i st porth<7> data input. an15 i ana a/d input channel 15. default input configuration on por; does not affect digital output. p1b (2) 0 o dig eccp1 enhanced pwm output, channel b; takes priority over port and psp data. may be configured for tri-state during enhanced pwm shutdown events. legend: o = output, i = input, ana = analog signal, dig = digital output, st = schmitt buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: unimplemented on 80-pin devices. 2: alternate assignments for p1b/p1c and p3b/p3c when e ccpmx configuration bit is cleared (80-pin and 100-pin devices only). default assignments are porte<6:3>. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page porth rh7 rh6 rh5 rh4 rh3 rh2 rh1 rh0 62 lath lath7 lath6 lath5 lath4 lath3 lath2 lath1 lath0 61 trish trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 61 pic18f97j60 family ds39762a-page 158 advance information ? 2006 microchip technology inc. 10.10 portj, trisj and latj registers portj is implemented as a bidirectional port in two different ways: ? 80-pin devices: 2 bits wide (rj<5:4>) ? 100-pin devices: 8 bits wide (rj<7:0>) the corresponding data direction register is trisj. setting a trisj bit (= 1 ) will make the corresponding portj pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisj bit (= 0 ) will make the corresponding portj pin an output (i.e., put the contents of the output latch on the selected pin). all pins on portj are digital only and tolerate voltages up to 5.5v. the data latch register (latj) is also memory mapped. read-modify-write operations on the latj register read and write the latched output value for portj. all pins on portj are implemented with schmitt trigger input buffers. each pin is individually configurable as an input or output. when the external memory interface is enabled, all of the portj pins function as control outputs for the interface. this occurs automatically when the interface is enabled by clearing the ebdis control bit (memcon<7>). the trisj bits are also overridden. each of the portj pins has a weak internal pull-up. the pull-ups are provided to keep the inputs at a known state for the external memory interface while powering up. a single control bit can turn off all the pull-ups. this is performed by clearing bit rjpu (porta<7>). the weak pull-up is automatically turned off when the port pin is configured as an output. the pull-ups are disabled on any device reset. example 10-9: initializing portj note: portj is available only on 80-pin and 100-pin devices. note: these pins are configured as digital inputs on any device reset. clrf portj ; initialize portg by ; clearing output ; data latches clrf latj ; alternate method ; to clear output ; data latches movlw 0cfh ; value used to ; initialize data ; direction movwf trisj ; set rj3:rj0 as inputs ; rj5:rj4 as output ; rj7:rj6 as inputs ? 2006 microchip technology inc. advance information ds39762a-page 159 pic18f97j60 family table 10-19: portj functions table 10-20: summary of registers associated with portj pin name function tris setting i/o i/o type description rj0/ale (1) rj0 (1) 0 o dig latj<0> data output. 1 i st portj<0> data input. ale (1) x o dig external memory interface address latch enable control output; takes priority over digital i/o. rj1/oe (1) rj1 (1) 0 o dig latj<1> data output. 1 i st portj<1> data input. oe (1) x o dig external memory interface output enable control output; takes priority over digital i/o. rj2/wrl (1) rj2 (1) 0 o dig latj<2> data output. 1 i st portj<2> data input. wrl (1) x o dig external memory bus write low by te control; takes priority over digital i/o. rj3/wrh (1) rj3 (1) 0 o dig latj<3> data output. 1 i st portj<3> data input. wrh (1) x o dig external memory interface write high byte control output; takes priority over digital i/o. rj4/ba0 rj4 0 o dig latj<4> data output. 1 i st portj<4> data input. ba0 (2) x o dig external memory interface byte address 0 control output; takes priority over digital i/o. rj5/ce rj5 0 o dig latj<5> data output. 1 i st portj<5> data input. ce (2) x o dig external memory interface chip enable control output; takes priority over digital i/o. rj6/lb (1) rj6 (1) 0 o dig latj<6> data output. 1 i st portj<6> data input. lb (1) x o dig external memory interface lower byte enable control output; takes priority over digital i/o. rj7/ub (1) rj7 (1) 0 o dig latj<7> data output. 1 i st portj<7> data input. ub (1) x o dig external memory interface upper byte enable control output; takes priority over digital i/o. legend: o = output, i = input, dig = digital output, st = schmitt buffer input, x = don?t care (tris bit does not affect port direction or is overridden for this option). note 1: implemented on 100-pin devices only. 2: emb functions are implemented on 100-pin devices only. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portj rj7 (1) rj6 (1) rj5 rj4 rj3 (1) rj2 (1) rj1 (1) rj0 (1) 62 latj latj7 (1) latj6 (1) latj5 latj4 latj3 (1) latj2 (1) latj1 (1) latj0 (1) 61 trisj trisj7 (1) trisj6 (1) trisj5 trisj4 trisj3 (1) trisj2 (1) trisj1 (1) trisj0 (1) 61 porta rjpu ? ra5 ra4 ra3 ra2 ra1 ra0 62 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by portj. note 1: implemented on 100-pin devices only. pic18f97j60 family ds39762a-page 160 advance information ? 2006 microchip technology inc. 10.11 parallel slave port portd can also function as an 8-bit wide parallel slave port, or microprocessor port, when control bit, pspmode (pspcon<4>), is set. it is asynchronously readable and writable by the external world through the rd control input pin, re0/ad8/rd /p2d and wr control input pin, re1/ad9//wr /p2c. the psp can directly interface to an 8-bit micro- processor data bus. the external microprocessor can read or write the portd latch as an 8-bit latch. setting bit, pspmode, enables port pin re0/ad8/rd /p2d to be the rd input, re1/ad9//wr /p2c to be the wr input and re2/ad10//cs /p2b to be the cs (chip select) input. for this functionality, the corresponding data direction bits of the trise register (trise<2:0>) must be configured as inputs (set). a write to the psp occurs when both the cs and wr lines are first detected low and ends when either are detected high. the pspif and ibf flag bits are both set when the write ends. a read from the psp occurs when both the cs and rd lines are first detected low. the data in portd is read out and the obf bit is set. if the user writes new data to portd to set obf, the data is immediately read out; however, the obf bit is not set. when either the cs or rd lines is detected high, the portd pins return to the input state and the pspif bit is set. user applications should wait for pspif to be set before servicing the psp. when this happens, the ibf and obf bits can be polled and the appropriate action taken. the timing for the control signals in write and read modes is shown in figure 10-3 and figure 10-4, respectively. figure 10-2: portd and porte block diagram (parallel slave port) note: the parallel slave port is only implemented in 100-pin devices. note: the parallel slave port is available only in microcontroller mode. data bus wr latd rdx q d ck en qd en rd portd pin one bit of portd set interrupt flag pspif (pir1<7>) read chip select write rd cs wr note: i/o pin has protection diodes to v dd and v ss . ttl ttl ttl ttl or portd rd latd data latch tris latch ? 2006 microchip technology inc. advance information ds39762a-page 161 pic18f97j60 family figure 10-3: parallel slave port write waveforms register 10-1: pspcon: parallel slave port control register r-0 r-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ibf obf ibov pspmode ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ibf: input buffer full status bit 1 = a word has been received and is waiting to be read by the cpu 0 = no word has been received bit 6 obf: output buffer full status bit 1 = the output buffer still holds a previously written word 0 = the output buffer has been read bit 5 ibov: input buffer overflow detect bit 1 = a write occurred when a previously input word has not been read (must be cleared in software) 0 = no overflow occurred bit 4 pspmode: parallel slave port mode select bit 1 = parallel slave port mode 0 = general purpose i/o mode bit 3-0 unimplemented: read as ? 0 ? q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr rd ibf obf pspif portd<7:0> pic18f97j60 family ds39762a-page 162 advance information ? 2006 microchip technology inc. figure 10-4: parallel slave port read waveforms table 10-21: registers associated with parallel slave port q1 q2 q3 q4 cs q1 q2 q3 q4 q1 q2 q3 q4 wr ibf pspif rd obf portd<7:0> name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page portd rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 62 latd latd7 latd6 latd5 latd4 latd3 latd2 latd1 latd0 62 trisd trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 61 porte re7 re6 re5 re4 re3 re2 re1 re0 62 late late7 late6 late5 late4 late3 late2 late1 late0 62 trise trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 61 pspcon ibf obf ibov pspmode ? ? ? ?61 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the parallel slave port. ? 2006 microchip technology inc. advance information ds39762a-page 163 pic18f97j60 family 11.0 timer0 module the timer0 module incorporates the following features: ? software selectable operation as a timer or counter in both 8-bit or 16-bit modes ? readable and writable registers ? dedicated 8-bit, software programmable prescaler ? selectable clock source (internal or external) ? edge select for external clock ? interrupt-on-overflow the t0con register (register 11-1) controls all aspects of the module?s operation, including the prescale selection. it is both readable and writable. a simplified block diagram of the timer0 module in 8-bit mode is shown in figure 11-1. figure 11-2 shows a simplified block diagram of the timer0 module in 16-bit mode. register 11-1: t0con: timer0 control register r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 tmr0on: timer0 on/off control bit 1 = enables timer0 0 = stops timer0 bit 6 t08bit : timer0 8-bit/16-bit control bit 1 = timer0 is configured as an 8-bit timer/counter 0 = timer0 is configured as a 16-bit timer/counter bit 5 t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clko) bit 4 t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa : timer0 prescaler assignment bit 1 = timer0 prescaler is not assigned. timer0 clock input bypasses prescaler. 0 = timer0 prescaler is assigned. timer0 clock input comes from prescaler output. bit 2-0 t0ps2:t0ps0 : timer0 prescaler select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value pic18f97j60 family ds39762a-page 164 advance information ? 2006 microchip technology inc. 11.1 timer0 operation timer0 can operate as either a timer or a counter; the mode is selected with the t0cs bit (t0con<5>). in timer mode (t0cs = 0 ), the module increments on every clock by default unless a different prescaler value is selected (see section 11.3 ?prescaler? ). if the tmr0 register is written to, the increment is inhibited for the following two instruction cycles. the user can work around this by writing an adjusted value to the tmr0 register. the counter mode is selected by setting the t0cs bit (= 1 ). in this mode, timer0 increments either on every rising or falling edge of pin ra4/t0cki. the increment- ing edge is determined by the timer0 source edge select bit, t0se (t0con<4>); clearing this bit selects the rising edge. restrictions on the external clock input are discussed below. an external clock source can be used to drive timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (t osc ). there is a delay between synchronization and the onset of incrementing the timer/counter. 11.2 timer0 reads and writes in 16-bit mode tmr0h is not the actual high byte of timer0 in 16-bit mode. it is actually a buffered version of the real high byte of timer0 which is not directly readable nor writ- able (refer to figure 11-2). tmr0h is updated with the contents of the high byte of timer0 during a read of tmr0l. this provides the ability to read all 16 bits of timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. similarly, a write to the high byte of timer0 must also take place through the tmr0h buffer register. the high byte is updated with the contents of tmr0h when a write occurs to tmr0l. this allows all 16 bits of timer0 to be updated at once. figure 11-1: timer0 block diagram (8-bit mode) figure 11-2: timer0 block diagram (16-bit mode) note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) internal data bus psa t0ps2:t0ps0 set tmr0if on overflow 3 8 8 note: upon reset, timer0 is enabled in 8-bit mode with clock input from t0cki max. prescale. t0cki pin t0se 0 1 1 0 t0cs f osc /4 programmable prescaler sync with internal clocks tmr0l (2 t cy delay) internal data bus 8 psa t0ps2:t0ps0 set tmr0if on overflow 3 tmr0 tmr0h high byte 8 8 8 read tmr0l write tmr0l 8 ? 2006 microchip technology inc. advance information ds39762a-page 165 pic18f97j60 family 11.3 prescaler an 8-bit counter is available as a prescaler for the timer0 module. the prescaler is not directly readable or writable. its value is set by the psa and t0ps2:t0ps0 bits (t0con<3:0>) which determine the prescaler assignment and prescale ratio. clearing the psa bit assigns the prescaler to the timer0 module. when it is assigned, prescale values from 1:2 through 1:256 in power-of-2 increments are selectable. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf tmr0 , movwf tmr0 , bsf tmr0 , etc.) clear the prescaler count. 11.3.1 switching prescaler assignment the prescaler assignment is fully under software control and can be changed ?on-the-fly? during program execution. 11.4 timer0 interrupt the tmr0 interrupt is generated when the tmr0 register overflows from ffh to 00h in 8-bit mode, or from ffffh to 0000h in 16-bit mode. this overflow sets the tmr0if flag bit. the interrupt can be masked by clearing the tmr0ie bit (intcon<5>). before re-enabling the interrupt, the tmr0if bit must be cleared in software by the interrupt service routine. since timer0 is shut down in sleep mode, the tmr0 interrupt cannot awaken the processor from sleep. table 11-1: registers associated with timer0 note: writing to tmr0 when the prescaler is assigned to timer0 will clear the prescaler count but will not change the prescaler assignment. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page tmr0l timer0 register low byte 60 tmr0h timer0 register high byte 60 intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 intcon2 rbpu intedg0 intedg1 intedg2 intedg3 tmr0ip int3ip rbip 59 t0con tmr0on t08bit t0cs t0se psa t0ps2 t0ps1 t0ps0 60 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 61 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by timer0. pic18f97j60 family ds39762a-page 166 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 167 pic18f97j60 family 12.0 timer1 module the timer1 timer/counter module incorporates these features: ? software selectable operation as a 16-bit timer or counter ? readable and writable 8-bit registers (tmr1h and tmr1l) ? selectable clock source (internal or external) with device clock or timer1 oscillator internal options ? interrupt-on-overflow ? reset on eccp special event trigger ? device clock status flag (t1run) a simplified block diagram of the timer1 module is shown in figure 12-1. a block diagram of the module?s operation in read/write mode is shown in figure 12-2. the module incorporates its own low-power oscillator to provide an additional clocking option. the timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. timer1 can also be used to provide real-time clock (rtc) functionality to applications with only a minimal addition of external components and code overhead. timer1 is controlled through the t1con control register (register 12-1). it also contains the timer1 oscillator enable bit (t1oscen). timer1 can be enabled or disabled by setting or clearing control bit, tmr1on (t1con<0>). register 12-1: t1con: ti mer1 control register r/w-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer1 in one 16-bit operation 0 = enables register read/write of timer1 in two 8-bit operations bit 6 t1run: timer1 system clock status bit 1 = device clock is derived from timer1 oscillator 0 = device clock is derived from another source bit 5-4 t1ckps1:t1ckps0: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: timer1 oscillator enable bit 1 = timer1 oscillator is enabled 0 = timer1 oscillator is shut off the oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 t1sync : timer1 external clock input synchronization select bit when tmr1cs = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr1cs = 0 : this bit is ignored. timer1 uses the internal clock when tmr1cs = 0 . bit 1 tmr1cs: timer1 clock source select bit 1 = external clock from rc0/t1oso/t13cki pin (on the rising edge) 0 = internal clock (f osc /4) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 pic18f97j60 family ds39762a-page 168 advance information ? 2006 microchip technology inc. 12.1 timer1 operation timer1 can operate in one of these modes: ?timer ? synchronous counter ? asynchronous counter the operating mode is determined by the clock select bit, tmr1cs (t1con<1>). when tmr1cs is cleared (= 0 ), timer1 increments on every internal instruction cycle (f osc /4). when the bit is set, timer1 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. when timer1 is enabled, the rc1/t1osi and rc0/t1oso/t13cki pins become inputs. this means the values of trisc<1:0> are ignored and the pins are read as ? 0 ?. figure 12-1: timer1 block diagram figure 12-2: timer1 block diagram (16-bit read/write mode) t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen (1) f osc /4 internal clock on/off prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi 1 0 tmr1on tmr1l set tmr1if on overflow tmr1 high byte clear tmr1 (eccpx special event trigger) timer1 oscillator note 1: when enable bit, t1oscen, is cleared, the inverter and f eedback resistor are turned off to eliminate power drain. on/off timer1 timer1 clock input t1sync tmr1cs t1ckps1:t1ckps0 sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi note 1: when enable bit, t1oscen, is cleared, the inverter and f eedback resistor are turned off to eliminate power drain. 1 0 tmr1l internal data bus 8 set tmr1if on overflow tmr1 tmr1h high byte 8 8 8 read tmr1l write tmr1l 8 tmr1on clear tmr1 (eccpx special event trigger) timer1 oscillator on/off timer1 timer1 clock input ? 2006 microchip technology inc. advance information ds39762a-page 169 pic18f97j60 family 12.2 timer1 16-bit read/write mode timer1 can be configured for 16-bit reads and writes (see figure 12-2). when the rd16 control bit (t1con<7>) is set, the address for tmr1h is mapped to a buffer register for the high byte of timer1. a read from tmr1l will load the contents of the high byte of timer1 into the timer1 high byte buffer register. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. a write to the high byte of timer1 must also take place through the tmr1h buffer register. the timer1 high byte is updated with the contents of tmr1h when a write occurs to tmr1l. this allows a user to write all 16 bits to both the high and low bytes of timer1 at once. the high byte of timer1 is not directly readable or writable in this mode. all reads and writes must take place through the timer1 high byte buffer register. writes to tmr1h do not clear the timer1 prescaler. the prescaler is only cleared on writes to tmr1l. 12.3 timer1 oscillator an on-chip crystal oscillator circuit is incorporated between pins t1osi (input) and t1oso (amplifier output). it is enabled by setting the timer1 oscillator enable bit, t1oscen (t1con<3>). the oscillator is a low-power circuit rated for 32 khz crystals. it will continue to run during all power-managed modes. the circuit for a typical lp oscillator is shown in figure 12-3. table 12-1 shows the capacitor selection for the timer1 oscillator. the user must provide a software time delay to ensure proper start-up of the timer1 oscillator. figure 12-3: external components for the timer1 oscillator table 12-1: capacitor selection for the timer oscillator (2,3,4) 12.3.1 using timer1 as a clock source the timer1 oscillator is also available as a clock source in power-managed modes. by setting the clock select bits, scs1:scs0 (osccon<1:0>), to ? 01 ?, the device switches to sec_run mode; both the cpu and peripherals are clocked from the timer1 oscillator. if the idlen bit (osccon<7>) is cleared and a sleep instruction is executed, the device enters sec_idle mode. additional details are available in section 3.0 ?power-managed modes? . whenever the timer1 oscillator is providing the clock source, the timer1 system clock status flag, t1run (t1con<6>), is set. this can be used to determine the controller?s current clocking mode. it can also indicate the clock source being currently used by the fail-safe clock monitor. if the clock monitor is enabled and the timer1 oscillator fails while providing the clock, polling the t1run bit will indicate whether the clock is being provided by the timer1 oscillator or another source. note: see the notes with table 12-1 for additional information about capacitor selection. c1 c2 xtal pic18f97j60 t1osi t1oso 32.768 khz 27 pf 27 pf oscillator type freq. c1 c2 lp 32 khz 27 pf (1) 27 pf (1) note 1: microchip suggests these values as a starting point in validating the oscillator circuit. 2: higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: capacitor values are for design guidance only. pic18f97j60 family ds39762a-page 170 advance information ? 2006 microchip technology inc. 12.3.2 timer1 oscillator layout considerations the timer1 oscillator circuit draws very little power during operation. due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. the oscillator circuit, shown in figure 12-3, should be located as close as possible to the microcontroller. there should be no circuits passing within the oscillator circuit boundaries other than v ss or v dd . if a high-speed circuit must be located near the oscilla- tor (such as the eccp1 pin in output compare or pwm mode, or the primary oscillator using the osc2 pin), a grounded guard ring around the oscillator circuit, as shown in figure 12-4, may be helpful when used on a single-sided pcb or in addition to a ground plane. figure 12-4: oscillator circuit with grounded guard ring 12.4 timer1 interrupt the tmr1 register pair (tmr1h:tmr1l) increments from 0000h to ffffh and rolls over to 0000h. the timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, tmr1if (pir1<0>). this interrupt can be enabled or disabled by setting or clearing the timer1 interrupt enable bit, tmr1ie (pie1<0>). 12.5 resetting timer1 using the eccp special event trigger if eccp1 or eccp2 is configured to use timer1 and to generate a special event trigger in compare mode (ccpxm3:ccpxm0 = 1011 ), this signal will reset timer3. the trigger from eccp2 will also start an a/d conversion if the a/d module is enabled (see section 17.2.1 ?special event trigger? for more information). the module must be configured as either a timer or a synchronous counter to take advantage of this feature. when used this way, the ccprxh:ccprxl register pair effectively becomes a period register for timer1. if timer1 is running in asynchronous counter mode, this reset operation may not work. in the event that a write to timer1 coincides with a special event trigger, the write operation will take precedence. 12.6 using timer1 as a real-time clock adding an external lp oscillator to timer1 (such as the one described in section 12.3 ?timer1 oscillator? ) gives users the option to include rtc functionality to their applications. this is accomplished with an inexpensive watch crystal to provide an accurate time base and several lines of application code to calculate the time. when operating in sleep mode and using a battery or supercapacitor as a power source, it can completely eliminate the need for a separate rtc device and battery backup. the application code routine, rtcisr , shown in example 12-1, demonstrates a simple method to increment a counter at one-second intervals using an interrupt service routine. incrementing the tmr1 register pair to overflow triggers the interrupt and calls the routine which increments the seconds counter by one. additional counters for minutes and hours are incremented as the previous counter overflows. since the register pair is 16 bits wide, counting up to overflow the register directly from a 32.768 khz clock would take 2 seconds. to force the overflow at the required one-second intervals, it is necessary to pre- load it. the simplest method is to set the msb of tmr1h with a bsf instruction. note that the tmr1l register is never preloaded or altered; doing so may introduce cumulative error over many cycles. for this method to be accurate, timer1 must operate in asynchronous mode and the timer1 overflow interrupt must be enabled (pie1<0> = 1 ), as shown in the routine, rtcinit . the timer1 oscillator must also be enabled and running at all times. v dd osc1 v ss osc2 rc0 rc1 rc2 note: not drawn to scale. note: the special event triggers from the eccpx module will not set the tmr1if interrupt flag bit (pir1<0>). ? 2006 microchip technology inc. advance information ds39762a-page 171 pic18f97j60 family example 12-1: implementing a real-time clock using a timer1 interrupt service table 12-2: registers associated with timer1 as a timer/counter rtcinit movlw 80h ; preload tmr1 register pair movwf tmr1h ; for 1 second overflow clrf tmr1l movlw b?00001111? ; configure for external clock, movwf t1con ; asynchronous operation, external oscillator clrf secs ; initialize timekeeping registers clrf mins ; movlw .12 movwf hours bsf pie1, tmr1ie ; enable timer1 interrupt return rtcisr bsf tmr1h, 7 ; preload for 1 sec overflow bcf pir1, tmr1if ; clear interrupt flag incf secs, f ; increment seconds movlw .59 ; 60 seconds elapsed? cpfsgt secs return ; no, done clrf secs ; clear seconds incf mins, f ; increment minutes movlw .59 ; 60 minutes elapsed? cpfsgt mins return ; no, done clrf mins ; clear minutes incf hours, f ; increment hours movlw .23 ; 24 hours elapsed? cpfsgt hours return ; no, done clrf hours ; reset hours return ; done name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 tmr1l timer1 register low byte 60 tmr1h timer1 register high byte 60 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 60 legend: shaded cells are not used by the timer1 module. pic18f97j60 family ds39762a-page 172 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 173 pic18f97j60 family 13.0 timer2 module the timer2 timer module incorporates the following features: ? 8-bit timer and period registers (tmr2 and pr2, respectively) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4 and 1:16) ? software programmable postscaler (1:1 through 1:16) ? interrupt on tmr2 to pr2 match ? optional use as the shift clock for the mssp module the module is controlled through the t2con register (register 13-1) which enables or disables the timer and configures the prescaler and postscaler. timer2 can be shut off by clearing control bit, tmr2on (t2con<2>), to minimize power consumption. a simplified block diagram of the module is shown in figure 13-1. 13.1 timer2 operation in normal operation, tmr2 is incremented from 00h on each clock (f osc /4). a 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by-16 prescale options. these options are selected by the prescaler control bits, t2ckps1:t2ckps0 (t2con<1:0>). the value of tmr2 is compared to that of the period register, pr2, on each clock cycle. when the two values match, the com- parator generates a match signal as the timer output. this signal also resets the value of tmr2 to 00h on the next cycle and drives the output counter/postscaler (see section 13.2 ?timer2 interrupt? ). the tmr2 and pr2 registers are both directly readable and writable. the tmr2 register is cleared on any device reset, while the pr2 register initializes at ffh. both the prescaler and postscaler counters are cleared on the following events: ? a write to the tmr2 register ? a write to the t2con register ? any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr2 is not cleared when t2con is written. register 13-1: t2con: ti mer2 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-3 t2outps3:t2outps0 : timer2 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale ? ? ? 1111 = 1:16 postscale bit 2 tmr2on : timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps1:t2ckps0 : timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 pic18f97j60 family ds39762a-page 174 advance information ? 2006 microchip technology inc. 13.2 timer2 interrupt timer2 can also generate an optional device interrupt. the timer2 output signal (tmr2 to pr2 match) pro- vides the input for the 4-bit output counter/postscaler. this counter generates the tmr2 match interrupt flag which is latched in tmr2if (pir1<1>). the interrupt is enabled by setting the tmr2 match interrupt enable bit, tmr2ie (pie1<1>). a range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, t2outps3:t2outps0 (t2con<6:3>). 13.3 timer2 output the unscaled output of tmr2 is available primarily to the ccp modules, where it is used as a time base for operations in pwm mode. timer2 can be optionally used as the shift clock source for the mssp module operating in spi mode. additional information is provided in section 19.0 ?master synchronous serial port (mssp) module? . figure 13-1: timer2 block diagram table 13-1: registers associated with timer2 as a timer/counter name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 tmr2 timer2 register 60 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 60 pr2 timer2 period register 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer2 module. comparator tmr2 output tmr2 postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 4 t2outps3:t2outps0 t2ckps1:t2ckps0 set tmr2if internal data bus 8 reset tmr2/pr2 8 8 (to pwm or mssp) match ? 2006 microchip technology inc. advance information ds39762a-page 175 pic18f97j60 family 14.0 timer3 module the timer3 timer/counter module incorporates these features: ? software selectable operation as a 16-bit timer or counter ? readable and writable 8-bit registers (tmr3h and tmr3l) ? selectable clock source (internal or external) with device clock or timer1 oscillator internal options ? interrupt-on-overflow ? module reset on ccp special event trigger a simplified block diagram of the timer3 module is shown in figure 14-1. a block diagram of the module?s operation in read/write mode is shown in figure 14-2. the timer3 module is controlled through the t3con register (register 14-1). it also selects the clock source options for the ccp and eccp modules; see section 16.1.1 ?ccp modules and timer resources? for more information. register 14-1: t3con: ti mer3 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t 3s ync tmr3cs tmr3on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rd16: 16-bit read/write mode enable bit 1 = enables register read/write of timer3 in one 16-bit operation 0 = enables register read/write of timer3 in two 8-bit operations bit 6,3 t3ccp2:t3ccp1: timer3 and timer1 to ccpx enable bits 11 = timer3 and timer4 are the clock sources for all ccp/eccp modules 10 = timer3 and timer4 are the clock sources for eccp3, ccp4 and ccp5; timer1 and timer2 are the clock sources for eccp1 and eccp2 01 = timer3 and timer4 are the clock sources for eccp2, eccp3, ccp4 and ccp5; timer1 and timer2 are the clock sources for eccp1 00 = timer1 and timer2 are the clock sources for all ccp/eccp modules bit 5-4 t3ckps1:t3ckps0: timer3 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 2 t 3s ync : timer3 external clock input synchronization select bit (not usable if the device clock comes from timer1/timer3.) when tmr 3c s = 1 : 1 = do not synchronize external clock input 0 = synchronize external clock input when tmr 3c s = 0 : this bit is ignored. timer3 uses the internal clock when tmr3cs = 0 . bit 1 tmr3cs: timer3 clock source select bit 1 = external clock input from timer1 oscillator or t13cki (on the rising edge after the first falling edge) 0 = internal clock (f osc /4) bit 0 tmr3on: timer3 on bit 1 = enables timer3 0 = stops timer3 pic18f97j60 family ds39762a-page 176 advance information ? 2006 microchip technology inc. 14.1 timer3 operation timer3 can operate in one of three modes: ?timer ? synchronous counter ? asynchronous counter the operating mode is determined by the clock select bit, tmr3cs (t3con<1>). when tmr3cs is cleared (= 0 ), timer3 increments on every internal instruction cycle (f osc /4). when the bit is set, timer3 increments on every rising edge of the timer1 external clock input or the timer1 oscillator, if enabled. as with timer1, the rc1/t1osi and rc0/t1oso/t13cki pins become inputs when the timer1 oscillator is enabled. this means the values of trisc<1:0> are ignored and the pins are read as ? 0 ?. figure 14-1: timer3 block diagram figure 14-2: timer3 block diagram (16-bit read/write mode) t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi 1 0 tmr3on tmr3l set tmr3if on overflow tmr3 high byte timer1 oscillator note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. on/off timer3 eccpx special event trigger eccpx select from t3con<6,3> clear tmr3 timer1 clock input t3sync tmr3cs t3ckps1:t3ckps0 sleep input t1oscen (1) f osc /4 internal clock prescaler 1, 2, 4, 8 synchronize detect 1 0 2 t1oso/t13cki t1osi note 1: when enable bit, t1oscen, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. 1 0 tmr3l internal data bus 8 set tmr3if on overflow tmr3 tmr3h high byte 8 8 8 read tmr1l write tmr1l 8 tmr3on eccpx special event trigger timer1 oscillator on/off timer3 timer1 clock input eccpx select from t3con<6,3> clear tmr3 ? 2006 microchip technology inc. advance information ds39762a-page 177 pic18f97j60 family 14.2 timer3 16-bit read/write mode timer3 can be configured for 16-bit reads and writes (see figure 14-2). when the rd16 control bit (t3con<7>) is set, the address for tmr3h is mapped to a buffer register for the high byte of timer3. a read from tmr3l will load the contents of the high byte of timer3 into the timer3 high byte buffer register. this provides the user with the ability to accurately read all 16 bits of timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. a write to the high byte of timer3 must also take place through the tmr3h buffer register. the timer3 high byte is updated with the contents of tmr3h when a write occurs to tmr3l. this allows a user to write all 16 bits to both the high and low bytes of timer3 at once. the high byte of timer3 is not directly readable or writable in this mode. all reads and writes must take place through the timer3 high byte buffer register. writes to tmr3h do not clear the timer3 prescaler. the prescaler is only cleared on writes to tmr3l. 14.3 using the timer1 oscillator as the timer3 clock source the timer1 internal oscillator may be used as the clock source for timer3. the timer1 oscillator is enabled by setting the t1oscen (t1con<3>) bit. to use it as the timer3 clock source, the tmr3cs bit must also be set. as previously noted, this also configures timer3 to increment on every rising edge of the oscillator source. the timer1 oscillator is described in section 12.0 ?timer1 module? . 14.4 timer3 interrupt the tmr3 register pair (tmr3h:tmr3l) increments from 0000h to ffffh and overflows to 0000h. the timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, tmr3if (pir2<1>). this interrupt can be enabled or disabled by setting or clearing the timer3 interrupt enable bit, tmr3ie (pie2<1>). 14.5 resetting timer3 using the eccp special event trigger if eccp1 or eccp2 is configured to use timer3 and to generate a special event trigger in compare mode (ccpxm3:ccpxm0 = 1011 ), this signal will reset timer3. the trigger from eccp2 will also start an a/d conversion if the a/d module is enabled (see section 17.2.1 ?special event trigger? for more information). the module must be configured as either a timer or synchronous counter to take advantage of this feature. when used this way, the ccprxh:ccprxl register pair effectively becomes a period register for timer3. if timer3 is running in asynchronous counter mode, the reset operation may not work. in the event that a write to timer3 coincides with a special event trigger from an eccp module, the write will take precedence. table 14-1: registers associated with timer3 as a timer/counter note: the special event triggers from the eccpx module will not set the tmr3if interrupt flag bit (pir2<1>). name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir2 oscfif cmif ethif r bcl1if ?tmr3if ccp2if 61 pie2 oscfie cmie ethie r bcl1ie ?tmr3ie ccp2ie 61 ipr2 oscfip cmip ethip r bcl1ip ?tmr3ip ccp2ip 61 tmr3l timer3 register low byte 60 tmr3h timer3 register high byte 60 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 60 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 60 legend: ? = unimplemented, read as ? 0 ?, r = reserved. shaded cells are not used by the timer3 module. pic18f97j60 family ds39762a-page 178 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 179 pic18f97j60 family 15.0 timer4 module the timer4 module has the following features: ? 8-bit timer register (tmr4) ? 8-bit period register (pr4) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16) ? software programmable postscaler (1:1 to 1:16) ? interrupt on tmr4 match of pr4 timer4 has a control register shown in register 15-1. timer4 can be shut off by clearing control bit, tmr4on (t4con<2>), to minimize power consumption. the prescaler and postscaler selection of timer4 are also controlled by this register. figure 15-1 is a simplified block diagram of the timer4 module. 15.1 timer4 operation timer4 can be used as the pwm time base for the pwm mode of the ccp module. the tmr4 register is readable and writable and is cleared on any device reset. the input clock (f osc /4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits t4ckps1:t4ckps0 (t4con<1:0>). the match out- put of tmr4 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a tmr4 interrupt, latched in flag bit tmr4if (pir3<3>). the prescaler and postscaler counters are cleared when any of the following occurs: ? a write to the tmr4 register ? a write to the t4con register ? any device reset (power-on reset, mclr reset, watchdog timer reset or brown-out reset) tmr4 is not cleared when t4con is written. register 15-1: t4con: ti mer4 control register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-3 t4outps3:t4outps0 : timer4 output postscale select bits 0000 = 1:1 postscale 0001 = 1:2 postscale ? ? ? 1111 = 1:16 postscale bit 2 tmr4on : timer4 on bit 1 = timer4 is on 0 = timer4 is off bit 1-0 t4ckps1:t4ckps0 : timer4 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 1x = prescaler is 16 pic18f97j60 family ds39762a-page 180 advance information ? 2006 microchip technology inc. 15.2 timer4 interrupt the timer4 module has an 8-bit period register, pr4, which is both readable and writable. timer4 increments from 00h until it matches pr4 and then resets to 00h on the next increment cycle. the pr4 register is initialized to ffh upon reset. 15.3 output of tmr4 the output of tmr4 (before the postscaler) is used only as a pwm time base for the ccp modules. it is not used as a baud rate clock for the mssp as is the timer2 output. figure 15-1: timer4 block diagram table 15-1: registers associated with timer4 as a timer/counter comparator tmr4 output tmr4 postscaler prescaler pr4 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16 4 t4outps3:t4outps0 t4ckps1:t4ckps0 set tmr4if internal data bus 8 reset tmr4/pr4 8 8 (to pwm) match name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 ipr3 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 61 pir3 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 61 tmr4 timer4 register 62 t4con ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 62 pr4 timer4 period register 62 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer4 module. ? 2006 microchip technology inc. advance information ds39762a-page 181 pic18f97j60 family 16.0 capture/compare/pwm (ccp) modules members of the pic18f97j60 family of devices all have a total of five ccp (capture/compare/pwm) modules. two of these (ccp4 and ccp5) implement standard capture, compare and pulse-width modulation (pwm) modes and are discussed in this section. the other three modules (eccp1, eccp2, eccp3) implement standard capture and compare modes, as well as enhanced pwm modes. these are discussed in section 17.0 ?enhanced capture/compare/pwm (eccp) module? . each ccp/eccp module contains a 16-bit register which can operate as a 16-bit capture register, a 16-bit compare register or a pwm master/slave duty cycle register. for the sake of clarity, all ccp module opera- tion in the following sections is described with respect to ccp4, but is equally applicable to ccp5. capture and compare operations described in this chapter apply to all standard and enhanced ccp modules. the operations of pwm mode, described in section 16.4 ?pwm mode? , apply to ccp4 and ccp5 only. note: throughout this section and section 17.0 ?enhanced capture/compare/pwm (eccp) module? , references to register and bit names that may be associated with a specific ccp module are referred to generically by the use of ?x? or ?y? in place of the specific module number. thus, ?ccpxcon? might refer to the control register for eccp1, eccp2, eccp3, ccp4 or ccp5. register 16-1: ccpxcon: ccpx control register (ccp4 and ccp5) u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dcxb1:dcxb0 : ccpx module pwm duty cycle bit 1 and bit 0 capture mode: unused. compare mode : unused. pwm mode: these bits are the two least significant bits (bit 1 and bit 0) of the 10-bit pwm duty cycle. the eight most significant bits (dcxb9:dcxb2) of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : ccpx module mode select bits 0000 = capture/compare/pwm disabled (resets ccpx module) 0001 = reserved 0010 = compare mode; toggle output on match (ccpxif bit is set) 0011 = reserved 0100 = capture mode; every falling edge 0101 = capture mode; every rising edge 0110 = capture mode; every 4th rising edge 0111 = capture mode; every 16th rising edge 1000 = compare mode; initialize ccpx pin low; on compare match, force ccpx pin high (ccpxif bit is set) 1001 = compare mode; initialize ccpx pin high; on compare match, force ccpx pin low (ccpxif bit is set) 1010 = compare mode; generate software interrupt on compare match (ccpxif bit is set, ccpx pin reflects i/o state) 1011 = reserved 11xx =pwm mode pic18f97j60 family ds39762a-page 182 advance information ? 2006 microchip technology inc. 16.1 ccp module configuration each capture/compare/pwm module is associated with a control register (generically, ccpxcon) and a data register (ccprx). the data register, in turn, is comprised of two 8-bit registers: ccprxl (low byte) and ccprxh (high byte). all registers are both readable and writable. 16.1.1 ccp modules and timer resources the ccp/eccp modules utilize timers 1, 2, 3 or 4, depending on the mode selected. timer1 and timer3 are available to modules in capture or compare modes, while timer2 and timer4 are available for modules in pwm mode. table 16-1: ccp mode ? timer resource the assignment of a particular timer to a module is determined by the timer to ccp enable bits in the t3con register (register 14-1, page 175). depending on the configuration selected, up to four timers may be active at once, with modules in the same configuration (capture/compare or pwm) sharing timer resources. the possible configurations are shown in figure 16-1. 16.1.2 eccp2 pin assignment the pin assignment for eccp2 (capture input, compare and pwm output) can change based on device configuration. the ccp2mx configuration bit determines which pin eccp2 is multiplexed to. by default, it is assigned to rc1 (ccp2mx = 1 ). if the configuration bit is cleared, eccp2 is multiplexed with re7 on 80-pin and 100-pin devices in microcontroller mode and rb3 on 100-pin devices in extended microcontroller mode. changing the pin assignment of eccp2 does not auto- matically change any requirements for configuring the port pin. users must always verify that the appropriate tris register is configured correctly for eccp2 operation regardless of where it is located. figure 16-1: ccp and timer interconnect configurations ccp mode timer resource capture compare pwm timer1 or timer3 timer1 or timer3 timer2 or timer4 tmr1 ccp5 tmr2 tmr3 tmr4 ccp4 eccp3 eccp2 eccp1 tmr1 tmr2 tmr3 ccp5 tmr4 ccp4 eccp3 eccp2 eccp1 tmr1 tmr2 tmr3 ccp5 tmr4 ccp4 eccp3 eccp2 eccp1 tmr1 tmr2 tmr3 ccp5 tmr4 ccp4 eccp3 eccp2 eccp1 t3ccp<2:1> = 00 t3ccp<2:1> = 01 t3ccp<2:1> = 10 t3ccp<2:1> = 11 timer1 is used for all capture and compare operations for all ccp modules. timer2 is used for pwm operations for all ccp modules. modules may share either timer resource as a common time base. timer3 and timer4 are not available. timer1 and timer2 are used for capture and compare or pwm operations for eccp1 only (depending on selected mode). all other modules use either timer3 or timer4. modules may share either timer resource as a common time base if they are in capture/compare or pwm modes. timer1 and timer2 are used for capture and compare or pwm operations for eccp1 and eccp2 only (depending on the mode selected for each module). both modules may use a timer as a common time base if they are both in capture/compare or pwm modes. the other modules use either timer3 or timer4. modules may share either timer resource as a common time base if they are in capture/compare or pwm modes. timer3 is used for all capture and compare operations for all ccp modules. timer4 is used for pwm operations for all ccp modules. modules may share either timer resource as a common time base. timer1 and timer2 are not available. ? 2006 microchip technology inc. advance information ds39762a-page 183 pic18f97j60 family 16.2 capture mode in capture mode, the ccprxh:ccprxl register pair captures the 16-bit value of the tmr1 or tmr3 registers when an event occurs on the corresponding ccpx pin. an event is defined as one of the following: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge the event is selected by the mode select bits, ccpxm3:ccpxm0 (ccpxcon<3:0>). when a capture is made, the interrupt request flag bit, ccpxif, is set; it must be cleared in software. if another capture occurs before the value in register ccprx is read, the old captured value is overwritten by the new captured value. 16.2.1 ccp pin configuration in capture mode, the appropriate ccpx pin should be configured as an input by setting the corresponding tris direction bit. 16.2.2 timer1/timer3 mode selection the timers that are to be used with the capture feature (timer1 and/or timer3) must be running in timer mode or synchronized counter mode. in asynchronous counter mode, the capture operation will not work. the timer to be used with each ccp module is selected in the t3con register (see section 16.1.1 ?ccp modules and timer resources? ). 16.2.3 software interrupt when the capture mode is changed, a false capture interrupt may be generated. the user should keep the ccpxie interrupt enable bit clear to avoid false interrupts. the interrupt flag bit, ccpxif, should also be cleared following any such change in operating mode. 16.2.4 ccp prescaler there are four prescaler settings in capture mode. they are specified as part of the operating mode selected by the mode select bits (ccpxm3:ccpxm0). whenever the ccp module is turned off or capture mode is disabled, the prescaler counter is cleared. this means that any reset will clear the prescaler counter. switching from one capture prescaler to another may generate an interrupt. also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. example 16-1 shows the recommended method for switching between capture prescalers. this example also clears the prescaler counter and will not generate the ?false? interrupt. example 16-1: changing between capture prescalers (ccp5 shown) figure 16-2: capture mode operat ion block diagram note: if rg4/ccp5/p1d is configured as an output, a write to the port can cause a capture condition. clrf ccp5con ; turn ccp module off movlw new_capt_ps ; load wreg with the ; new prescaler mode ; value and ccp on movwf ccp5con ; load ccp5con with ; this value ccpr4h ccpr4l tmr1h tmr1l set ccp4if tmr3 enable q1:q4 ccp4con<3:0> ccp4 pin prescaler 1, 4, 16 and edge detect tmr1 enable t3ccp2 t3ccp2 ccpr5h ccpr5l tmr1h tmr1l set ccp5if tmr3 enable ccp5con<3:0> ccp5 pin prescaler 1, 4, 16 tmr3h tmr3l tmr1 enable t3ccp2 t3ccp1 t3ccp2 t3ccp1 tmr3h tmr3l and edge detect 4 4 4 pic18f97j60 family ds39762a-page 184 advance information ? 2006 microchip technology inc. 16.3 compare mode in compare mode, the 16-bit ccprx register value is constantly compared against either the tmr1 or tmr3 register pair value. when a match occurs, the ccpx pin can be: ? driven high ? driven low ? toggled (high-to-low or low-to-high) ? remain unchanged (that is, reflects the state of the i/o latch) the action on the pin is based on the value of the mode select bits (ccpxm3:ccpxm0). at the same time, the interrupt flag bit, ccpxif, is set. 16.3.1 ccp pin configuration the user must configure the ccpx pin as an output by clearing the appropriate tris bit. 16.3.2 timer1/timer3 mode selection timer1 and/or timer3 must be running in timer mode or synchronized counter mode if the ccp module is using the compare feature. in asynchronous counter mode, the compare operation may not work. 16.3.3 software interrupt mode when the generate software interrupt mode is chosen (ccpxm3:ccpxm0 = 1010 ), the corresponding ccpx pin is not affected. only a ccp interrupt is generated, if enabled and the ccpxie bit is set. figure 16-3: compare mode operation block diagram note: clearing the ccp5con register will force the rg4 compare output latch (depend- ing on device configuration) to the default low level. this is not the portb or portc i/o data latch. ccpr4h ccpr4l tmr1h tmr1l comparator q s r output logic set ccp4if ccp4 pin tris ccp4con<3:0> output enable tmr3h tmr3l ccpr5h ccpr5l comparator 1 0 t3ccp2 t3ccp1 set ccp5if 1 0 compare 4 q s r output logic ccp5 pin tris ccp5con<3:0> output enable 4 match compare match ? 2006 microchip technology inc. advance information ds39762a-page 185 pic18f97j60 family table 16-2: registers associated with capture, compare, timer1 and timer3 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 rcon ipen ? ? ri to pd por bor 60 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir2 oscfif cmif ethif r bcl1if ?tmr3if ccp2if 61 pie2 oscfie cmie ethie r bcl1ie ?tmr3ie ccp2ie 61 ipr2 oscfip cmip ethip r bcl1ip ?tmr3ip ccp2ip 61 pir3 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 61 ipr3 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 61 trisg trisg7 trisg6 trisg5 trisg4 trisg3 (1) trisg2 trisg1 trisg0 61 tmr1l timer1 register low byte 60 tmr1h timer1 register high byte 60 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 60 tmr3h timer3 register high byte 60 tmr3l timer3 register low byte 60 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 60 ccpr4l capture/compare/pwm register 4 low byte 62 ccpr4h capture/compare/pwm register 4 high byte 62 ccpr5l capture/compare/pwm register 5 low byte 63 ccpr5h capture/compare/pwm register 5 high byte 63 ccp4con ? ? dc4b1 dc4b0 ccp4m3 ccp4m2 ccp4m1 ccp4m0 63 ccp5con ? ? dc5b1 dc5b0 ccp5m3 ccp5m2 ccp5m1 ccp5m0 63 legend: ? = unimplemented, read as ? 0 ?, r = reserved. shaded cells are not used by capture/compare, timer1 or timer3. note 1: this bit is only available in 80-pin and 100-pin devices; otherwise, it is unimplemented and reads as ? 0 ?. pic18f97j60 family ds39762a-page 186 advance information ? 2006 microchip technology inc. 16.4 pwm mode in pulse-width modulation (pwm) mode, the ccpx pin produces up to a 10-bit resolution pwm output. since the ccp4 and ccp5 pins are multiplexed with a portg data latch, the appropriate trisg bit must be cleared to make the ccp4 or ccp5 pin an output. figure 16-4 shows a simplified block diagram of the ccp module in pwm mode. for a step-by-step procedure on how to set up a ccp module for pwm operation, see section 16.4.3 ?setup for pwm operation? . figure 16-4: simplified pwm block diagram a pwm output (figure 16-5) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 16-5: pwm output 16.4.1 pwm period the pwm period is specified by writing to the pr2 (pr4) register. the pwm period can be calculated using equation 16-1: equation 16-1: pwm frequency is defined as 1/[pwm period]. when tmr2 (tmr4) is equal to pr2 (pr4), the following three events occur on the next increment cycle: ? tmr2 (tmr4) is cleared ? the ccpx pin is set (exception: if pwm duty cycle = 0%, the ccpx pin will not be set) ? the pwm duty cycle is latched from ccprxl into ccprxh 16.4.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccprxl register and to the ccpxcon<5:4> bits. up to 10-bit resolution is available. the ccprxl contains the eight msbs and the ccpxcon<5:4> contains the two lsbs. this 10-bit value is represented by ccprxl:ccpxcon<5:4>. equation 16-2 is used to calculate the pwm duty cycle in time. equation 16-2: ccprxl and ccpxcon<5:4> can be written to at any time, but the duty cycle value is not latched into ccprxh until after a match between pr2 (pr4) and tmr2 (tmr4) occurs (i.e., the period is complete). in pwm mode, ccprxh is a read-only register. note: clearing the ccp4con or ccp5con register will force the rg3 or rg4 output latch (depending on device configuration) to the default low level. this is not the portg i/o data latch. ccpr1l comparator comparator pr2 ccp1con<5:4> q s r eccp1 tris output enable ccpr1h tmr2 2 lsbs latched from q clocks reset match tmr2 = pr2 latch 0 9 (1) note 1: the two lsbs of the duty cycle register are held by a 2-bit latch that is part of the module?s hardware. it is physically separate from the ccprx registers. duty cycle register set ccpx pin duty cycle pin period duty cycle tmr2 (tmr4) = pr2 (tmr4) tmr2 (tmr4) = duty cycle tmr2 (tmr4) = pr2 (pr4) note: the timer2 and timer 4 postscalers (see section 13.0 ?timer2 module? and section 15.0 ?timer4 module? ) are not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period = [(pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value) pwm duty cycle = (ccpr x l:ccp x con<5:4>) ? t osc ? (tmr2 prescale value) ? 2006 microchip technology inc. advance information ds39762a-page 187 pic18f97j60 family the ccprxh register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm operation. when the ccprxh and 2-bit latch match tmr2 (tmr4), concatenated with an internal 2-bit q clock or 2 bits of the tmr2 (tmr4) prescaler, the ccpx pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by equation 16-3: equation 16-3: 16.4.3 setup for pwm operation the following steps should be taken when configuring the ccp module for pwm operation: 1. set the pwm period by writing to the pr2 (pr4) register. 2. set the pwm duty cycle by writing to the ccprxl register and ccpxcon<5:4> bits. 3. make the ccpx pin an output by clearing the appropriate tris bit. 4. set the tmr2 (tmr4) prescale value, then enable timer2 (timer4) by writing to t2con (t4con). 5. configure the ccpx module for pwm operation. table 16-3: example pwm frequencies and resolutions at 40 mhz note: if the pwm duty cycle value is longer than the pwm period, the ccpx pin will not be cleared. log ( f pwm log(2) f osc ) bits pwm resolution (max) = pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz timer prescaler (1, 4, 16)1641111 pr2 value ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 10 10 10 8 7 6.58 pic18f97j60 family ds39762a-page 188 advance information ? 2006 microchip technology inc. table 16-4: registers associated with pwm, timer2 and timer4 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 rcon ipen ? ? ri to pd por bor 60 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir3 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 61 ipr3 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 61 trisg trisg7 trisg6 trisg5 trisg4 trisg3 (1) trisg2 trisg1 trisg0 61 tmr2 timer2 register 60 pr2 timer2 period register 60 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 60 tmr4 timer4 register 62 pr4 timer4 period register 62 t4con ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 62 ccpr4l capture/compare/pwm register 4 low byte 62 ccpr4h capture/compare/pwm register 4 high byte 62 ccpr5l capture/compare/pwm register 5 low byte 63 ccpr5h capture/compare/pwm register 5 high byte 63 ccp4con ? ? dc4b1 dc4b0 ccp4m3 ccp4m2 ccp4m1 ccp4m0 63 ccp5con ? ? dc5b1 dc5b0 ccp5m3 ccp5m2 ccp5m1 ccp5m0 63 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by pwm, timer2 or timer4. note 1: this bit is only available in 80-pin and 100-pin devices; otherwise, it is unimplemented and reads as ? 0 ?. ? 2006 microchip technology inc. advance information ds39762a-page 189 pic18f97j60 family 17.0 enhanced capture/ compare/pwm (eccp) module in the pic18f97j60 family of devices, three of the ccp modules are implemented as standard ccp modules with enhanced pwm capabilities. these include the provision for 2 or 4 output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. the enhanced features are discussed in detail in section 17.4 ?enhanced pwm mode? . capture, compare and single-output pwm functions of the eccp module are the same as described for the standard ccp module. the control register for the enhanced ccp module is shown in register 17-1. it differs from the ccp4con/ ccp5con registers in that the two most significant bits are implemented to control pwm functionality. in addition to the expanded range of modes available through the enhanced ccpxcon register, the eccp modules each have two additional features associated with enhanced pwm operation and auto-shutdown features. they are: ? eccpxdel (dead-band delay) ? eccpxas (auto-shutdown configuration) register 17-1: ccpxcon: enhanced ccpx control register (eccp1/eccp2/eccp3) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pxm1 pxm0 dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 pxm1:pxm0: enhanced pwm output configuration bits if ccpxm3:ccpxm2 = 00 , 01 , 10 : xx = pxa assigned as capture/compare input/output; pxb, pxc, pxd assigned as port pins if ccpxm3:ccpxm2 = 11 : 00 = single output: pxa modulated; pxb, pxc, pxd assigned as port pins 01 = full-bridge output forward: p1d modulated; p1a active; p1b, p1c inactive 10 = half-bridge output: p1a, p1b modulated with dead-band control; p1c, p1d assigned as port pins 11 = full-bridge output reverse: p1b modulated; p1c active; p1a, p1d inactive bit 5-4 dcxb1:dcxb0 : eccpx module pwm duty cycle bit 1 and bit 0 capture mode: unused. compare mode : unused. pwm mode: these bits are the 2 lsbs of the 10-bit pwm duty cycle. the 8 msbs of the duty cycle are found in ccprxl. bit 3-0 ccpxm3:ccpxm0 : eccpx module mode select bits 0000 = capture/compare/pwm disabled (resets eccpx module) 0001 = reserved 0010 = compare mode; toggle output on match 0011 = capture mode 0100 = capture mode; every falling edge 0101 = capture mode; every rising edge 0110 = capture mode; every 4th rising edge 0111 = capture mode; every 16th rising edge 1000 = compare mode; initialize eccpx pin low; set output on compare match (set ccpxif) 1001 = compare mode; initialize eccpx pin high; clear output on compare match (set ccpxif) 1010 = compare mode; generate software interrupt only, eccpx pin reverts to i/o state) 1011 = compare mode; trigger special event (eccpx resets tmr1 or tmr3, sets ccpxif bit, eccp2 trigger also starts a/d conversion if a/d module is enabled) (1) 1100 = pwm mode; pxa, pxc active-high; pxb, pxd active-high 1101 = pwm mode; pxa, pxc active-high; pxb, pxd active-low 1110 = pwm mode; pxa, pxc active-low; pxb, pxd active-high 1111 = pwm mode; pxa, pxc active-low; pxb, pxd active-low note 1: implemented only for eccp1 and eccp2; same as ? 1010 ? for eccp3. pic18f97j60 family ds39762a-page 190 advance information ? 2006 microchip technology inc. 17.1 eccp outputs and configuration each of the enhanced ccp modules may have up to four pwm outputs, depending on the selected operating mode. these outputs, designated pxa through pxd, are multiplexed with various i/o pins. some eccpx pin assignments are constant, while others change based on device configuration. for those pins that do change, the controlling bits are: ? ccp2mx configuration bit (80-pin and100-pin devices only) ? eccpmx configuration bit (80-pin and100-pin devices only) ? program memory operating mode set by the emb configuration bits (100-pin devices only) the pin assignments for the enhanced ccp modules are summarized in table 17-1, table 17-2 and table 17-3. to configure the i/o pins as pwm outputs, the proper pwm mode must be selected by setting the pxmx and ccpxmx bits (ccpxcon<7:6> and <3:0>, respectively). the appropriate tris direction bits for the corresponding port pins must also be set as outputs. 17.1.1 eccp1/eccp3 outputs and program memory mode in 100-pin devices, the use of extended microcontroller mode has an indirect effect on the eccp1 and eccp3 pins in enhanced pwm modes. by default, pwm outputs p1b/p1c and p3b/p3c are multiplexed to porte pins, along with the high-order byte of the external memory bus. when the bus is active in extended microcontroller mode, it overrides the enhanced ccp outputs and makes them unavailable. because of this, eccp1 and eccp3 can only be used in compatible (single-output) pwm modes when the device is in extended microcontroller mode and default pin configuration. an exception to this configuration is when a 12-bit address width is selected for the external bus (emb1:emb0 configuration bits = 10 ). in this case, the upper pins of porte continue to operate as digital i/o, even when the external bus is active. p1b/p1c and p3b/p3c remain available for use as enhanced pwm outputs. if an application requires the use of additional pwm outputs during extended microcontroller mode, the p1b/p1c and p3b/p3c outputs can be reassigned to the upper bits of porth. this is done by clearing the eccpmx configuration bit. 17.1.2 eccp2 outputs and program memory modes for 100-pin devices, the program memory mode of the device ( section 5.1.3 ?pic18f9xj60/9xj65 program memory modes? ) also impacts pin multiplexing for the module. the eccp2 input/output (eccp2/p2a) can be multi- plexed to one of three pins. the default assignment (ccp2mx configuration bit is set) for all devices is rc1. clearing ccp2mx reassigns eccp2/p2a to re7. an additional option exists for 100-pin devices. when these devices are operating in microcontroller mode, the multiplexing options described above still apply. in extended microcontroller mode, clearing ccp2mx reassigns eccp2/p2a to rb3. 17.1.3 use of ccp4 and ccp5 with eccp1 and eccp3 only the eccp2 module has four dedicated output pins that are available for use. assuming that the i/o ports or other multiplexed functions on those pins are not needed, they may be used without interfering with any other ccp module. eccp1 and eccp3, on the other hand, only have three dedicated output pins: eccpx/pxa, pxb and pxc. whenever these modules are configured for quad pwm mode, the pin normally used for ccp4 or ccp5 becomes the pxd output pin for eccp3 and eccp1, respectively. the ccp4 and ccp5 modules remain functional but their outputs are overridden. 17.1.4 eccp modules and timer resources like the standard ccp modules, the eccp modules can utilize timers 1, 2, 3 or 4, depending on the mode selected. timer1 and timer3 are available for modules in capture or compare modes, while timer2 and timer4 are available for modules in pwm mode. additional details on timer resources are provided in section 16.1.1 ?ccp modules and timer resources? . ? 2006 microchip technology inc. advance information ds39762a-page 191 pic18f97j60 family table 17-1: pin configurations for eccp1 table 17-2: pin configurations for eccp2 eccp mode ccp1con configuration rc2 rd0 or re6 (1) re5 rg4 rh7 (2) rh6 (2) 64-pin devices; 80-pin devices, eccpmx = 1 ; 100-pin devices, eccpmx = 1 , microcontroller mode or extended microcontroller mode with 12-bit address width: compatible ccp 00xx 11xx eccp1 rd0/re6 re5 rg4/ccp5 rh7/an15 rh6/an14 dual pwm 10xx 11xx p1a p1b re5 rg4/ccp5 rh7/an15 rh6/an14 quad pwm x1xx 11xx p1a p1b p1c p1d rh7/an15 rh6/an14 80-pin devices, eccpmx = 0 ; 100-pin devices, eccpmx = 0 , all program memory modes: compatible ccp 00xx 11xx eccp1 rd0/re6 re5/ad13 rg4/ccp5 rh7/an15 rh6/an14 dual pwm 10xx 11xx p1a rd0/re6 re5/ad13 rg4/ccp5 p1b rh6/an14 quad pwm (3) x1xx 11xx p1a rd0/re6 re5/ad13 p1d p1b p1c 100-pin devices, eccpmx = 1 , extended microcontroller mode with 16-bit or 20-bit address width: compatible ccp 00xx 11xx eccp1 rd0/re6 re5/ad13 rg4/ccp5 rh7/an15 rh6/an14 legend: x = don?t care, n/a = not available. shaded cells indicate pin assignments not used by eccp1 in a given mode. note 1: p1b is multiplexed with rd0 on 64-pin devices, and re6 on 80-pin and 100-pin devices. 2: these pin options are not available on 64-pin devices. 3: with eccp1 in quad pwm mode, the ccp5 pin?s output is overridden by p1d; otherwise, ccp5 is fully operational. eccp mode ccp2con configuration rb3 rc1 re7 re2 re1 re0 all devices, ccp2mx = 1 , all program memory modes: compatible ccp 00xx 11xx rb3/int3 eccp2 re7 re2 re1 re0 dual pwm 10xx 11xx rb3/int3 p2a re7 p2b re1 re0 quad pwm x1xx 11xx rb3/int3 p2a re7 p2b p2c p2d 80-pin and 100-pin devices, ccp2mx = 0 , microcontroller mode: compatible ccp 00xx 11xx rb3/int3 rc1/t1os1 eccp2 re2 re1 re0 dual pwm 10xx 11xx rb3/int3 rc1/t1os1 p2a p2b re1 re0 quad pwm x1xx 11xx rb3/int3 rc1/t1os1 p2a p2b p2c p2d 100-pin devices, ccp2mx = 0 , extended microcontroller mode: compatible ccp 00xx 11xx eccp2 rc1/t1os1 re7/ad15 re2/cs re1/wr re0/rd dual pwm 10xx 11xx p2a rc1/t1os1 re7/ad15 p2b re1/wr re0/rd quad pwm x1xx 11xx p2a rc1/t1os1 re7/ad15 p2b p2c p2d legend: x = don?t care. shaded cells indicate pin assignments not used by eccp2 in a given mode. pic18f97j60 family ds39762a-page 192 advance information ? 2006 microchip technology inc. table 17-3: pin configurations for eccp3 17.2 capture and compare modes except for the operation of the special event trigger discussed below, the capture and compare modes of the eccp module are identical in operation to that of ccp4. these are discussed in detail in section 16.2 ?capture mode? and section 16.3 ?compare mode? . 17.2.1 special event trigger eccp1 and eccp2 incorporate an internal hardware trigger that is generated in compare mode on a match between the ccprx register pair and the selected timer. this can be used in turn to initiate an action. this mode is selected by setting ccpxcon<3:0> to ? 1011 ?. the special event trigger output of either eccp1 or eccp2 resets the tmr1 or tmr3 register pair, depending on which timer resource is currently selected. this allows the ccprx register to effectively be a 16-bit programmable period register for timer1 or timer3. in addition, the eccp2 special event trigger will also start an a/d conversion if the a/d module is enabled. special event triggers are not implemented for eccp3, ccp4 or ccp5. selecting the special event trigger mode for these modules has the same effect as selecting the compare with software interrupt mode (ccpxm3:ccpxm0 = 1010 ). 17.3 standard pwm mode when configured in single output mode, the eccp module functions identically to the standard ccp module in pwm mode as described in section 16.4 ?pwm mode? . this is also sometimes referred to as ?compatible ccp? mode as in tables 17-1 through 17-3. eccp mode ccp3con configuration rd1 or rg0 (1) re4 re3 rd2 or rg3 (1) rh5 (2) rh4 (2) 64-pin devices; 80-pin devices, eccpmx = 1 ; 100-pin devices, eccpmx = 1 , microcontroller mode: compatible ccp 00xx 11xx eccp3 re4 re3 rd2/rg3 rh5/an13 rh4/an12 dual pwm 10xx 11xx p3a p3b re3 rd2/rg3 rh5/an13 rh4/an12 quad pwm x1xx 11xx p3a p3b p3c p3d rh5/an13 rh4/an12 80-pin devices, eccpmx = 0 ; 100-pin devices, eccpmx = 0 , all program memory modes: compatible ccp 00xx 11xx eccp3 re6/ad14 re5/ad13 rd2/rg3 rh5/an13 rh4/an12 dual pwm 10xx 11xx p3a re6/ad14 re5/ad13 rd2/rg3 p3b rh4/an12 quad pwm (3) x1xx 11xx p3a re6/ad14 re5/ad13 p3d p3b p3c 100-pin devices, eccpmx = 1 , extended microcontroller with 12-bit address width: compatible ccp 00xx 11xx eccp3 re4/ad12 re3/ad11 rd2/rg3 rh5/an13 rh4/an12 dual pwm 10xx 11xx p3a p3b re3/ad11 rd2/rg3 rh5/an13 rh4/an12 100-pin devices, eccpmx = 1 , extended microcontroller mode with 16-bit or 20-bit address width: compatible ccp 00xx 11xx eccp3 re6/ad14 re5/ad13 rd2/rg3 rh5/an13 rh4/an12 legend: x = don?t care, n/a = not available. shaded cells indicate pin assignments not used by eccp3 in a given mode. note 1: eccp3/p3a and ccp4/p3d are multiplexed with rd1 and rd2 on 64-pin devices, and rg0 and rg3 on 80-pin and 100-pin devices. 2: these pin options are not available on 64-pin devices. 3: with eccp3 in quad pwm mode, the ccp4 pin?s output is overridden by p3d; otherwise, ccp4 is fully operational. note: the special event trigger from eccp2 will not set the timer1 or timer3 interrupt flag bits. note: when setting up single-output pwm operations, users are free to use either of the processes described in section 16.4.3 ?setup for pwm operation? or section 17.4.9 ?setup for pwm opera- tion? . the latter is more generic but will work for either single or multi-output pwm. ? 2006 microchip technology inc. advance information ds39762a-page 193 pic18f97j60 family 17.4 enhanced pwm mode the enhanced pwm mode provides additional pwm output options for a broader range of control applica- tions. the module is a backward compatible version of the standard ccp module and offers up to four outputs, designated pxa through pxd. users are also able to select the polarity of the signal (either active-high or active-low). the module?s output mode and polarity are configured by setting the pxm1:pxm0 and ccpxm3ccpxm0 bits of the ccpxcon register (ccpxcon<7:6> and ccpxcon<3:0>, respectively). for the sake of clarity, enhanced pwm mode operation is described generically throughout this section with respect to eccp1 and tmr2 modules. control register names are presented in terms of eccp1. all three enhanced modules, as well as the two timer resources, can be used interchangeably and function identically. tmr2 or tmr4 can be selected for pwm operation by selecting the proper bits in t3con. figure 17-1 shows a simplified block diagram of pwm operation. all control registers are double-buffered and are loaded at the beginning of a new pwm cycle (the period boundary when timer2 resets) in order to pre- vent glitches on any of the outputs. the exception is the eccp1 dead-band delay register, eccp1del, which is loaded at either the duty cycle boundary or the boundary period (whichever comes first). because of the buffering, the module waits until the assigned timer resets instead of starting immediately. this means that enhanced pwm waveforms do not exactly match the standard pwm waveforms but are instead offset by one full instruction cycle (4 t osc ). as before, the user must manually configure the appropriate tris bits for output. 17.4.1 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the equation: equation 17-1: pwm frequency is defined as 1/[pwm period]. when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the eccp1 pin is set (if pwm duty cycle = 0%, the eccp1 pin will not be set) ? the pwm duty cycle is copied from ccpr1l into ccpr1h figure 17-1: simplified block diagram of the enhanced pwm module note: the timer2 postscaler (see section 13.0 ?timer2 module? ) is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. pwm period = [(pr2) + 1] ? 4 ? t osc ? (tmr2 prescale value) ccpr1l ccpr1h (slave) comparator tmr2 comparator pr2 (note 1) rq s duty cycle registers ccp1con<5:4> clear timer, set eccp1 pin and latch d.c. note: the 8-bit timer tmr2 register is concatenated with the 2-bit internal q clock, or 2 bits of the prescaler, to create the 10-bit time base. trisx pic18f97j60 family ds39762a-page 194 advance information ? 2006 microchip technology inc. 17.4.2 pwm duty cycle the pwm duty cycle is specified by writing to the ccpr1l register and to the ccp1con<5:4> bits. up to 10-bit resolution is available. the ccpr1l contains the eight msbs and the ccp1con<5:4> contains the two lsbs. this 10-bit value is represented by ccprxl:ccpxcon<5:4>. the pwm duty cycle is calculated by the equation: equation 17-2: ccpr1l and ccp1con<5:4> can be written to at any time but the duty cycle value is not copied into ccpr1h until a match between pr2 and tmr2 occurs (i.e., the period is complete). in pwm mode, ccpr1h is a read-only register. the ccprxh register and a 2-bit internal latch are used to double-buffer the pwm duty cycle. this double-buffering is essential for glitchless pwm opera- tion. when the ccpr1h and 2-bit latch match tmr2, concatenated with an internal 2-bit q clock or two bits of the tmr2 prescaler, the eccp1 pin is cleared. the maximum pwm resolution (bits) for a given pwm frequency is given by the equation: equation 17-3: 17.4.3 pwm output configurations the p1m1:p1m0 bits in the ccp1con register allow one of four configurations: ? single output ? half-bridge output ? full-bridge output, forward mode ? full-bridge output, reverse mode the single output mode is the standard pwm mode discussed in section 17.4 ?enhanced pwm mode? . the half-bridge and full-bridge output modes are covered in detail in the sections that follow. the general relationship of the outputs in all configurations is summarized in figure 17-2. table 17-4: example pwm frequencies and resolutions at 40 mhz pwm duty cycle = (ccpr1l:ccp1con<5:4>) ? t osc ? (tmr2 prescale value) ( ) pwm resolution (max) = f osc f pwm log log(2) bits note: if the pwm duty cycle value is longer than the pwm period, the eccp1 pin will not be cleared. pwm frequency 2.44 khz 9.77 khz 39.06 khz 156.25 khz 312.50 khz 416.67 khz timer prescaler (1, 4, 16)1641111 pr2 value ffh ffh ffh 3fh 1fh 17h maximum resolution (bits) 10 10 10 8 7 6.58 ? 2006 microchip technology inc. advance information ds39762a-page 195 pic18f97j60 family figure 17-2: pwm output relationships (active-high state) figure 17-3: pwm output relationships (active-low state) 0 period 00 10 01 11 signal pr2 + 1 ccp1con<7:6> p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive duty cycle (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) 0 period 00 10 01 11 signal pr2 + 1 ccp1con<7:6> duty cycle (single output) (half-bridge) (full-bridge, forward) (full-bridge, reverse) delay (1) delay (1) relationships: ? period = 4 * t osc * (pr2 + 1) * (tmr2 prescale value) ? duty cycle = t osc * (ccpr1l<7:0>:ccp1con<5:4>) * (tmr2 prescale value) ? delay = 4 * t osc * (eccp1del<6:0>) note 1: dead-band delay is programmed us ing the eccp1del register ( section 17.4.6 ?programmable dead-band delay? ). p1a modulated p1a modulated p1b modulated p1a active p1b inactive p1c inactive p1d modulated p1a inactive p1b modulated p1c active p1d inactive pic18f97j60 family ds39762a-page 196 advance information ? 2006 microchip technology inc. 17.4.4 half-bridge mode in the half-bridge output mode, two pins are used as outputs to drive push-pull loads. the pwm output signal is output on the p1a pin, while the complemen- tary pwm output signal is output on the p1b pin (figure 17-4). this mode can be used for half-bridge applications, as shown in figure 17-5, or for full-bridge applications, where four power switches are being modulated with two pwm signals. in half-bridge output mode, the programmable dead-band delay can be used to prevent shoot-through current in half-bridge power devices. the value of bits pxdc6:pxdc0 sets the number of instruction cycles before the output is driven active. if the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. see section 17.4.6 ?programmable dead-band delay? for more details on dead-band delay operations. since the p1a and p1b outputs are multiplexed with the portc<2> and porte<6> data latches, the trisc<2> and trise<6> bits must be cleared to configure p1a and p1b as outputs. figure 17-4: half-bridge pwm output figure 17-5: examples of half-bri dge output mode applications period duty cycle td td (1) p1a (2) p1b (2) td = dead band delay period (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. 2: output signals are shown as active-high. pic18f97j60 p1a p1b fet driver fet driver v+ v- load + v - + v - fet driver fet driver v+ v- load fet driver fet driver pic18f97j60 p1a p1b standard half-bridge circuit (?push-pull?) half-bridge output driving a full-bridge circuit ? 2006 microchip technology inc. advance information ds39762a-page 197 pic18f97j60 family 17.4.5 full-bridge mode in full-bridge output mode, four pins are used as outputs; however, only two outputs are active at a time. in the forward mode, pin p1a is continuously active and pin p1d is modulated. in the reverse mode, pin p1c is continuously active and pin p1b is modulated. these are illustrated in figure 17-6. p1a, p1b, p1c and p1d outputs are multiplexed with the data latches of the port pins listed in table 17-1 and table 17-3. the corresponding tris bits must be cleared to make the p1a, p1b, p1c and p1d pins outputs. figure 17-6: full-bridge pwm output period duty cycle p1a (2) p1b (2) p1c (2) p1d (2) forward mode (1) period duty cycle p1a (2) p1c (2) p1d (2) p1b (2) reverse mode (1) (1) (1) note 1: at this time, the tmr2 register is equal to the pr2 register. note 2: output signal is shown as active-high. pic18f97j60 family ds39762a-page 198 advance information ? 2006 microchip technology inc. figure 17-7: example of full-bridge application 17.4.5.1 direction change in full-bridge mode in the full-bridge output mode, the p1m1 bit in the ccp1con register allows users to control the forward/ reverse direction. when the application firmware changes this direction control bit, the module will assume the new direction on the next pwm cycle. just before the end of the current pwm period, the modulated outputs (p1b and p1d) are placed in their inactive state, while the unmodulated outputs (p1a and p1c) are switched to drive in the opposite direction. this occurs in a time interval of (4 t osc * (timer2 prescale value) before the next pwm period begins. the timer2 prescaler will be either 1, 4 or 16, depend- ing on the value of the t2ckps bits (t2con<1:0>). during the interval from the switch of the unmodulated outputs to the beginning of the next period, the modulated outputs (p1b and p1d) remain inactive. this relationship is shown in figure 17-8. note that in the full-bridge output mode, the eccp1 module does not provide any dead-band delay. in gen- eral, since only one output is modulated at all times, dead-band delay is not required. however, there is a situation where a dead-band delay might be required. this situation occurs when both of the following conditions are true: 1. the direction of the pwm output changes when the duty cycle of the output is at or near 100%. 2. the turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. figure 17-9 shows an example where the pwm direc- tion changes from forward to reverse at a near 100% duty cycle. at time t1, the outputs p1a and p1d become inactive, while output p1c becomes active. in this example, since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current may flow through power devices qc and qd (see figure 17-7) for the duration of ?t?. the same phenomenon will occur to power devices qa and qb for pwm direction change from reverse to forward. if changing pwm direction at high duty cycle is required for an application, one of the following requirements must be met: 1. reduce pwm for a pwm period before changing directions. 2. use switch drivers that can drive the switches off faster than they can drive them on. other options to prevent shoot-through current may exist. pic18f97j60 p1a p1c fet driver fet driver v+ v- load fet driver fet driver p1b p1d qa qb qd qc ? 2006 microchip technology inc. advance information ds39762a-page 199 pic18f97j60 family figure 17-8: pwm direction change figure 17-9: pwm direction chang e at near 100% duty cycle dc period (1) signal note 1: the direction bit in the eccp1 control register (ccp1c on<7>) is written at any time during the pwm cycle. 2: when changing directions, the p1a and p1c signals switch before the end of the current pwm cycle at intervals of 4 t osc , 16 t osc or 64 t osc , depending on the timer2 prescaler value. the modulated p1b and p1d signals are inactive at this time. period (note 2) p1a (active-high) p1b (active-high) p1c (active-high) p1d (active-high) dc forward period reverse period p1a (1) t on (2) t off (3) t = t off ? t on (2,3) p1b (1) p1c (1) p1d (1) external switch d (1) potential shoot-through current (1) note 1: all signals are shown as active-high. 2: t on is the turn-on delay of power switch qc and its driver. 3: t off is the turn-off delay of power switch qd and its driver. external switch c (1) t1 dc dc pic18f97j60 family ds39762a-page 200 advance information ? 2006 microchip technology inc. 17.4.6 programmable dead-band delay in half-bridge applications, where all power switches are modulated at the pwm frequency at all times, the power switches normally require more time to turn off than to turn on. if both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period of time until one switch completely turns off. during this brief interval, a very high current ( shoot-through current ) may flow through both power switches, shorting the bridge supply. to avoid this potentially destructive shoot-through current from flow- ing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. in the half-bridge output mode, a digitally program- mable dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. the delay occurs at the signal transition from the non-active state to the active state. see figure 17-4 for illustration. the lower seven bits of the eccpxdel register (register 17-2) set the delay period in terms of microcontroller instruction cycles (t cy or 4 t osc ). 17.4.7 enhanced pwm auto-shutdown when the eccp1 is programmed for any of the enhanced pwm modes, the active output pins may be configured for auto-shutdown. auto-shutdown immedi- ately places the enhanced pwm output pins into a defined shutdown state when a shutdown event occurs. a shutdown event can be caused by either of the two comparator modules or the flt0 pin (or any combina- tion of these three source s). the comparators may be used to monitor a voltage input proportional to a current being monitored in the bridge circuit. if the voltage exceeds a threshold, the comparator switches state and triggers a shutdown. alternatively, a low-level digital signal on the flt0 pin can also trigger a shutdown. the auto-shutdown feature can be disabled by not selecting any auto-shutdown sources. the auto-shutdown sources to be used are selected using the eccp1as2:eccp1as0 bits (bits<6:4> of the eccp1as register). when a shutdown occurs, the output pins are asynchronously placed in their shutdown states, specified by the pss1ac1:pss1ac0 and pss1bd1:pss1bd0 bits (eccp1as3:eccp1as0). each pin pair (p1a/p1c and p1b/p1d) may be set to drive high, drive low or be tri-stated (not driving). the eccp1ase bit (eccp1as<7>) is also set to hold the enhanced pwm outputs in their shutdown states. the eccp1ase bit is set by hardware when a shutdown event occurs. if automatic restarts are not enabled, the eccp1ase bit is cleared by firmware when the cause of the shutdown clears. if automatic restarts are enabled, the ecc1pase bit is automatically cleared when the cause of the auto-shutdown has cleared. if the eccp1ase bit is set when a pwm period begins, the pwm outputs remain in their shutdown state for that entire pwm period. when the eccp1ase bit is cleared, the pwm outputs will return to normal operation at the beginning of the next pwm period. note: writing to the eccp1ase bit is disabled while a shutdown condition is active. register 17-2: eccpxdel: eccpx dead-band delay register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pxrsen pxdc6 pxdc5 pxdc4 pxdc3 pxdc2 pxdc1 pxdc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 pxrsen: pwm restart enable bit 1 = upon auto-shutdown, the eccpxase bit clears automatically once the shutdown event goes away; the pwm restarts automatically 0 = upon auto-shutdown, eccpxase must be cleared in software to restart the pwm bit 6-0 pxdc6:pxdc0: pwm delay count bits delay time, in number of f osc /4 (4 * t osc ) cycles, between the scheduled and actual time for a pwm signal to transition to active. ? 2006 microchip technology inc. advance information ds39762a-page 201 pic18f97j60 family 17.4.7.1 auto-shutdown and automatic restart the auto-shutdown feature can be configured to allow automatic restarts of the module following a shutdown event. this is enabled by setting the p1rsen bit of the eccp1del register (eccp1del<7>). in shutdown mode with p1rsen = 1 (figure 17-10), the eccp1ase bit will remain set for as long as the cause of the shutdown continues. when the shutdown condition clears, the eccp1ase bit is cleared. if p1rsen = 0 (figure 17-11), once a shutdown condi- tion occurs, the eccp1ase bit will remain set until it is cleared by firmware. once eccp1ase is cleared, the enhanced pwm will resume at the beginning of the next pwm period. independent of the p1rsen bit setting, if the auto-shutdown source is one of the comparators, the shutdown condition is a level. the eccp1ase bit cannot be cleared as long as the cause of the shutdown persists. the auto-shutdown mode can be forced by writing a ? 1 ? to the eccp1ase bit. 17.4.8 start-up considerations when the eccp module is used in the pwm mode, the application hardware must use the proper external pull-up and/or pull-down resistors on the pwm output pins. when the microcontroller is released from reset, all of the i/o pins are in the high-impedance state. the external circuits must keep the power switch devices in the off state until the microcontroller drives the i/o pins with the proper signal levels, or activates the pwm output(s). the ccp1m1:ccp1m0 bits (ccp1con<1:0>) allow the user to choose whether the pwm output signals are active-high or active-low for each pair of pwm output pins (p1a/p1c and p1b/p1d). the pwm output polarities must be selected before the pwm pins are configured as outputs. changing the polarity configura- tion while the pwm pins are configured as outputs is not recommended since it may result in damage to the application circuits. register 17-3: eccpxas: eccpx aut o-shutdown configuration register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 eccpxase eccpxas2 eccpxas1 eccpxas0 pssxac1 pssxac0 pssxbd1 pssxbd0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 eccpxase: eccpx auto-shutdown event status bit 0 = eccpx outputs are operating 1 = a shutdown event has occurred; eccpx outputs are in shutdown state bit 6-4 eccpxas2:eccpxas0: eccpx auto-shutdown source select bits 000 = auto-shutdown is disabled 001 = comparator 1 output 010 = comparator 2 output 011 = either comparator 1 or 2 100 =flt0 101 = flt0 or comparator 1 110 = flt0 or comparator 2 111 =flt0 or comparator 1 or comparator 2 bit 3-2 pssxac1:pssxac0: pins a and c shutdown state control bits 00 = drive pins a and c to ? 0 ? 01 = drive pins a and c to ? 1 ? 1x = pins a and c tri-state bit 1-0 pssxbd1:pssxbd0: pins b and d shutdown state control bits 00 = drive pins b and d to ? 0 ? 01 = drive pins b and d to ? 1 ? 1x = pins b and d tri-state note: writing to the eccp1ase bit is disabled while a shutdown condition is active. pic18f97j60 family ds39762a-page 202 advance information ? 2006 microchip technology inc. the p1a, p1b, p1c and p1d output latches may not be in the proper states when the pwm module is initialized. enabling the pwm pins for output at the same time as the eccp module may cause damage to the applica- tion circuit. the eccp module must be enabled in the proper output mode and complete a full pwm cycle before configuring the pwm pins as outputs. the com- pletion of a full pwm cycle is indicated by the tmr2if bit being set as the second pwm period begins. figure 17-10: pwm auto-shutdown (p1rsen = 1 , auto-restart enabled) figure 17-11: pwm auto-shutdown (p1rsen = 0 , auto-restart disabled) shutdown pwm eccp1ase bit activity event shutdown event occurs shutdown event clears pwm resumes normal pwm start of pwm period pwm period shutdown pwm eccp1ase bit activity event shutdown event occurs shutdown event clears pwm resumes normal pwm start of pwm period eccp1ase cleared by firmware pwm period ? 2006 microchip technology inc. advance information ds39762a-page 203 pic18f97j60 family 17.4.9 setup for pwm operation the following steps should be taken when configuring the eccpx module for pwm operation: 1. configure the pwm pins pxa and pxb (and pxc and pxd, if used) as inputs by setting the corresponding tris bits. 2. set the pwm period by loading the pr2 (pr4) register. 3. configure the eccpx module for the desired pwm mode and configuration by loading the ccpxcon register with the appropriate values: ? select one of the available output configurations and direction with the pxm1:pxm0 bits. ? select the polarities of the pwm output signals with the ccpxm3:ccpxm0 bits. 4. set the pwm duty cycle by loading the ccprxl register and the ccpxcon<5:4> bits. 5. for auto-shutdown: ? disable auto-shutdown; eccp1ase = 0 ? configure auto-shutdown source ? wait for run condition 6. for half-bridge output mode, set the dead-band delay by loading eccpxdel<6:0> with the appropriate value. 7. if auto-shutdown operation is required, load the eccpxas register: ? select the auto-shutdown sources using the eccpxas2:eccpxas0 bits. ? select the shutdown states of the pwm output pins using pssxac1:pssxac0 and pssxbd1:pssxbd0 bits. ? set the eccpxase bit (eccpxas<7>). 8. if auto-restart operation is required, set the pxrsen bit (eccpxdel<7>). 9. configure and start tmrx (tmr2 or tmr4): ? clear the tmrx interrupt flag bit by clearing the tmrxif bit (pir1<1> for timer2 or pir3<3> for timer4). ? set the tmrx prescale value by loading the txckps bits (txcon<1:0>). ? enable timer2 (or timer4) by setting the tmrxon bit (txcon<2>). 10. enable pwm outputs after a new pwm cycle has started: ? wait until tmrx overflows (tmrxif bit is set). ? enable the eccpx/pxa, pxb, pxc and/or pxd pin outputs by clearing the respective tris bits. ? clear the eccpxase bit (eccpxas<7>). 17.4.10 effects of a reset both power-on reset and subsequent resets will force all ports to input mode and the ccp registers to their reset states. this forces the enhanced ccp module to reset to a state compatible with the standard ccp module. pic18f97j60 family ds39762a-page 204 advance information ? 2006 microchip technology inc. table 17-5: registers associated with eccp modules and timer1 to timer4 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 rcon ipen ? ? ri to pd por bor 60 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir2 oscfif cmif ethif r bcl1if ? tmr3if ccp2if 61 pie2 oscfie cmie ethie r bcl1ie ? tmr3ie ccp2ie 61 ipr2 oscfip cmip ethip r bcl1ip ? tmr3ip ccp2ip 61 pir3 ssp2if bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 61 ipr3 ssp2ip bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 61 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 61 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 61 trisd (1) trisd7 trisd6 trisd5 trisd4 trisd3 trisd2 trisd1 trisd0 61 trise trise7 trise6 trise5 trise4 trise3 trise2 trise1 trise0 61 trisg trisg7 (2) trisg6 (2) trisg5 (2) trisg4 trisg3 (2) trisg2 (2) trisg1 (2) trisg0 (2) 61 trish (2) trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 61 tmr1l timer1 register low byte 60 tmr1h timer1 register high byte 60 t1con rd16 t1run t1ckps1 t1ckps0 t1oscen t1sync tmr1cs tmr1on 60 tmr2 timer2 register 60 t2con ? t2outps3 t2outps2 t2outps1 t2outps0 tmr2on t2ckps1 t2ckps0 60 pr2 timer2 period register 60 tmr3l timer3 register low byte 60 tmr3h timer3 register high byte 60 t3con rd16 t3ccp2 t3ckps1 t3ckps0 t3ccp1 t3sync tmr3cs tmr3on 60 tmr4 timer4 register 62 t4con ? t4outps3 t4outps2 t4outps1 t4outps0 tmr4on t4ckps1 t4ckps0 62 pr4 timer4 period register 62 ccprxl (3) capture/compare/pwm register x low byte 60 ccprxh (3) capture/compare/pwm register x high byte 60 ccpxcon (3) pxm1 pxm0 dcxb1 dcxb0 ccpxm3 ccpxm2 ccpxm1 ccpxm0 60 eccpxas (3) eccpxase eccpxas2 eccpxas1 eccpxas0 pssxac1 pssxac0 pssxbd1 pssxbd0 60, 63 eccpxdel (3) pxrsen pxdc6 pxdc5 pxdc4 pxdc3 pxdc2 pxdc1 pxdc0 63 legend: ? = unimplemented, read as ? 0 ?, r = reserved. shaded cells are not used during eccp operation. note 1: applicable to 64-pin devices only. 2: registers and/or specific bits are unimplemented on 64-pin devices. 3: generic term for all of the identical registers of this name for all enhanced ccp modules, where ?x? identifies the individual module (eccp1, eccp2 or eccp3). bit assignments and reset values for all registers of the same generic name are identical. ? 2006 microchip technology inc. advance information ds39762a-page 205 pic18f97j60 family 18.0 ethernet module all members of the pic18f97j60 family of devices feature an embedded ethernet controller module. this is a complete connectivity solution, including full imple- mentations of both media access control (mac) and physical layer transceiver (phy) modules. two pulse transformers and a few passive components are all that are required to connect the microcontroller directly to an ethernet network. the ethernet module meets all of the ieee 802.3 specifications for 10-baset connectivity to a twisted-pair network. it incorporates a number of packet filtering schemes to limit incoming packets. it also provides an internal dma module for fast data throughput and hardware assisted ip checksum calcu- lations. provisions are also made for two led outputs to indicate link and network activity. a simple block diagram of the module is shown in figure 18-1. the ethernet module consists of five major functional blocks: 1. the phy transceiver module that encodes and decodes the analog data that is present on the twisted-pair interface and sends or receives it over the network. 2. the mac module that implements ieee 802.3 compliant mac logic and provides media independent interface management (miim) to control the phy. 3. an independent, 8-kbyte ram buffer for storing packets that have been received and packets that are to be transmitted. 4. an arbiter to control access to the ram buffer when requests are made from the microcontroller core, dma, transmit and receive blocks 5. the register interface that functions as an inter- preter of commands and internal status signals between the module and the microcontroller?s sfrs. figure 18-1: ethernet module block diagram dma and ip checksum txbm rxbm arbiter flow control host interface phy mii interface miim interface tpout+ tpout- tpin+ tpin- tx rx rbias rxf (filter) rx tx mac ch0 ch1 ch0 ch1 ethernet ram buffer edata ethernet control ethernet buffer pointers mird/miwr miregadr phy register data phy register addresses ethernet data ethernet buffer addresses microcontroller sfrs microcontroller data bus leda/ledb control 8 8-kbyte ch2 pic18f97j60 family ds39762a-page 206 advance information ? 2006 microchip technology inc. 18.1 physical interfaces and external connections 18.1.1 signal and power interfaces pic18f97j60 family devices all provide a dedicated 4-pin signal interface for the ethernet module. no other microcontroller or peripheral functions are multiplexed with these pins, so potential device configuration conflicts do not need to be considered. the pins are: ? tpin+: differential plus twisted-pair input ? tpin-: differential minus twisted-pair input ? tpout+: differential plus twisted-pair output ? tpout-: differential minus twisted-pair output provisions are not made for providing or receiving digital ethernet data from an external ethernet controller or mac/phy subsystem. in addition to the signal connections, the ethernet mod- ule has its own independent voltage source and ground connections for the phy module. separate connections are provided for the receiver (v ddrx and v ssrx ), the transmitter (v ddtx and v sstx ) and the transmitter?s internal pll (v ddpll and v sspll ). although the voltage requirements are the same as v dd and v ss for the microcontroller, the pins are not internally connected. for the ethernet module to operate properly, supply voltage and ground must also be connected to these pins. a microcontroller power and ground supply pins should be externally connected to the same power source or ground node. besides the independent voltage connections, the phy module has a separate bias current input pin, rbias. a bias current must be applied to rbias for proper transceiver operation. 18.1.2 led configuration the phy module provides separate outputs to drive the standard ethernet indicators, leda and ledb. the led outputs are multiplexed with porta pins ra0 and ra1. their use as led outputs is enabled by setting the con- figuration bit, ethled (register 24-6, config3h<2>). when configured as led outputs, ra0/leda and ra1/ledb have sufficient drive capacity (8 ma) to directly power the leds. the pins must always be configured to supply current to (source) the leds. users must also configure the pins as outputs, by clearing trisa<1:0>. the leds can be individually configured to automatically display link status, rx/tx activity, etc. a configurable stretch capability prolongs the led blink duration for short events, such as a single packet transmit, allowing human perception. the options are controlled by the phlcon register (register 18-14). typical values for blink stretch are listed in table 18-1. table 18-1: led blink stretch length 18.1.3 oscillator requirements the ethernet module is designed to operate at 25 mhz. this is provided by the primary microcontroller clock, either with a crystal connected to the osc1 and osc2 pins or an external clock source connected to the osc1 pin. no provision is made to clock the module from a different source. 18.1.3.1 start-up timer the ethernet module contains a start-up timer, independent of the microcontroller?s ost, to ensure that the phy module?s pll has stabilized before operation. clearing the module enable bit, ethen (econ2<5>), clears the phyrdy status bit (estat<0>). setting the ethen bit causes this start-up timer to start counting. when the timer expires, after 1 ms, the phyrdy bit will be automatically set. the application software should always poll phyrdy as necessary to determine when normal ethernet operation can begin. stretch length typical stretch (ms) t nstrch (normal) 40 t mstrch (medium) 70 t lstrch (long) 140 ? 2006 microchip technology inc. advance information ds39762a-page 207 pic18f97j60 family 18.1.4 magnetics, termination and other external components to complete the ethernet interface, the ethernet module requires several standard components to be installed externally. these components should be connected as shown in figure 18-2. the internal analog circuitry in the phy module requires that an external resistor, r ebias , be attached from rbias to ground. the resistor influences the tpout+/- signal amplitude. the resistor should be placed as close as possible to the chip with no immediately adjacent signal traces to prevent noise capacitively coupling into the pin and affecting the transmit behavior. it is recommended that the resistor be a surface mount type. on the tpin+/tpin- and tpout+/tpout- pins, 1:1 center taped pulse transformers rated for ethernet operations are required. when the ethernet module is enabled, current is continually sunk through both tpout pins. when the phy is actively transmitting, a differential voltage is created on the ethernet cable by varying the relative current sunk by tpout+ compared to tpout-. a common mode choke on the tpout interface, placed between the tpout pins and the ethernet transformer (not shown), is not recommend. if a common mode choke is used to reduce emi emissions, it should be placed between the ethernet transformer and pins 1 and 2 of the rj-45 connector. many ethernet transformer modules include common mode chokes inside the same device package. the transformers should have at least the isolation rating specified in table 27-28 to protect against static voltages and meet ieee 802.3 isolation requirements (see section 27.5 ?ethernet specifications and requirements? for specific transformer requirements). both transmit and receive interfaces additionally require two resistors and a capacitor to properly terminate the transmission line, minimizing signal reflections. all power supply pins must be externally connected to the same power source. similarly, all ground refer- ences must be externally connected to the same ground node. each v dd and v ss pin pair should have a 0.1 f ceramic bypass capacitor placed as close to the pins as possible. since relatively high currents are necessary to operate the twisted-pair interface, all wires should be kept as short as possible. reasonable wire widths should be used on power wires to reduce resistive loss. if the differential data lines cannot be kept short, they should be routed in such a way as to have a 50 characteristic impedance. figure 18-2: external components required for ethernet operation 1 pic18fxxj6x leda ledb rbias tpout+ tpout- tpin+ tpin- 1 2 3 4 5 6 7 8 rj-45 1:1 ct 1:1 ct ferrite bead (1,3) 0.1 f (3) 3.3v note 1: ferrite bead should be rated for at least 80 ma. 2: resistor value r ebias to be determined. see current silicon errata for proper value. 3: these components are installed for emi reduction purposes. 49.9 , 1% 49.9 , 1% 49.9 , 1% 49.9 , 1% r ebias (2) 0.1 f 75 (3) 1 nf, 2 kv (3) 75 (3) 75 (3) 75 (3) pic18f97j60 family ds39762a-page 208 advance information ? 2006 microchip technology inc. 18.2 ethernet buffer and register spaces the ethernet module uses three independent memory spaces for its operations: ? an ethernet ram buffer which stores packet data as it is received and being prepared for transmission. ? a set of 8-bit special function registers (sfrs), used to control the module and pass data back and forth between the module and microcontroller core. ? a separate set of 16-bit phy registers used specifically for phy control and status reporting. the ethernet buffer and phy control registers are con- tained entirely within the ethernet module and cannot be accessed directly by the microcontroller. data is transferred between the ethernet and microcontroller by using buffer and pointer registers mapped in the microcontroller?s sfr space. the relationships between the sfrs and the ethernet module?s memory spaces are shown in figure 18-3. figure 18-3: relationship between microcontroller and ethernet memory spaces 0000h 1fffh ethernet buffer 00h 1fh phy registers ethernet module microcontroller sfrs edata erdpt(h:l) ewrpt(h:l) etxst(h:l) etxnd(h:l) erxst(h:l) erxnd(h:l) erxrdpt(h:l) erxwrpt(h:l) mird(h:l) miwr(h:l) miregadr ethernet data buffer address phy register data (in/out) phy register address note 1: microcontroller sfrs are not shown in the order of their placement in the data memory space. memory areas are not shown to scale. ? 2006 microchip technology inc. advance information ds39762a-page 209 pic18f97j60 family 18.2.1 ethernet buffer and buffer pointer registers the ethernet buffer contains the transmit and receive memory used by the ethernet controller. the entire buffer is 8 kbytes, divided into separate receive and transmit buffer spaces. the buffer is always accessible through the edata and ethernet pointer sfrs, regardless of whether or not the ethernet module is enabled. the sizes and locations of transmit and receive memory are fully definable using the pointers in the ethernet sfr space. 18.2.1.1 receive buffer the receive buffer constitutes a circular fifo buffer managed by hardware. the register pairs, erxsth:erxstl and erxndh:erxndl, serve as pointers to define the buffer?s size and location within the memory. the byte pointed to by erxst and the byte pointed to by erxnd are both included in the fifo buffer. as bytes of data are received from the ethernet interface, they are written into the receive buffer sequentially. however, after the memory pointed to by erxnd is written to, the hardware will automatically write the next byte of received data to the memory pointed to by erxst. as a result, the receive hardware will never write outside the boundaries of the fifo. the user may program the erxst and erxnd pointers while the receive logic is disabled. the point- ers must not be modified while the receive logic is enabled; erxen (econ1<2>) is set. the erxwrpth:erxwrptl registers define a location within the fifo where the hardware will write bytes that it receives. the pointer is read only and is automatically updated by the hardware whenever a new packet is received, depending on the hardware filter settings. the pointer is useful for determining how much free space is available within the fifo. the erxrdpt registers define a location within the fifo where the receive hardware is forbidden to write to. in normal operation, the receive hardware will write data up to, but not including, the memory pointed to by erxrdpt. if the fifo fills up with data and new data continues to arrive, the hardware will not overwrite the previously received data. instead, the incoming data will be thrown away and the old data will be preserved. in order to continuously receive new data, the application must periodically advance this pointer whenever it finishes processing some, or all, of the old received data. 18.2.1.2 transmit buffer any space within the 8-kbyte memory which is not programmed as part of the receive fifo buffer is consid- ered to be the transmit buffer. the responsibility of managing where packets are located in the transmit buffer belongs to the application. whenever the applica- tion decides to transmit a packet, the etxst and etxnd pointers are programmed with addresses specifying where, within the transmit buffer, the particular packet to transmit is located. the hardware does not check that the start and end addresses do not overlap with the receive buffer. to prevent buffer corruption, the firmware must not transmit a packet while the etxst and etxnd pointers are overlapping the receive buffer, or while the etxnd pointer is too close to the receive buffer. see section 18.5.2 ?transmitting packets? for more information. 18.2.1.3 reading and writing to the buffer the ethernet buffer contents are accessed through the edata register, which acts as a window from the microcontroller data bus into the buffer. the location of the window is determined by either the erdpt or ewrpt pointers, depending on the operation being performed. for example, writing to edata causes a write to the ethernet buffer at the address currently indicated by ewrpth:ewrptl. similarly, moving the contents of edata to another register actually moves the buffer contents at the address indicated by the erdpth:erdptl registers. setting the autoinc bit (econ2<7>) causes the associated read or write pointer to increment by one address following each read or write operation. this eliminates the need to constantly update a pointer after each read or write, simplifying multiple sequential operations. while sequentially reading from the receive buffer, a wrapping condition will occur at the end of the receive buffer. a read of edata from the address programmed into the erxndh:erxndh registers will cause erdpth:erdptl to be incremented to the value contained in the erxsth:erxstl registers. while sequentially writing to the buffer, no wrapping conditions will occur. 18.2.1.4 dma access to the buffer the integrated dma controller must read from the buffer when calculating a checksum, and it must read and write to the buffer when copying memory. the dma follows the same wrapping rules as previously described. while it sequentially reads, it will be subject to a wrapping condition at the end of the receive buffer. all writes it does will not be subject to any wrapping conditions. see section 18.9 ?direct memory access controller? for more information. pic18f97j60 family ds39762a-page 210 advance information ? 2006 microchip technology inc. figure 18-4: ethernet buffer organization transmit buffer 0000h 1fffh transmit buffer start (etxsth:etxstl) transmit buffer end (etxndh:etxndl) receive buffer start (erxsth:erxstl) receive buffer end (erxndh:erxndl) receive buffer buffer write pointer (ewrpth:ewrptl) aah write buffer data buffer read pointer (erdpth:erdptl) read buffer data (circular fifo) 55h (data 55h moved out of edata) (data aah moved to edata) ? 2006 microchip technology inc. advance information ds39762a-page 211 pic18f97j60 family 18.2.2 sfrs and the ethernet module like other peripherals, direct control of the ethernet module is accomplished through a set of sfrs. because of their large number, the majority of these registers are located in the bottom half of bank 14 of the microcontroller?s data memory space. five key sfrs for the ethernet module are located in the microcontroller?s regular sfr area in bank 15, where fast access is possible. they are: ? econ1 ?edata ?eir ? the ethernet buffer read pointer pair (erdpth and erdptl) econ1 is described along with other ethernet control registers in the following section. edata and erdpth:erdptl are the ethernet data buffer registers and its pointers during read operations (see section 18.2.1 ?ethernet buffer and buffer pointer registers? ). eir is part of the ethernet interrupt structure and is described in section 18.3 ?ethernet interrupts? . many of the ethernet sfrs in bank 14 serve as pointer registers to indicate addresses within the dedicated ethernet buffer for storage and retrieval of packet data. others store information for packet pattern masks or checksum operations. several are used for controlling overall module operations, as well as specific mac and phy functions. 18.2.3 ethernet control registers the econ1 register (register 18-1) is used to control the main functions of the module. receive enable, trans- mit request and dma control bits are all located here. the econ2 register (register 18-2) is used to control other top level functions of the module. the estat register (register 18-3) is us ed to report the high-level status of the module and ethernet communications. the ethernet sfrs with the ?e? prefix are always accessible, regardless of whether or not the module is enabled. register 18-1: econ1: ethernet control register 1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 u-0 txrst rxrst dmast csumen txrts rxen ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 txrst: transmit logic reset bit 1 = transmit logic is held in reset 0 = normal operation bit 6 rxrst: receive logic reset bit 1 = receive logic is held in reset 0 = normal operation bit 5 dmast: dma start and busy status bit 1 = dma copy or checksum operation is in progress (set by software, cleared by hardware or software) 0 = dma hardware is idle bit 4 csumen: dma checksum enable bit 1 = dma hardware calculates checksums 0 = dma hardware copies buffer memory bit 3 txrts: transmit request to send bit 1 = the transmit logic is attempting to transmit a packet (set by software, cleared by hardware or software) 0 = the transmit logic is idle bit 2 rxen: receive enable bit 1 = packets which pass the current filter configuration will be written into the receive buffer 0 = all packets received will be discarded by hardware bit 1-0 unimplemented: read as ? 0 ? pic18f97j60 family ds39762a-page 212 advance information ? 2006 microchip technology inc. register 18-2: econ2: ethernet control register 2 r/w-1 r/w-0 (1) r/w-0 u-0 u-0 u-0 u-0 u-0 autoinc pktdec ethen ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 autoinc: automatic buffer pointer increment enable bit 1 = automatically increment erdpt or ewrpt on reading from or writing to edata 0 = do not automatically change erdpt and ewrpt after edata is accessed bit 6 pktdec: packet decrement bit 1 = decrement the epktcnt register by one 0 = leave epktcnt unchanged bit 5 ethen: ethernet module enable bit 1 = ethernet module enabled 0 = ethernet module disabled bit 4-0 unimplemented: read as ? 0 ? note 1: this bit is automatically cleared once it is set. register 18-3: estat: ethernet status register u-0 r/c-0 u-0 r/c-0 u-0 r-0 r/c-0 r-0 ?bufer ?latecol ? rxbusy txabrt phyrdy bit 7 bit 0 legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 bufer: ethernet buffer error status bit 1 = an ethernet read or write has generated a buffer error (overrun or underrun) 0 = no buffer error has occurred bit 5 unimplemented: read as ? 0 ? bit 4 latecol: late collision error bit 1 = a collision occurred after 64 bytes had been transmitted 0 = no collisions after 64 bytes have occurred bit 3 unimplemented: read as ? 0 ? bit 2 rxbusy: receive busy bit 1 = receive logic is receiving a data packet 0 = receive logic is idle bit 1 txabrt: transmit abort error bit 1 = the transmit request was aborted 0 = no transmit abort error bit 0 phyrdy: ethernet phy clock ready bit 1 = ethernet phy ost has expired; phy is ready 0 = ethernet phy ost is still counting; phy is not ready ? 2006 microchip technology inc. advance information ds39762a-page 213 pic18f97j60 family 18.2.4 mac and mii registers these sfrs are used to control the operations of the mac and, through the miim, the phy. the mac and mii registers occupy data addresses e80h-e85h, e8ah, and ea0h through eb9h. although mac and mii registers appear in the general memory map of the microcontroller, these registers are embedded inside the mac module. host interface logic translates the microcontroller data/address bus data to be able to access these registers. the host interface logic imposes restrictions on how firmware is able to access the mac and mii sfrs. see the following notes. the three macon registers control specific mac oper- ations and packet configuration operations. they are shown in register 18-4 through register 18-6. the mii registers are used to control the miim interface and serves as the communication channel with the phy registers. they are shown in register 18-7, register 18-8 and register 18-9. note 1: the mac and mii sfrs can only be accessed when the ethernet module is enabled, ethen (econ2<5>) = 1 ). 2: back to back accesses of mac or mii registers are not supported. between any instruction which addresses a mac or mii register, at least one nop or other instruction must be executed. register 18-4: macon1: mac control register 1 u-0 u-0 u-0 r-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? r txpaus rxpaus passall marxen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4 reserved: maintain as ? 0 ? bit 3 txpaus: pause control frame transmission enable bit 1 = allow the mac to transmit pause control frames (needed for flow control in full duplex) 0 = disallow pause frame transmissions bit 2 rxpaus: pause control frame reception enable bit 1 = inhibit transmissions when pause control frames are received (normal operation) 0 = ignore pause control frames which are received bit 1 passall: pass all received frames enable bit 1 = control frames received by the mac will be written into the receive buffer if not filtered out 0 = control frames will be discarded after being processed by the mac (normal operation) bit 0 marxen: mac receive enable bit 1 = enable packets to be received by the mac 0 = disable packet reception pic18f97j60 family ds39762a-page 214 advance information ? 2006 microchip technology inc. register 18-5: macon3: mac control register 3 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 padcfg2 padcfg1 padcfg0 txcrcen phdren hfrmen frmlnen fuldpx bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 padcfg2:padcfg0: automatic pad and crc configuration bits 111 = all short frames will be zero padded to 64 bytes and a valid crc will then be appended 110 = no automatic padding of short frames 101 = mac will automatically detect vlan protocol frames which have a 8100h type field and auto- matically pad to 64 bytes. if the frame is not a vlan frame, it will be padded to 60 bytes. after padding, a valid crc will be appended. 100 = no automatic padding of short frames 011 = all short frames will be zero padded to 64 bytes and a valid crc will then be appended 010 = no automatic padding of short frames 001 = all short frames will be zero padded to 60 bytes and a valid crc will then be appended 000 = no automatic padding of short frames bit 4 txcrcen: transmit crc enable bit 1 = mac will apend a valid crc to all frames transmitted regardless of padcfg. txcrcen must be set if padcfg specifies that a valid crc will be appended. 0 = mac will not append a crc. the last 4 bytes will be checked and if it is an invalid crc, it will be reported in the transmit status vector. bit 3 phdren: proprietary header enable bit 1 = frames presented to the mac contain a 4-byte proprietary header which will not be used when calculating the crc 0 = no proprietary header is present. the crc will cover all data (normal operation). bit 2 hfrmen: huge frame enable bit 1 = frames of any size will be allowed to be transmitted and receieved 0 = frames bigger than mamxfl will be aborted when transmitted or received bit 1 frmlnen: frame length checking enable bit 1 = the type/length field of transmitted and received frames will be checked. if it represents a length, the frame size will be compared and mismatches will be reported in the transmit/receive status vector. 0 = frame lengths will not be compared with the type/length field bit 0 fuldpx: mac full-duplex enable bit 1 = mac will operate in full-duplex mode. pdpxmd bit must also be set. 0 = mac will operate in half-duplex mode. pdpxmd bit must also be clear. ? 2006 microchip technology inc. advance information ds39762a-page 215 pic18f97j60 family register 18-6: macon4: mac control register 4 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r-0 r-0 ? defer bpen nobkoff ? ?rr bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 defer: defer transmission enable bit (applies to half duplex only) 1 = when the medium is occupied, the mac will wait indefinitely for it to become free when attempting to transmit (use this setting for 802.3 compliance) 0 = when the medium is occupied, the mac will abort the transmission after the excessive deferral limit is reached bit 5 bpen: no backoff during backpressure enable bit (applies to half duplex only) 1 = after incidentally causing a collision during backpressure, the mac will immediately begin retransmitting 0 = after incidentally causing a collision during backpressure, the mac will delay using the binary exponential backoff algorithm before attempting to retransmit (normal operation) bit 4 nobkoff: no backoff enable bit (applies to half duplex only) 1 = after any collision, the mac will immediately begin retransmitting 0 = after any collision, the mac will delay using the binary exponential backoff algorithm before attempting to retransmit (normal operation) bit 3-2 unimplemented: read as ? 0 ? bit 1-0 reserved: maintain as ? 0 ? register 18-7: micon: mii control register r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 rstmii ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rstmii: mii management module reset bit 1 = mii management module held in reset 0 = normal operation bit 6-0 unimplemented: read as ? 0 ? pic18f97j60 family ds39762a-page 216 advance information ? 2006 microchip technology inc. register 18-8: micmd: mii command register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 ? ? ? ? ? ? miiscan miird bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-2 unimplemented: read as ? 0 ? bit 1 miiscan: mii scan enable bit 1 = phy register at miregadr is continuously read and the data is placed in mird 0 = no mii management scan operation is in progress bit 0 miird: mii read enable bit 1 = phy register at miregadr is read once and the data is placed in mird 0 = no mii management read operation is in progress register 18-9: mistat: mii status register u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ? ? ? ? r nvalid scan busy bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented: read as ? 0 ? bit 3 reserved: maintain as ? 0 ? 1 = the link partner is not present or the ethernet cable is not attached 0 = link has not failed bit 2 nvalid: mii management read data not valid bit 1 = the contents of mird are not valid yet 0 = the mii management read cycle has completed and mird has been updated bit 1 scan: mii management scan operation bit 1 = mii management scan operation is in progress 0 = no mii management scan operation is in progress bit 0 busy: mii management busy bit 1 = a phy register is currently being read or written to 0 = the mii management interface is idle ? 2006 microchip technology inc. advance information ds39762a-page 217 pic18f97j60 family 18.2.5 phy registers the phy registers provide configuration and control of the phy module, as well as status information about its operation. all phy registers are 16 bits in width. there are a total of 32 phy addresses; however, only 9 locations are implemented. writes to unimplemented locations are ignored and any attempts to read these locations will return ? 0 ?. all reserved locations should be written as ? 0 ?; their contents should be ignored when read. the implemented phy registers are listed in table 18-2. the main phy control registers are described in register 18-10 through register 18-14. the other phy control and status registers are described later in this chapter. thy phy registers are only accessible through the mii management interface. they are not available to be read or written to until the phy start-up timer has expired and the phyrdy bit (estat<0>) is set. 18.2.5.1 phstat registers the phstat1 and phstat2 registers contain read-only bits that show the current status of the phy module?s operations, particularly the conditions of the communications link to the rest of the network. the phstat1 register (register 18-11) contains the llstat bit; it clears and latches low if the physical layer link has gone down since the last read of the register. periodic polling by the host controller can be used to determine exactly when the link fails. it may be particularly useful if the link change interrupt is not used. the phstat1 register also contains a jabber status bit. an ethernet controller is said to be ?jabbering? if it con- tinuously transmits data without stopping and allowing other nodes to share the medium. generally, the jabber condition indicates that the local controller may be grossly violating the maximum packet size defined by the ieee specification. this bit latches high to indicate that a jabber condition has occurred since the last read of the register. the phstat2 register (register 18-13) contains status bits which report if the phy module is linked to the network and whether or not it is transmitting or receiving. 18.2.5.2 phid1 and phid2 registers the phid1 and phid2 registers are read-only registers. they hold constant data that help identify the ethernet controller and may be useful for debugging purposes. this includes: ? the part number of the phy module (ppn5:ppn0) ? the revision level of the phy module (prev3:prev0); and ? the phy identifier, as part of microchip?s corporate organizationally unique identifier, oui (oui3:oui24) the phy part number and revision are part of phid2. the upper two bytes of the phy identifier are located in phid1, with the remainder in phid2. the exact locations within registers are shown in table 18-2. revision information is also stored in erevid. this is a read-only control register which contains a 5-bit identifier for the specific silicon revision level of the device. 18.2.5.3 accessing phy registers as already mentioned, the phy registers exist in a different memory space and are not directly accessible by the microcontroller. instead, they are addressed through a special set of mii registers in the ethernet sfr bank, that implement a media independent interface management (miim). access is similar to that of the ethernet buffer, but uses separate read and write buffers (mirdh:mirdl and miwrh:miwrl) and a 5-bit address register (miregadr). in addition, the micmd and mistat registers are used to control read and write operations. to read from a phy register: 1. write the address of the phy register to be read from the miregadr register. 2. set the miird bit (micmd<0>). the read operation begins and the busy bit (mistat<0>) is set. 3. wait 10.24 s, then poll the busy bit to be certain that the operation is complete. when the mac has obtained the register contents, the busy bit will clear itself. while busy is set, the user application should not start any miiscan operations or write to the miwrh register. 4. clear the miird bit. 5. read the entire 16 bits of the phy register from the mirdl and mirdh registers. pic18f97j60 family ds39762a-page 218 advance information ? 2006 microchip technology inc. to write to a phy register: 1. write the address of the phy register to be written to the miregadr register. 2. write the lower 8 bits of data to write into the miwrl register. 3. write the upper 8 bits of data to write into the miwrh register. writing to this register auto- matically begins the mii transaction, so it must be written to after miwrl. the busy bit is set automatically. the phy register is written after the mii operation completes, which takes 10.24 s. when the write operation has completed, the busy bit will clear itself. the application should not start any mii scan or read operations while busy. when a phy register is written to, the entire 16 bits is written at once; selective bit writes are not imple- mented. if it is necessary to reprogram only select bits in the register, the controller must first read the phy register, modify the resulting data and then write the data back to the phy register. the mac can also be configured to perform automatic back-to-back read operations on a phy register. to perform this scan operation: 1. write the address of the phy register to be scanned into the miregadr register. 2. set the miiscan bit (micmd<1>). the scan operation begins and the busy bit is set. after miiscan is set, the nvalid (mistat<2>), scan and busy bits are also set. the first read operation will complete after 10.24 s. subsequent reads will be done and the mirdl and mirdh registers will be con- tinuously updated automatically at the same interval until the operation is cancelled. the nvalid bit may be polled to determine when the first read operation is complete. there is no status information which can be used to determine when the mird registers are updated. since only one mii register can be read at a time, it must not be assumed that the values of mirdl and mirdh were read from the phy at exactly the same time. in scan mode, the values of mirdh and mirdl are not valid until nvalid has cleared. nvalid is cleared automatically once the first read sequence is complete. miiscan should remain set as long as the scan operation is desired. the busy and scan bits are automatically cleared after miiscan is set to ? 0 ? and the last read sequence is completed. miregadr should not be updated while miiscan is set. starting new phy operations, such as a read operation or writing to the miwrh register, must not be done while a scan is underway. the operation can be cancelled by clearing the miiscan bit and then polling the busy bit. new operations may be started after the busy bit is cleared. ? 2006 microchip technology inc. advance information ds39762a-page 219 pic18f97j60 family table 18-2: pic18f97j60 family phy register summary addr name bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values 00h phcon1 prst ploopbk ? ?ppwrsv r ?pdpxmdr ? ? ? ? ? ? ? 00-- 00-0 0--- ---- 01h phstat1 ? ? ? phfdpx phhdpx ? ? ? ? ? ? ? ? llstat jbstat ? ---1 1--- ---- -00- 02h phid1 phy identifier (oui3:oui18) = 0083h 0000 0000 1000 0011 03h phid2 phy identifier (oui19:oui24) = 000101 phy p/n (ppn5:ppn0) = 00h phy revision (prev3:prev0) = 00h 0001 0100 0000 0000 10h phcon2 ? frclnk txdis r r jabber r hdldis r r r r r r r r -000 0000 0000 0000 11h phstat2 ? ? txstat rxstat colstat lstat dpxstat (1) ? ? ?plrity ? ? ? ? ? --00 00x- --0- ---- 12h phie r r r r r r r r r r r plnkie r r pgeie r xxxx xxxx xx00 xx00 13h phir r r r r r r r r r r r plnkif r pgif r r xxxx xxxx xx00 00x0 14h phlcon r r r r lacfg3:lacfg0 lbcfg3:lbcfg0 lfrq1:lfrq0 strch r 0011 0100 0010 001x legend: x = unknown, u = unchanged, - = unimplemented, read as ? 0 ?, r = reserved, do not modify. shaded cells are unimplemented, read as ? 0 ?. note 1: reset values of the duplex mode/status bit depends on the connection of the led to the ledb pin (see section 18.1.2 ?led configuration? for additional details). pic18f97j60 family ds39762a-page 220 advance information ? 2006 microchip technology inc. register 18-10: phcon1: phy control register 1 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 u-0 r/w-0 prst ploopbk ? ? ppwrsv r ? pdpxmd bit 15 bit 8 r/w-0 u-0 u-0 u-0 u-0 u-0 u-0 u-0 r ? ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 prst: phy software reset bit 1 = phy is processing a software reset (automatically resets to ? 0 ? when done) 0 = normal operation bit 14 ploopbk: phy loopback bit 1 = all data transmitted will be returned to the mac. the twisted-pair interface will be disabled. 0 = normal operation bit 13-12 unimplemented: read as ? 0 ? bit 11 ppwrsv: phy power-down bit 1 = phy is shut down 0 = normal operation bit 10 reserved: maintain as ? 0 ? bit 9 unimplemented: read as ? 0 ? bit 8 pdpxmd: phy duplex mode bit 1 = phy operates in full-duplex mode 0 = phy operates in half-duplex mode bit 7 reserved: maintain as ? 0 ? bit 6-0 unimplemented: read as ? 0 ? ? 2006 microchip technology inc. advance information ds39762a-page 221 pic18f97j60 family register 18-11: phstat1: physical layer status register 1 u-0 u-0 u-0 r-1 r-1 u-0 u-0 u-0 ? ? ? phfdpx phhdpx ? ? ? bit 15 bit 8 u-0 u-0 u-0 u-0 u-0 r/ll-0 r/lh-0 u-0 ? ? ? ? ? llstat jbstat ? bit 7 bit 0 legend: ?1? = bit is set r = read-only bit ?0? = bit is cleared u = unimplemented bit, read as ?0? -n = value at por r/l = read-only latch bit ll = bit latches low lh = bit latches high bit 15-13 unimplemented: read as ? 0 ? bit 12 phfdpx: phy full-duplex capable bit 1 = phy is capable of operating at 10 mbps in full-duplex mode (this bit is always set) bit 11 phhdpx: phy half-duplex capable bit 1 = phy is capable of operating at 10 mbps in half-duplex mode (this bit is always set) bit 10-3 unimplemented: read as ? 0 ? bit 2 llstat: phy latching link status bit 1 = link is up and has been up continously since phstat1 was last read 0 = link is down or was down for a period since phstat1 was last read bit 1 jbstat: phy latching jabber status bit 1 = phy has detected a transmission meeting the jabber criteria since phstat1 was last read 0 = phy has not detected any jabbering transmissions since phstat1 was last read bit 0 unimplemented: read as ? 0 ? pic18f97j60 family ds39762a-page 222 advance information ? 2006 microchip technology inc. register 18-12: phcon2: phy control register 2 u-0 r/w-0 r/w-0 r/w-x r/w-x r/w-0 r/w-0 r/w-0 ? frclnk txdis r r jabber r hdldis bit 15 bit 8 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x rrrrrrrr bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15 unimplemented: read as ? 0 ? bit 14 frclnk: phy force linkup bit 1 = force linkup even when no link partner is detected 0 = normal operation bit 13 txdis: twisted-pair transmitter disable bit 1 = disable twisted-pair transmitter 0 = normal operation bit 12-11 reserved: write as ? 0 ? bit 10 jabber: jabber correction disable bit 1 = disable jabber correction 0 = normal operation bit 9 reserved: write as ? 0 ? bit 8 hdldis: phy half-duplex loopback disable bit when phcon1 <8> = 1 or phcon1 <14> = 1 : this bit is ignored. when phcon1<8> = 0 a nd phcon1 <14> = 0 : 1 = transmitted data will only be sent out on the twisted-pair interface 0 = transmitted data will be looped back to the mac and sent out on the twisted-pair interface bit 7-0 reserved: write as ? 0 ? ? 2006 microchip technology inc. advance information ds39762a-page 223 pic18f97j60 family register 18-13: phstat2: physical layer status register 2 u-0 u-0 r-0 r-0 r-0 r-0 r-x u-0 ? ? txstat rxstat colstat lstat dpxstat (1) ? bit 15 bit 8 u-0 u-0 r-0 u-0 u-0 u-0 u-0 u-0 ? ?plrity ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 unimplemented: read as ? 0 ? bit 13 txstat: phy transmit status bit 1 = phy is transmitting data 0 = phy is not transmitting data bit 12 rxstat: phy receive status bit 1 = phy is receiving data 0 = phy is not receiving data bit 11 colstat: phy collision status bit 1 = a collision is occuring 0 = a collision is not occuring bit 10 lstat: phy link status bit (non-latching) 1 =link is up 0 =link is down bit 9 dpxstat: phy duplex status bit (1) 1 = phy is configured for full-duplex operation (phcon1<8> is set) 0 = phy is configured for half-duplex operation (phcon1<8> is clear) bit 8-6 unimplemented: read as ? 0 ? bit 5 plrity: polarity status bit 1 = the polarity of the signal on tpin+/tpin- is reversed 0 = the polarity of the signal on tpin+/tpin- is correct bit 4-0 unimplemented: read as ? 0 ? note 1: reset values of the duplex mode/status bit depends on the connection of the led to the ledb pin (see section 18.1.2 ?led configuration? for additional details). pic18f97j60 family ds39762a-page 224 advance information ? 2006 microchip technology inc. register 18-14: phlcon: phy module led control register r/w-0 r/w-0 r/w-1 r/w-1 r/w-0 r/w-1 r/w-0 r/w-0 r r r r lacfg3 lacfg2 lacfg1 lacfg0 bit 15 bit 8 r/w-0 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-1 r/w-x lbcfg3 lbcfg2 lbcfg1 lbcfg0 lfrq1 lfrq0 strch r bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-14 reserved: write as ? 0 ? bit 13-12 reserved: write as ? 1 ? bit 11-8 lacfg3:lacfg0: leda configuration bits 0000 = reserved 0001 = display transmit activity (stretchable) 0010 = display receive activity (stretchable) 0011 = display collision activity (stretchable) 0100 = display link status 0101 = display duplex status 0110 = reserved 0111 = display transmit and receive activity (stretchable) 1000 = on 1001 = off 1010 = blink fast 1011 = blink slow 1100 = display link status and receive activity (always stretched) 1101 = display link status and transmit/receive activity (always stretched) 1110 = display duplex status and collision activity (always stretched) 1111 = reserved bit 7-4 lbcfg3:lbcfg0: ledb configuration bits 0000 = reserved 0001 = display transmit activity (stretchable) 0010 = display receive activity (stretchable) 0011 = display collision activity (stretchable) 0100 = display link status 0101 = display duplex status 0110 = reserved 0111 = display transmit and receive activity (stretchable) 1000 = on 1001 = off 1010 = blink fast 1011 = blink slow 1100 = display link status and receive activity (always stretched) 1101 = display link status and transmit/receive activity (always stretched) 1110 = display duplex status and collision activity (always stretched) 1111 = reserved bit 3-2 lfrq1:lfrq0: led pulse stretch time configuration bits (see table 18-1) 11 = reserved 10 = stretch led events by t lstrch 01 = stretch led events by t mstrch 00 = stretch led events by t nstrch bit 1 strch: led pulse stretching enable bit 1 = stretchable led events will cause lengthened led pulses based on lfrq1:lfrq0 configuration 0 = stretchable led events will only be displayed while they are occurring bit 0 reserved: do not modify ? 2006 microchip technology inc. advance information ds39762a-page 225 pic18f97j60 family 18.3 ethernet interrupts the ethernet module can generate multiple interrupt conditions. to accommodate all of these sources, the module has its own interrupt logic structure, similar to that of the microcontroller. separate sets of registers are used to enable and flag different interrupt conditions. the eie register contains the individual interrupt enable bits for each source, while the eir register con- tains the corresponding interrupt flag bits. when an interrupt occurs, the interrupt flag is set. if the interrupt is enabled in the eie register, and the corresponding ethie global interrupt enable bit is set, the micro- controller?s master ethernet interrupt flag (ethif) is set, as appropriate (see figure 18-5). 18.3.1 control interrupt (ethie) the four registers associated with the control interrupts are shown in register 18-15 through register 18-18. figure 18-5: ethernet module interrupt logic note: except for the linkif interrupt flag, interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the associ- ated global enable bit. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. this feature allows for software polling. pktif pktie dmaif dmaie linkie txif txie set ethif ethie txerif txerie rxerif rxerie linkif pgif pgeie plnkif plnkie pic18f97j60 family ds39762a-page 226 advance information ? 2006 microchip technology inc. register 18-15: eie: ethernet interrupt enable register u-0 r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 ? pktie dmaie linkie txie ? txerie rxerie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 pktie: receive packet pending interrupt enable bit 1 = enable receive packet pending interrupt 0 = disable receive packet pending interrupt bit 5 dmaie: dma interrupt enable bit 1 = enable dma interrupt 0 = disable dma interrupt bit 4 linkie: link status change interrupt enable bit 1 = enable link change interrupt from the phy 0 = disable link change interrupt bit 3 txie: transmit enable bit 1 = enable transmit interrupt 0 = disable transmit interrupt bit 2 unimplemented: read as ? 0 ? bit 1 txerie: transmit error interrupt enable bit 1 = enable transmit error interrupt 0 = disable transmit error interrupt bit 0 rxerie: receive error interrupt enable bit 1 = enable receive error interrupt 0 = disable receive error interrupt ? 2006 microchip technology inc. advance information ds39762a-page 227 pic18f97j60 family register 18-16: eir: ethernet interrupt request (flag) register u-0 r-0 r/c-0 r-0 r/c-0 u-0 r/c-0 r/c-0 ? pktif dmaif linkif txif ? txerif rxerif bit 7 bit 0 legend: r = readable bit c = clearable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6 pktif: receive packet pending interrupt flag bit 1 = receive buffer contains one or more unprocessed packets; cleared when pktdec is set 0 = receive buffer is empty bit 5 dmaif: dma interrupt flag bit 1 = dma copy or checksum calculation has completed 0 = no dma interrupt is pending bit 4 linkif: link change interrupt flag bit 1 = phy reports that the link status has changed; read phir register to clear 0 = link status has not changed bit 3 txif: transmit interrupt flag bit 1 = transmit request has ended 0 = no transmit interrupt is pending bit 2 unimplemented: read as ? 0 ? bit 1 txerif: transmit error interrupt flag bit 1 = a transmit error has occurred 0 = no transmit error has occurred bit 0 rxerif: receive error interrupt flag bit 1 = a packet was aborted because there is insufficient buffer space or the packet count is 255 0 = no receive error interrupt is pending pic18f97j60 family ds39762a-page 228 advance information ? 2006 microchip technology inc. register 18-17: phie: phy interrupt enable register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x rrrrrrrr bit 15 bit 8 r/w-x r/w-x r/w-0 r/w-0 r/w-x r/w-x r/w-0 r/w-0 rrrplnkierrpgeier bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 reserved: write as ? 0 ?, ignore on read bit 5 reserved: maintain as ? 0 ? bit 4 plnkie: phy link change interrupt enable bit 1 = phy link change interrupt is enabled 0 = phy link change interrupt is disabled bit 3-2 reserved: write as ? 0 ?, ignore on read bit 1 pgeie: phy global interrupt enable bit 1 = phy interrupts are enabled 0 = phy interrupts are disabled bit 0 reserved: maintain as ? 0 ? register 18-18: phir: phy interrupt request (flag) register r-x r-x r-x r-x r-x r-x r-x r-x rrrrrrrr bit 15 bit 8 r-x r-x r-0 r/sc-0 r-0 r/sc-0 r-x r-0 r r r plnkif r pgif r r bit 7 bit 0 legend: r = readable bit sc = self-clearing bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 15-6 reserved: do not modify bit 5 reserved: read as ? 0 ? bit 4 plnkif: phy link change interrupt flag bit 1 = phy link status has changed since phir was last read; resets to ? 0 ? when read 0 = phy link status has not changed since phir was last read bit 3 reserved: read as ? 0 ? bit 2 pgif: phy global interrupt flag bit 1 = one or more enabled phy interrupts have occurred since phir was last read; resets to ? 0 ? when read 0 = no phy interrupts have occurred bit 1 reserved: do not modify bit 0 reserved: read as ? 0 ? ? 2006 microchip technology inc. advance information ds39762a-page 229 pic18f97j60 family 18.3.1.1 receive error interrupt (rxerif) the receive error interrupt is used to indicate a receive buffer overflow condition. alternately, this interrupt may indicate that too many packets are in the receive buffer and more cannot be stored without overflowing the epktcnt register. when a packet is being received and the receive buffer runs completely out of space, or epktcnt is 255 and cannot be incremented, the packet being received will be aborted (permanently lost) and the rxerif bit will be set to ? 1 ?. once set, rxerif can only be cleared by firmware or by a reset condition. if the receive error interrupt and ethernet interrupt are enabled (both rxerie and ethie are set), an ethernet interrupt is generated. if the receive error interrupt is not enabled (either rxerie or ethie are cleared), the user appli- cation may poll the rxerif and take appropriate action. normally, upon the receive error condition, the applica- tion would process any packets pending from the receive buffer and then make additional room for future packets by advancing the erxrdpt registers (low byte first) and decrementing the epktcnt register. see section 18.5.3.3 ?freeing receive buffer space? for more information on processing packets. once processed, the application should clear the rxerif bit. 18.3.1.2 transmit error interrupt (txerif) the transmit error interrupt is used to indicate that a transmit abort has occurred. an abort can occur because of any of the following conditions: 1. excessive collisions occurred as defined by the retransmission maximum (retmax) bits in the maclcon1 register. 2. a late collision occurred as defined by the collision window (colwin) bits in the maclcon2 register. 3. a collision after transmitting 64 bytes occurred (latecol is set). 4. the transmission was unable to gain an oppor- tunity to transmit the packet because the medium was constantly occupied for too long. the deferral limit was reached and the defer bit (macon4<6>) was clear. 5. an attempt to transmit a packet larger than the maximum frame length defined by the mamxfl registers was made without setting the hfrmen bit (macon3<2>) or per-packet poverride and phugeen bits. upon any of these conditions, the txerif flag is set to ? 1 ?. once set, it can only be cleared by firmware or by a reset condition. if the transmit error interrupt is enabled (txerie and ethie are both set), an ethernet interrupt is generated. if the transmit error interrupt is not enabled (either txerie or ethie is cleared), the application may poll txerif and take appropriate action. once the interrupt is processed, the flag bit should be cleared. after a transmit abort, the txrts bit will be cleared, the txabrt bit (estat<1>) becomes set and the transmit status vector will be written at etxnd + 1. the mac will not automatically attempt to retransmit the packet. the application may wish to read the transmit status vector and latecol bit to determine the cause of the abort. after determining the problem and solution, the application should clear the latecol (if set) and txabrt bits so that future aborts can be detected accurately. in full-duplex mode, condition 5 is the only one that should cause this interrupt. collisions and other prob- lems related to sharing the network are not possible on full-duplex networks. the conditions which cause the transmit error interrupt meet the requirements of the transmit interrupt. as a result, when this interrupt occurs, txif will also be simultaneously set. 18.3.1.3 transmit interrupt (txif) the transmit interrupt is used to indicate that the requested packet transmission has ended (the txrts bit has transitioned from ? 1 ? to ? 0 ?). upon transmission completion, abort, or transmission cancellation by the application, the txif flag will be set to ? 1 ?. if the application did not clear the txrts bit, and the txabrt bit are not set, the packet was successfully transmitted. once txif is set, it can only be cleared in software or by a reset condition. if the transmit interrupt is enabled (txie and ethie are both set), an interrupt is generated. if the transmit interrupt is not enabled (either txie or ethie is cleared), the application may poll the txif bit and take appropriate action. pic18f97j60 family ds39762a-page 230 advance information ? 2006 microchip technology inc. 18.3.1.4 link change interrupt (linkif) the linkif indicates that the link status has changed. the actual current link status can be obtained from the llstat (phstat1<2>) or lstat (phstat2<10>) bits (see register 18-11 and register 18-13). unlike other interrupt sources, the link status change interrupt is created in the integrated phy module; additional steps must be taken to enable it. by reset default, linkif is never set for any reason. to receive it, both the plnkie and pgeie bits must be set. when the interrupt is enabled, the linkif bit will shadow the contents of the pgif bit. the phy only supports one interrupt, so the pgif bit will always be the same as the plnkif bit (when both phy enable bits are set). once linkif is set, it can only be cleared in software or by a reset. if the link change interrupt is enabled (linkie, plnkie, pgeie and ethie are all set), an interrupt is generated. if the link change interrupt is not enabled (linkie, plnkie, pgeie or ethie are cleared), the user application may poll the plnkif flag and take appropriate action. the linkif bit is read-only. because reading phy registers requires a non-negligible period of time, the application may instead set plnkie and pgeie, then poll the linkif flag bit. performing an mii read on the phir register will clear the linkif, pgif and plnkif bits automatically and allow for future link status change interrupts. see section 18.2.5 ?phy registers? for information on accessing the phy registers. 18.3.1.5 dma interrupt (dmaif) the dma interrupt indicates that the dma module has completed its memory copy or checksum calculation (the dmast bit has transitioned from ? 1 ? to ? 0 ?). addi- tionally, this interrupt will be caused if the application cancels a dma operation by manually clearing the dmast bit. once set, dmaif can only be cleared by the firmware or by a reset condition. if the dma inter- rupt is enabled, an ethernet interrupt is generated. if the dma interrupt is not enabled, the user application may poll the dmaif flag status and take appropriate action. once processed, the flag bit should be cleared. 18.3.1.6 receive packet pending interrupt (pktif) the receive packet pending interrupt is used to indicate the presence of one or more data packets in the receive buffer and to provide a notification means for the arrival of new packets. when the receive buffer has at least one packet in it, the pktif flag bit is set. in other words, this interrupt flag will be set anytime the ethernet packet count register (epktcnt) is non-zero. when the receive packet pending interrupt is enabled (both pktie and intie are set), an ethernet interrupt is generated whenever a new packet is successfully received and written into the receive buffer. if the receive packet pending interrupt is not enabled (pktie or intie is cleared), the user application may poll the pktif bit and take appropriate action. the pktif bit can only be cleared indirectly in software, by decrementing the epktcnt register to ? 0 ?, or by a reset condition. see section 18.5.3 ?receiving pack- ets? for more information about clearing the epktcnt register. when the last data packet in the receive buffer is processed, epktcnt becomes zero and the pktif bit is automatically cleared. ? 2006 microchip technology inc. advance information ds39762a-page 231 pic18f97j60 family 18.4 module initialization before the ethernet module can be used to transmit and receive packets, certain device settings must be initialized. depending on the application, some config- uration options may need to be changed. normally, these tasks may be accomplished once after reset and do not need to be changed thereafter. 18.4.1 receive buffer before receiving any packets, the receive buffer must be initialized by setting the erxst and erxnd point- ers. all memory between and including the erxst and erxnd addresses will be dedicated to the receive hardware. it is recommended that the erxst pointers be programmed with an even address. applications expecting large amounts of data and frequent packet delivery may wish to allocate most of the memory as the receive buffer. applications that may need to save older packets, or have several packets ready for transmission, should allocate less memory. when programming the erxst or erxnd pointers, the erxwrpt pointer registers will automatically be updated with the value in erxst. the address in the erxwrpt will be used as the starting location when the receive hardware begins writing received data. for track- ing purposes, the erxrdpt registers should additionally be programmed with the same value. to program the erxrdpt registers, write to erxrdptl first, followed by erxrdpth. see section 18.5.3.3 ?freeing receive buffer space? for more information. 18.4.2 transmission buffer all memory which is not used by the receive buffer is considered to be transmission buffer. data which is to be transmitted should be written into any unused space. after a packet is transmitted, however, the hard- ware will write a 7-byte status vector into memory after the last byte in the packet. therefore, the application should leave at least 7 bytes between each packet and the beginning of the receive buffer. 18.4.3 receive filters the appropriate receive filters should be enabled or disabled by writing to the erxfcon register. see section 18.8 ?receive filters? for information on how to configure it. 18.4.4 waiting for the phy start-up timer if the initialization procedure is being executed immedi- ately after enabling the module (setting econ2<5> to ? 1 ?), the phyrdy bit should be polled to make certain that enough time (1 ms typical) has elapsed before proceeding to modify the phy registers. for more information on the phy start-up timer, see section 18.1.3.1 ?start-up timer? . 18.4.5 mac initialization settings several of the mac registers require configuration during initialization. this only needs to be done once during initialization; the order of programming is unimportant. 1. set the marxen bit (macon1<0>) to enable the mac to receive frames. if using full duplex, most applications should also set txpaus and rxpaus to allow ieee defined flow control to function. 2. configure the padcfg<2:0>, txcrcen and fuldpx bits in the macon3 register. most applications should enable automatic padding to at least 60 bytes and always append a valid crc. for convenience, many applications may wish to set the frmlnen bit as well to enable frame length status reporting. the fuldpx bit should be set if the application will be connected to a full-duplex configured remote node; otherwise it should be left clear. 3. configure the bits in macon4. for maintaining compliance with ieee 802.3, be certain to set the defer bit (macon4<6>). 4. program the mamxfl registers with the maxi- mum frame length to be permitted to be received or transmitted. normal network nodes are designed to handle packets that are 1518 bytes or less. 5. configure the back-to-back inter-packet gap register, mabbipg. most applications will program this register with 15h when full-duplex mode is used and 12h when half-duplex mode is used. refer to register 18-19 for a more detailed description of configuring the inter-packet gap. 6. configure the non back-to-back inter-packet gap low byte register, maipgl. most applications will program this register with 12h. 7. if half duplex is used, the non back-to-back inter-packet gap high byte register, maipgh, should be programmed. most applications will program this register to 0ch. 8. if half-duplex mode is used, program the retransmission maximum and collision win- dow registers, maclcon1 and maclcon2. most applications will not need to change the default reset values. if the network is spread over exceptionally long cables, the default value of maclcon2 may need to be increased. 9. program the local mac address into the maadr1:maadr6 registers. pic18f97j60 family ds39762a-page 232 advance information ? 2006 microchip technology inc. 18.4.6 phy initialization settings depending on the application, bits in three of the phy module?s registers may also require configuration. the pdpxmd bit (phcon1<8>) controls the phy half/full-duplex configuration. the application must program the bit properly, along with the fuldpx bit (macon3<0>). the hdldis bit (phcon2<8>) disables automatic loopback of the data. it should always be set. the phy register phlcon (register 18-14) controls the outputs of leda and ledb. if an application requires a led configuration other than the default, alter this register to match the new requirements. the settings for led operation are discussed in section 18.1.2 ?led configuration? . 18.4.7 disabling the ethernet module there may be circumstances during which the ethernet module is not needed for prolonged periods. for exam- ple, in situations where the application only needs to transmit or receive ethernet packets on the occurrence of a particular event. in these cases, the module can be selectively powered down. to selectively disable the module: 1. turn off packet reception by clearing the rxen bit. 2. wait for any in-progress packets to finish being received by polling the rxbusy bit (estat<2>). this bit should be clear before proceeding. 3. wait for any current transmissions to end by confirming that the txrts bit (econ1<3>) is clear. 4. clear the ethen bit. this makes all mac, mii and phy registers inaccessible, and also clears the phyrdy bit automatically. register 18-19: mabbipg: mac back-to-back inter-packet gap register u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? bbipg6 bbipg5 bbipg4 bbipg3 bbipg2 bbipg1 bbipg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-0 bbipg6:bbipg0: back-to-back inter-packet gap delay time bits when fuldpx (macon3<0>) = 1 : nibble time offset delay between the end of one transmission and the beginning of the next in a back-to-back sequence. the register value should be programmed to the desired period in nibble times minus 3. the recommended setting is 15h which represents the minimum ieee specified inter-packet gap (ipg) of 9.6 s. when fuldpx (macon3<0>) = 0 : nibble time offset delay between the end of one transmission and the beginning of the next in a back-to-back sequence. the register value should be programmed to the desired period in nibble times minus 6. the recommended setting is 12h which represents the minimum ieee specified inter-packet gap (ipg) of 9.6 s. ? 2006 microchip technology inc. advance information ds39762a-page 233 pic18f97j60 family 18.5 transmitting and receiving data the ethernet protocol (ieee standard 802.3) provides an extremely detailed description of the 10 mbps, frame-based serial communications system. before discussing the actual use of the ethernet module, a brief review of the structure of a typical ethernet data frame may be appropriate. it is assumed that users already have some familiarity with ieee 802.3. those requiring more information should refer to the official standard, or other ethernet reference texts, for a more comprehensive explanation. 18.5.1 packet format normal ieee 802.3 compliant ethernet frames are between 64 and 1518 bytes long. they are made up of five or six different fields: a destination mac address, a source mac address, a type/length field, data payload, an optional padding field and a cyclic redundancy check (crc). additionally, when transmitted on the ethernet medium, a 7-byte preamble field and start-of-frame delimiter byte are appended to the beginning of the ethernet packet. thus, traffic seen on the twisted-pair cabling will appear as shown in figure 18-6. 18.5.1.1 preamble/start-of-frame delimiter when transmitting and receiving data with the ethernet module, the preamble and start-of-frame delimiter bytes are automatically generated, or stripped from the packets, when they are transmitted or received. it can also automatically generate crc fields and padding as needed on transmission, and verify crc data on reception. the user application does not need to create or process these fields, or manually verify crc data. however, the padding and crc fields are written into the receive buffer when packets arrive, so they may be evaluated by the user application as needed. figure 18-6: ethernet packet format sa padding fcs (1) number field comments 6 46-1500 4 da destination address, such as multicast, broadcast or unicast source address packet payload frame check sequence ? crc type/length data of bytes 6 2 type of packet or the length of the packet (with optional padding) 7 preamble filtered out by the module sfd 1 start-of-frame delimiter (filtered out by the module) used in the calculation of the fcs note 1: the fcs is transmitted starting with bit 31 and ending with bit 0. pic18f97j60 family ds39762a-page 234 advance information ? 2006 microchip technology inc. 18.5.1.2 destination address the destination address field is a 6-byte field filled with the mac address of the device that the packet is directed to. if the least significant bit in the first byte of the mac address is set, the address is a multicast des- tination. for example, 01-00-00-00-f0-00 and 33-45-67-89-ab-cd are multicast addresses, while 00-00-00-00-f0-00 and 32-45-67-89-ab-cd are not. packets with multicast destination addresses are designed to arrive and be important to a selected group of ethernet nodes. if the destination address field is the reserved multicast address, ff-ff-ff-ff-ff-ff, the packet is a broadcast packet and it will be directed to everyone sharing the network. if the least significant bit in the first byte of the mac address is clear, the address is a unicast address and will be designed for usage by only the addressed node. the ethernet module incorporates receive filters which can be used to discard or accept packets with multicast, broadcast and/or unicast destination addresses. when transmitting packets, the application is responsible for writing the desired destination address into the transmit buffer. 18.5.1.3 source address the source address field is a 6-byte field filled with the mac address of the node which created the ethernet packet. users of the ethernet module must generate a unique mac address for each and every microcontroller used. mac addresses consist of two portions. the first three bytes are known as the organizationally unique identi- fier (oui). ouis are distributed by the ieee. the last three bytes are address bytes at the discretion of the company that purchased the oui. when transmitting packets, the assigned source mac address must be written into the transmit buffer by the application. the module will not automatically transmit the contents of the maadr registers which are used for the unicast receive filter. 18.5.1.4 type/length the type/length field is a 2-byte field which defines which protocol the following packet data belongs to. alternately, if the field is filled with the contents of 05dch (1500) or any smaller number, the field is considered a length field, and it specifies the amount of non-padding data which follows in the data field. users implementing proprietary networks may choose to treat this field as a length field, while applications implementing protocols such as the internet protocol (ip), or address resolution protocol (arp), should program this field with the appropriate type defined by the protocol?s specification when transmitting packets. 18.5.1.5 data the data field is a variable length field anywhere from 0 to 1500 bytes. larger data packets will violate ethernet standards and will be dropped by most ethernet nodes. the ethernet module, however, is capable of transmit- ting and receiving larger packets when the huge frame enable bit, hfrmen, is set (macon3<2> = 1 ). 18.5.1.6 padding the padding field is a variable length field added to meet ieee 802.3 specification requirements when small data payloads are used. the destination, source, type, data and padding of an ethernet packet must be no smaller than 60 bytes. adding the required 4-byte crc field, packets must be no smaller than 64 bytes. if the data field is less than 46 bytes long, a padding field is required. when transmitting packets, the ethernet module automatically generates zero padding if the padcfg2:padcfg0 bits (macon3<7:5>) are config- ured for this. otherwise, the user application will need to add any padding to the packet before transmitting it. the module will not prevent the transmission of undersized packets should the application command such an action. when receiving packets, the module automatically rejects packets which are less than 18 bytes. all pack- ets, 18 bytes and larger, will be subject to the standard receive filtering criteria and may be accepted as normal traffic. since the module only rejects packets smaller than 18 bytes, it is important that the firmware check the length of every received packet and reject packets which are smaller than 64 bytes to meet ieee 802.3 specification requirements. 18.5.1.7 crc the crc field is a 4-byte field which contains an indus- try standard, 32-bit crc, calculated with the data from the destination, source, type, data and padding fields. when receiving packets, the ethernet module will check the crc of each incoming packet. if the crcen bit is set, packets with invalid crcs will automatically be discarded. if crcen is clear and the packet meets all other receive filtering criteria, the packet will be written into the receive buffer and the application will be able to determine if the crc was valid by reading the receive status vector (see section 18.5.3 ?receiving packets? ). when transmitting packets, the module automatically generates a valid crc and transmits it if the padcfg2:padcfg0 bits are configured for this. other- wise, the user application must generate the crc and place it in the transmit buffer. given the complexity of calculating a crc, it is highly recommended to allow the module to automatically calculate and include the crc. ? 2006 microchip technology inc. advance information ds39762a-page 235 pic18f97j60 family 18.5.2 transmitting packets the ethernet module?s mac will automatically generate the preamble and start-of-frame delimiter fields when transmitting. additionally, the mac can generate any padding (if needed) and the crc if configured to do so. the application must generate and write all other frame fields into the buffer memory for transmission. in addition, the ethernet module requires a single per-packet control byte to precede the packet for trans- mission. the control byte is organized as shown in figure 18-7. before transmitting packets, the mac registers, which alter the transmission characteristics, should be initialized as documented in section 18.4 ?module initialization? . figure 18-7: format for per-packet control bytes ? ? ? ? phugeen ppadn pcrcen poverride bit 7 bit 0 bit 7-4 unused bit 3 phugeen: per-packet huge frame enable bit when poverride = 1 : 1 = the packet will be transmitted in whole 0 = the mac will transmit up to the number of bytes specified by mamxfl. if the packet is larger than mamxfl, it will be aborted after mamxfl is reached. when poverride = 0 : this bit is ignored. bit 2 ppadn: per-packet padding enable bit when poverride = 1 : 1 = the packet will be zero padded to 60 bytes if it is less than 60 bytes 0 = the packet will be transmitted without adding any padding bytes when poverride = 0 : this bit is ignored. bit 1 pcrcen: per-packet crc enable bit when poverride = 1 : 1 = a valid crc will be calculated and attached to the frame 0 = no crc will be appended. the last 4 bytes of the frame will be checked for validity as a crc. when poverride = 0 : this bit is ignored. bit 0 poverride: per-packet override bit 1 = the values of pcrcen, ppadn and phugeen will override the configuration defined by macon3 0 = the values in macon3 will be used to determine how the packet will be transmitted pic18f97j60 family ds39762a-page 236 advance information ? 2006 microchip technology inc. an example of how the entire assembled transmit packet looks in memory is shown in figure 18-8. to construct and transmit a packet in this fashion: 1. set the etxst pointers to an appropriate unused location in the buffer. this will be the location of the per-packet control byte. in the example, it would be 0120h. it is recommended that an even address be used for etxst. 2. sequentially, write the data for the per-packet control byte, the destination address, the source mac address, the type/length and the data payload to the ethernet buffer. 3. set the etxnd pointers to point to the last byte in the data payload. in the example, it would be programmed to 0156h. 4. clear the txif flag bit (eir<3>), and set the txie (eie<3>) and ethie bits to enable an interrupt when done (if desired). 5. start the transmission process by setting the txrts bit (econ1<3>). if a dma operation was in progress while the txrts bit was set, the module will wait until the dma operation is complete before attempting to transmit the packet. this possible delay is required because the dma and transmission engine share the same memory access port. similarly, if the dmast bit is set after txrts is already set, the dma will wait until the txrts bit becomes clear before doing anything. while the transmission is in progress, the etxst and etxnd pointers should not be modified. if it is necessary to cancel the transmission, clear the txrts bit. when the packet is finished transmitting, or was aborted due to an error/cancellation, several things occur: ? the txrts bit is cleared ? a 7-byte transmit status vector is written to the buffer at the location pointed to by etxnd + 1 ? the txif flag is set ? an interrupt will be generated (if enabled) ? the etxst and etxnd pointers will not be modified. to check if the packet was successfully transmitted, read the txabrt bit. if it has been set, poll the latecol bit in addition to the various fields in the transmit status vector to determine the cause. the transmit status vector is organized as shown in table 18-3. multi-byte fields are written in little-endian format. figure 18-8: sample transmit packet layout control tsv[7:0] tsv[15:8] address memory description 0120h 0121h 0122h 016ah 016bh 016ch 016dh 0eh phugeen, ppadn, destination address, 016eh start of the next packet tsv[23:16] tsv[31:24] data[1] data[2] tsv[39:32] tsv[47:40] tsv[55:48] 0159h 0157h 0158h 0156h data[m] data packet status vector status vector etxst = 0120h etxnd = 0156h type/length and data pcrcen and poverride written by the hardware source address, buffer pointers ? 2006 microchip technology inc. advance information ds39762a-page 237 pic18f97j60 family table 18-3: transmit status vectors bit field description 55-52 zero 0 51 transmit vlan tagged frame frame?s length/type field contained 8100h which is the vlan protocol identifier. 50 backpressure applied carrier sense method backpressure was previously applied. 49 transmit pause control frame the frame transmit ted was a control frame with a valid pause opcode. 48 transmit control frame the frame transmitted was a control frame. 47-32 total bytes transmitted on wire total bytes transmitted on the wire for the current packet, including all bytes from collided attempts. 31 transmit underrun reserved. this bit will always be ? 0 ?. 30 transmit giant byte count for frame was greater than mamxfl. 29 transmit late collision collision occurred beyond the collision window (maclcon2). 28 transmit excessive collision packet was aborted after the number of collisions exceeded the retransmission maximum (maclcon1). 27 transmit excessive defer packet was deferred in excess of 24,287 bit times (2.4287ms). 26 transmit packet defer packet was deferred for at least one attempt but less than an excessive defer. 25 transmit broadcast packet?s destination address was a broadcast address. 24 transmit multicast packet?s destination address was a multicast address. 23 transmit done transmission of the packet was completed. 22 transmit length out of range indicates that frame type/length field was larger than 1500 bytes (type field). 21 transmit length check error indicates that frame length field value in the packet does not match the actual data byte length and is not a type field. macon3.frmlnen must be set to get this error. 20 transmit crc error the attached crc in the packet did not match the internally generated crc. 19-16 transmit collision count number of collisions the current packet incurred during transmission attempts. it applies to successfully transmitted packets and as such, will not show the possible maximum count of 16 collisions. 15-0 transmit byte count total bytes in frame not counting collided bytes. pic18f97j60 family ds39762a-page 238 advance information ? 2006 microchip technology inc. 18.5.3 receiving packets assuming that the receive buffer has been initialized, the mac has been properly configured and the receive filters have been configured, the application should perform these steps to receive ethernet packets: 1. set the pktie and ethie bits to generate an ethernet interrupt whenever a packet is received (if desired). 2. clear the rxerif flag and set both rxerie and ethie to generate an interrupt whenever a packet is dropped due to insufficient buffer space (if desired). 3. enable reception by setting the rxen bit (econ1<2>). after setting rxen, the duplex mode and the receive buffer start and end pointers should not be modified. additionally, to prevent unexpected packets from arriv- ing, it is recommended that rxen be cleared before altering the receive filter configuration (erxfcon) and mac address. after reception is enabled, packets which are not filtered out will be written into the circular receive buffer. any packet which does not meet the necessary filter criteria will be discarded and the application will not have any means of identifying that a packet was thrown away. when a packet is accepted and completely written into the buffer: ? the epktcnt register is incremented, ? the pktif bit is set, ? an interrupt is generated (if enabled), and ? the hardware write pointers, erxwrpt, are automatically advanced. 18.5.3.1 receive packet layout figure 18-9 shows the layout of a received packet. the packets are preceded by a 6-byte header which contains a next packet pointer, in addition to a receive status vector, which contains receive statistics, including the packet?s size. this receive status header is shown in table 18-4. if the last byte in the packet ends on an odd value address, the hardware will automatically add a padding byte when advancing the hardware write pointer. as such, all packets will start on an even boundary. figure 18-9: sample receive packet layout low byte high byte rsv[7:0] rsv[15:8] data[m-3] data[m-2] data[m-1] data[m] address memory description 1020h 1021h 1022h 1023h 106ah 106bh 106ch 1059h 10h 6eh next packet pointer packet data: destination address, receive status vector crc[31:24] crc[23:16] crc[15:8] crc[7:0] 106eh start of the next packet rsv[23:16] rsv[30:24] 1024h 1025h data[1] 1026h data[2] 1027h status[7:0] status[15:8] status[23:16] status[31:24] 106dh byte skipped to ensure even buffer address 101fh end of the previous packet packet n ? 1 source address, type/length, data, padding, crc packet n packet n + 1 ? 2006 microchip technology inc. advance information ds39762a-page 239 pic18f97j60 family table 18-4: receive status vectors 18.5.3.2 reading received packets to process the packet, an application will normally start reading from the beginning of the next packet pointer. the application will save the next packet pointer, any necessary bytes from the receive status vector, and then proceed to read the actual packet contents. if the autoinc bit is set, it will be able to sequentially read the entire packet without ever modifying the erdpt registers. the read pointer would automatically wrap at the end of the circular receive buffer to the beginning. in the event that the application needed to randomly access the packet, it would be necessary to manually calculate the proper erdpt, taking care to not exceed the end of the receive buffer, if the packet spans the erxnd to erxst buffer boundary. in other words, given the packet start address and a desired offset, the application should follow the logic shown in equation 18-1. equation 18-1: random access address calculation bit field description 31 zero ? 0 ? 30 receive vlan type detected current frame was recognized as a vlan tagged frame. 29 receive unknown opcode current frame was recognized as a control frame but it contained an unknown opcode. 28 receive pause control frame current frame was recognized as a control frame containing a valid pause frame opcode and a valid destination address. 27 receive control frame current frame was recognized as a control frame for having a valid type/length designating it as a control frame. 26 dribble nibble indicates that after the end of this packet, an additional 1 to 7 bits were received. the extra bits were thrown away. 25 receive broadcast packet indicates packet received had a valid broadcast address. 24 receive multicast packet indicates packet received had a valid multicast address. 23 received ok indicates that the packet had a valid crc and no symbol errors. 22 length out of range indicates that frame type/length field was larger than 1500 bytes (type field). 21 length check error indicates that frame length field value in the packet does not match the actual data byte length and specifies a valid length. 20 crc error indicates that frame crc field value does not match the crc calculated by the mac. 19 reserved 18 carrier event previously seen indicates that at some time since the last receive, a carrier event was detected. the carrier event is not associated with this packet. a carrier event is activity on the receive channel that does not result in a packet receive attempt being made. 17 reserved 16 long event/drop event indicates a packet over 50,000 bit times occurred or that a packet was dropped since the last receive. 15-0 received byte count indicates length of the received frame. this includes the destination address, source address, type/length, data, padding and crc fields. this field is stored in little-endian format. if packet start address + offset > erxnd, then erdpt = packet start address + offset ? (erxnd ? erxst + 1) else erdpt = packet start address + offset pic18f97j60 family ds39762a-page 240 advance information ? 2006 microchip technology inc. 18.5.3.3 freeing receive buffer space after the user application has processed a packet (or part of the packet) and needs to free the occupied buffer space used by the processed data, it must advance the receive buffer read pointers, erxrdpt. the module will always write up to, but not include, the memory pointed to by the receive buffer read point- ers. if an overwrite of the receive buffer read pointer locations occurs, the packet in progress will be aborted, the rxerif flag will be set and an interrupt will be gen- erated (if enabled). in this manner, the hardware will never overwrite unprocessed packets. normally, the erxrdpt will be advanced to the value pointed to by the next packet pointer which precedes the receive status vector for the current packet. following such a procedure will not require any pointer calculations to account for wrapping at the end of the circular receive buffer. the receive buffer read pointer low byte (erxrdptl register) is internally buffered to prevent the pointer from moving when only one byte is updated. to move erxrdpt, the application must write to erxrdptl first. the write will update the internal buffer but will not affect the register. when the applica- tion writes to erxrdpth, the internally buffered low byte will be loaded into the erxrdptl register at the same time. the erxrdpt bytes can be read in any order. when they are read, the actual value of the registers will be returned. as a result, the buffered low byte is not readable. in addition to advancing the receive buffer read pointers, after each packet is fully processed, the user application must set the pktdec bit (econ2<6>). this causes the epktcnt register to decrement by 1. after decrementing, if epktcnt is ? 0 ?, the pktif flag bit will automatically be cleared. otherwise, it will remain set, indicating that additional packets are in the receive buffer and are waiting to be processed. attempts to decrement epktcnt below 0 are ignored. additionally, if the epktcnt register ever maximizes at 255, all new packets which are received will be aborted, even if buffer space is available. to indicate the error, the rxerif is set and an interrupt is generated (if enabled). to prevent this condition, the user application must properly decrement the counter whenever a packet is processed. because only one pointer is available to control buffer area ownership, the application must process packets in the order they are received. if a packet is to be saved and processed later, the application should copy the packet to an unused location in memory. this can be done efficiently using the integrated dma controller (see section 18.9 ?direct memory access controller? ). 18.5.3.4 receive buffer free space at any time the application needs to know how much receive buffer space is remaining, it should read the hardware write pointers (erxwrpt registers) and compare it with the erxrdpt registers. combined with the known size of the receive buffer, the free space can be derived. when reading the erxwrpt registers with the receive hardware enabled, special care must be taken to ensure the low and high bytes are read as a matching set. to be assured that a matching set is obtained: 1. read the epktcnt register and save its contents. 2. read erxwrptl and erxwrpth. 3. read the epktcnt register again. 4. compare the two packet counts. if they are not the same, go back to step 2. with the hardware write pointers obtained, the free space can be calculated as shown in example 18-2. the hardware prohibits moving the write pointers to the same value occupied by erxrdpt (except when the buffer pointers are being configured), so at least one byte will always go unused in the buffer. the equation 18-2 calculation reflects the lost byte. equation 18-2: receive buffer free space calculation note: the erxwrpt registers only update when a packet has been successfully received. if the application reads it just before another packet is to be successfully completed, the value returned could be stale and off by the maximum frame length permitted (mamxfln) plus 7. further- more, as the application reads one byte of erxwrpt, a new packet may arrive and update the pointers before the application has an opportunity to read the other byte of erxwrpt. if erxwrpt > erxrdpt, then free space = (erxnd ? erxst) ? (erxwrpt ? erxrdpt) else if erxwrpt=erxrdpt, then free space = (erxnd ? erxst) else free space = erxrdpt ? erxwrpt ? 1 ? 2006 microchip technology inc. advance information ds39762a-page 241 pic18f97j60 family table 18-5: summary of registers used for packet transmission table 18-6: summary of registers used for packet reception register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page eie ? pktie dmaie linkie txie ?txerie rxerie 63 eir ? pktif dmaif linkif txif ?txerif rxerif 63 estat ?bufer ?latecol ? rxbusy txabrt phyrdy 63 econ1 txrst rxrst dmast csumen txrts rxen ? ?60 etxstl transmit start register low byte (etxst<7:0>) 64 etxsth ? ? ? transmit start register high byte (etxst<12:8>) 64 etxndl transmit end register low byte (etxnd<7:0>) 64 etxndh ? ? ? transmit end register high byte (etxnd<12:8>) 64 macon1 ? ? ? r txpaus rxpaus passall marxen 65 macon3 padcfg2 padcfg1 padcfg0 txcrcen phdren hfrmen frmlnen fuldpx 65 macon4 ? defer bpen nobkoff ? ? r r65 mabbipg ? bbipg6 bbipg5 bbipg4 bbipg3 bbipg2 bbipg1 bbipg0 65 maipgl ? non back-to-back inter-packet gap register low byte (maipgl<6:0>) 65 maipgh ? non back-to-back inter-packet gap register high byte (maipgh<6:0>) 65 maclcon1 ? ? ? ? retransmission maximum register (retmax<3:0>) 64 maclcon2 ? ? collision window register (colwin<5:0>) 64 mamxfll maximum frame length register low byte (mamxfl<7:0>) 64 mamxflh maximum frame length register high byte (mamxfl<15:8>) 64 legend: ? = unimplemented, r = reserved bit. shaded cells are not used. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page eie ? pktie dmaie linkie txie ? txerie rxerie 63 eir ? pktif dmaif linkif txif ? txerif rxerif 63 estat ?bufer ? latecol ?rxbusy txabrt phyrdy 63 econ2 autoinc pktdec ethen ? ? ? ? ?63 econ1 txrst rxrst dmast csumen txrts rxen ? ?60 erxstl receive start register low byte (erxst<7:0>) 64 erxsth ? ? ? receive start register high byte (erxst<12:8>) 64 erxndl receive end register low byte (erxnd<7:0>) 64 erxndh ? ? ? receive end register high byte (erxnd<12:8>) 64 erxrdptl receive buffer read pointer low byte (erxrdpt<7:0>) 63 erxrdpth ? ? ? receive buffer read pointer high byte (erxrdpt<12:8>) 63 erxfcon ucen andor crcen pmen mpen hten mcen bcen 64 epktcnt ethernet packet count register 64 macon1 ? ? ? r txpaus rxpaus passal marxen 65 macon3 padcfg2 padcfg1 padcfg0 txcrcen phdren hfrmen frmlnen fuldpx 65 macon4 ? defer bpen nobkoff ? ? r r65 mamxfll maximum frame length register low byte (mamxfl<7:0>) 64 mamxflh maximum frame length register high byte (mamxfl<15:8>) 64 legend: ? = unimplemented, r = reserved bit. shaded cells are not used. pic18f97j60 family ds39762a-page 242 advance information ? 2006 microchip technology inc. 18.6 duplex mode configuration and negotiation the ethernet module does not support automatic duplex mode negotiation. if it is connected to an auto- matic duplex negotiation enabled network switch or ethernet controller, the module will be detected as a half-duplex device. to communicate in full duplex, the module and the remote node (switch, router or ethernet controller) must be manually configured for full-duplex operation. 18.6.1 half-duplex operation the ethernet module operates in half-duplex mode when the fuldpx (macon3<0>) and pdpxmd (phcon1<8>) bits are cleared (= 0 ). if only one of these two bits is set, the module will be in an indetermi- nate state and not function correctly. since switching between full and half-duplex modes may result in this indeterminate state, the application should not transmit any packets (maintain the txrts bit clear), and disable packet reception (maintain the rxen bit clear) during this period. in half-duplex mode, only one ethernet controller may be transmitting on the physical medium at any time. if the application requests a packet to be transmitted by setting the txrts bit while another ethernet controller is already transmitting, the ethernet module will delay, waiting for the remote transmitter to stop. when it stops, the module will attempt to transmit its packet. should another ethernet controller start transmitting at approximately the same time, the data on the wire will become corrupt and a collision will occur. the hardware will handle this condition in one of two ways. if the collision occurs before the number of bytes specified by the ?collision window? in maclcon2 were transmitted, the txrts bit will remain set, the transmit error interrupt will occur, a random exponential backoff delay will elapse, as defined by the ieee 802.3 specifica- tion, and then a new attempt to transmit the packet from the beginning will occur. the application will not need to intervene. if the number of retransmission attempts already matches the ?retransmission maximum? (retmax) defined in maclcon1, the packet will be aborted and the txrts bit will be cleared. the applica- tion will then be responsible for taking appropriate action. the application will be able to determine that the packet was aborted instead of being successfully transmitted by reading the txabrt flag. for more information, see section 18.5.2 ?transmitting packets? . if the collision occurs after the number of bytes speci- fied by the ?collision window? in maclcon2 were transmitted, the packet will be immediately aborted without any retransmission attempts. ordinarily, in 802.3 compliant networks which are properly config- ured, this late collision will not occur. user intervention may be required to correct the issue. this problem may occur as a result of a full-duplex node attempting to transmit on the half-duplex medium. alternately, the module may be attempting to operate in half-duplex mode while it may be connected to a full-duplex network. excessively long cabling and network size may also be a possible cause of late collisions. when set in half-duplex mode, the reset default configuration will loop transmitted packets back to itself. unless the receive filter configuration filters these packets out, they will be written into the circular receive buffer just as any other network traffic. to prevent this, set the hdldis bit. 18.6.2 full-duplex operation the ethernet module operates in full-duplex mode when the fuldpx and pdpxmd bits are both set (= 1 ). if only one of these two bits is clear, the module will be in an indeterminate state and not function correctly. again, since switching between full and half-duplex modes may result in this indeterminate state, the application should not transmit any packets and should disable packet reception during this period. in full-duplex mode, packets will be transmitted while simultaneously packets may be received. given this, it is impossible to cause any collisions when transmitting packets. several configuration fields, such as ?retrans- mission maximum? (retmax) in maclcon1 and ?collision window? (colwin) in maclcon2 will not be used. when set in full-duplex mode, the reset default con- figuration will not loop transmitted packets back to itself. if loopback is desired for diagnostic purposes, the application should set the ploopbk bit (phcon1<14>). enabling loopback in full-duplex mode will disable the twisted-pair output driver and ignore all incoming data, thus dropping any link (if established). all packets received as a result of the loopback configuration will be subject to all enabled receive filters, just as ordinary network traffic would be. ? 2006 microchip technology inc. advance information ds39762a-page 243 pic18f97j60 family 18.7 flow control the ethernet module implements hardware flow con- trol for both full and half-duplex modes. the operation of this feature differs depending on which mode is being used. 18.7.1 half-duplex mode in half-duplex mode, setting the fcen0 bit (eflocon<0>) causes flow control to be enabled. when fcen0 is set, a continuous preamble pattern of alternating ? 1 ?s and ? 0 ?s (55h) will automatically be transmitted on the ethernet medium. any connected nodes will see the transmission and either not transmit anything, waiting for the transmission to end, or will attempt to transmit and immediately cause a collision. because a collision will always occur, no nodes on the network will be able to communicate with each other and no new packets will arrive. when the application causes the module to transmit a packet by setting the txrts bit, the preamble pattern will stop being transmitted. an inter-packet delay will pass as configured by register mabbipg, and then the module will attempt to transmit its packet. during the inter-packet delay, other nodes may begin to transmit. because all traffic was jammed previously, several nodes may begin transmitting and a series of collisions may occur. when the module successfully finishes transmitting its packet or aborts it, the transmission of the preamble pattern will automatically restart. when the application wishes to no longer jam the network, it should clear the fcen0 bit. the preamble transmis- sion will cease and normal network operation will resume. given the detrimental network effects that are possible and lack of effectiveness, it is not recommend that half-duplex flow control be used unless the application will be in a closed network environment with proper testing. 18.7.2 full-duplex mode in full-duplex mode (macon3<0> = 1 ), hardware flow control is implemented by means of transmitting pause control frames, as defined by the ieee 802.3 specifica- tion. pause control frames ar e 64-byte frames consisting of the reserved multicast destination address of 01-80-c2-00-00-01, the source address of the sender, a special pause opcode, a 2-byte pause timer value and padding/crc. normally, when a pause control frame is received by a mac, the mac will finish the packet it is transmitting and then stop transmitting any new frames. the pause timer value will be extracted from the control frame and used to initialize an internal timer. the timer will auto- matically decrement every 512 bit times, or 51.2 s. while the timer is counting down, reception of packets is still enabled. if new pause frames arrive, the timer will be re-initialized with the new pause timer value. when the timer reaches zero, or was sent a frame with a zero pause timer value, the mac that received the pause frame will resume transmitting any pending packets. to prevent a pause frame from stopping all traffic on the entire network, ethernet switches and routers do not propagate pause control frames in full-duplex mode. the pause operation only applies to the recipient. a sample network is shown in figure 18-10. if computer a were to be transmitting too much data to the microcontroller-based application in full-duplex mode, the ethernet module could transmit a pause control frame to stop the data which is being sent to it. the ethernet switch would take the pause frame and stop sending data to the application. if computer a continues to send data, the ethernet switch will buffer the data so it can be transmitted later when its pause timer expires. if the ethernet switch begins to run out of buffer space, it will likely transmit a pause control frame of its own to computer a. if, for some reason the ethernet switch does not gen- erate a pause control frame of its own, or one of the nodes does not properly handle the pause frame it receives, then packets will inevitably be dropped. in any event, any communication between computer a and computer b will always be completely unaffected. figure 18-10: sample full-duplex network pic18f97j60 family ds39762a-page 244 advance information ? 2006 microchip technology inc. to enable flow control in full-duplex mode, set the txpaus and rxpaus bits in the macon1 register. then, at any time that the receiver buffer is running out of space, set the flow control enable bits, fcen1:fcen0 (eflocon<1:0>). the module will automatically finish transmitting anything that was in progress and then send a valid pause frame loaded with the selected pause timer value. depending on the mode selected, the application may need to eventually clear flow control mode by again writing to the fcen bits. when the rxpaus bit is set and a valid pause frame arrives with a non-zero pause timer value, the module will automatically inhibit transmissions. if the txrts bit becomes set to send a packet, the hardware will simply wait until the pause timer expires before attempting to send the packet and subsequently, clearing the txrts bit. normally, this is transparent to the microcontroller, and it will never know that a pause frame had been received. should it be desirable to know when the mac is paused or not, the user should set the passall bit (macon1<1>), then manually interpret the pause control frames which may arrive. table 18-7: summary of registers used with flow control register 18-20: eflocon: ethernet flow control register u-0 u-0 u-0 u-0 u-0 r-0 r/w-0 r/w-0 ? ? ? ? ? fuldpxs fcen1 fcen0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented: read as ? 0 ? bit 2 fuldpxs: read-only mac full-duplex shadow bit 1 = mac is configured for full-duplex mode, fuldpx (macon3<0>) is set 0 = mac is configured for half-duplex mode, fuldpx (macon3<0>) is clear bit 1-0 fcen1:fcen0: flow control enable bits when fuldpxs = 1 : 11 = send one pause frame with a ? 0 ? timer value and then turn flow control off 10 = send pause frames periodically 01 = send one pause frame then turn flow control off 00 = flow control off when fuldpxs = 0 : 11 = flow control on 10 = flow control off 01 = flow control on 00 = flow control off register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page econ1 txrst rxrst dmast csumen txrts rxen ? ?60 macon1 ? ? ? r txpaus rxpaus passall marxen 65 mabbipg ? bbipg6 bbipg5 bbipg4 bbipg 3 bbipg2 bbipg1 bbipg0 65 eflocon ? ? ? ? ? fuldpxs fcen1 fcen0 65 epausl pause timer value register low byte (epaus<7:0>) 65 epaush pause timer value register high byte (epaus<15:8>) 65 legend: ? = unimplemented, r = reserved bit. shaded cells are not used. ? 2006 microchip technology inc. advance information ds39762a-page 245 pic18f97j60 family 18.8 receive filters to minimize microcontroller processing overhead, the ethernet module incorporates a range of different receive filters which can automatically reject packets which are not needed. six different types of packet filters are implemented: ? unicast ? multicast ? broadcast ? pattern match ?magic packet? ? hash table the individual filters are all configured by the erxfcon register (register 18-21). more than one filter can be active at any given time. additionally, the filters can be configured by the andor bit to either logically and or logically or the tests of several filters. in other words, the filters may be set so that only packets accepted by all active filters are accept ed, or a packet accepted by any one filter is accepted. the flowcharts in figure 18-11 and figure 18-12 show the effect that each of the filters will have, depending on the setting of andor. the device can enter promiscuous mode and receive all packets by clearing the erxfcon register. the proper setting of the register will depend on the application requirements. 18.8.1 unicast filter the unicast receive filter checks the destination address of all incoming packets. if the destination address exactly matches the contents of the maadr registers, the packet will meet the unicast filter criteria. 18.8.2 multicast filter the multicast receive filter checks the destination address of all incoming packets. if the least significant bit of the first byte of the destination address is set, the packet will meet the multicast filter criteria. 18.8.3 broadcast filter the broadcast receive filter checks the destination address of all incoming packets. if the destination address is ff-ff-ff-ff-ff-ff, the packet will meet the broadcast filter criteria. 18.8.4 hash table filter the hash table receive filter performs a crc over the six destination address bytes in the packet. the crc is then used as a pointer into the bits of the eht registers. if the pointer points to a bit which is set, the packet meets the hash table filter criteria. for example, if the crc is calculated to be 05h, bit 5 in the hash table will be checked. if it is set, the hash table filter criteria will be met. if every bit is clear in the hash table, the filter criteria will never be met. similarly, if every bit is set in the hash table, the filter criteria will always be met. pic18f97j60 family ds39762a-page 246 advance information ? 2006 microchip technology inc. register 18-21: erxfcon: ethernet receive filter control register r/w-1 r/w-0 r/w-1 r/w-0 r/w-0 r/w-0 r/w-0 r/w-1 ucen andor crcen pmen mpen hten mcen bcen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ucen: unicast filter enable bit when andor = 1 : 1 = packets not having a destination address matching the local mac address will be discarded 0 = filter disabled when andor = 0 : 1 = packets with a destination address matching the local mac address will be accepted 0 = filter disabled bit 6 andor: and/or filter select bit 1 = and: packets will be rejected unless all enabled filters accept the packet 0 = or: packets will be accepted unless all enabled filters reject the packet bit 5 crcen: post-filter crc check enable bit 1 = all packets with an invalid crc will be discarded 0 = the crc validity will be ignored bit 4 pmen: pattern match filter enable bit when andor = 1 : 1 = packets must meet the pattern match criteria or they will be discarded 0 = filter disabled when andor = 0 : 1 = packets which meet the pattern match criteria will be accepted 0 = filter disabled bit 3 mpen: magic packet filter enable bit when andor = 1 : 1 = packets must be magic packets for the local mac address or they will be discarded 0 = filter disabled when andor = 0 : 1 = magic packets for the local mac address will be accepted 0 = filter disabled bit 2 hten: hash table filter enable bit when andor = 1 : 1 = packets must meet the hash table criteria or they will be discarded 0 = filter disabled when andor = 0 : 1 = packets which meet the hash table criteria will be accepted 0 = filter disabled bit 1 mcen: multicast filter enable bit when andor = 1 : 1 = packets must have the least significant bit set in the destination address or they will be discarded 0 = filter disabled when andor = 0 : 1 = packets which have the least significant bit set in the destination address will be accepted 0 = filter disabled bit 0 bcen: broadcast filter enable bit when andor = 1 : 1 = packets must have a destination address of ff-ff-ff-ff-ff-ff or they will be discarded 0 = filter disabled when andor = 0 : 1 = packets which have a destination address of ff-ff-ff-ff-ff-ff will be accepted 0 = filter disabled ? 2006 microchip technology inc. advance information ds39762a-page 247 pic18f97j60 family figure 18-11: receive filtering using or logic crcen set? packet detected on wire, andor = 0 (or) crc valid? ye s ye s accept packet reject packet no ucen set? pmen set? mpen set? hten set? mcen set? bcen set? no no no no no unicast pattern magic packet? hash table multicast broadcast destination? yes yes yes yes yes ye s no no no no no no yes yes yes yes yes ye s no packet? matches? for us? bit set? destination? no pic18f97j60 family ds39762a-page 248 advance information ? 2006 microchip technology inc. figure 18-12: receive filtering using and logic crcen set? packet detected on wire, andor = 1 (and) crc valid? yes yes accept packet reject packet ucen set? pmen set? mpen set? hten set? mcen set? bcen set? no unicast pattern magic packet? hash table multicast broadcast destination? ye s ye s ye s ye s ye s ye s no no no no no no no yes no no yes no yes no yes no yes no yes destination? bit set? for us? matches? packet? ? 2006 microchip technology inc. advance information ds39762a-page 249 pic18f97j60 family 18.8.5 pattern match filter the pattern match filter selects up to 64 bytes from the incoming packet and calculates an ip checksum of the bytes. the checksum is then compared to the epmcs registers. the packet meets the pattern match filter cri- teria if the calculated checksum matches the epmcs registers. the pattern match filter may be useful for filtering packets which have expected data inside them. to use the pattern match filter, the application must program the pattern match offset (epmoh:epmol), all of the pattern match mask bytes (epmm0:epmm7) and the pattern match checksum register pair (epmcsh:epmcsl). the pattern match offset should be loaded with the offset from the beginning of the des- tination address field to the 64-byte window which will be used for the checksum computation. within the 64-byte window, each individual byte can be selectively included or excluded from the checksum computation by setting or clearing the respective bit in the pattern match mask. if a packet is received which would cause the 64 byte window to extend past the end of the crc, the filter criteria will immediately not be met, even if the corresponding mask bits are all ? 0 ?. the pattern match checksum registers should be programmed to the checksum which is expected for the selected bytes. the checksum is calculated in the same manner that the dma module calculates checksums (see section 18.9.2 ?checksum calculations? ). data bytes which have corresponding mask bits programmed to ? 0 ? are completely removed for purposes of calculating the checksum, as opposed to treating the data bytes as zero. as an example, if the application wished to filter all packets having a particular source mac address of 00-04-a3-ff-ff-ff, it could program the pattern match offset to 0000h and then set bits 6, 7 of epmm0 and bits 0, 1, 2 and 3 of epmm1 (assuming all other mask bits are ? 0 ?). the proper checksum to program into the epmcs registers would be 5bfch. as an alter- native configuration, it could program the offset to 0006h and set bits 0, 1, 2, 3, 4 and 5 of epmm0. the checksum would still be 5bfch. however, the second case would be less desirable as packets less than 70 bytes long could never meet the pattern match criteria, even if they would generate the proper checksum given the mask configuration. another example of a pattern match filter is illustrated in figure 18-13. figure 18-13: sample pattern match format sa empoh:epmol = 0006h fcs da type/length data bytes used for checksum computation epmm0:epmm7 = 0000000000001f0ah 11 22 33 44 55 66 77 88 99 aa bb cc 00 5a 09 0a 0b 0c 0d . . . 40 . . . fe 45 23 01 received data field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 . . . 70 . . . byte # 64-byte window used for pattern match input configuration: values used for checksum computation = {88h, aah, 09h, 0ah, 0bh, 0ch, 0dh, 00h} epmcsh:epmcsl = 563fh note: received data is shown in hexadecimal. byte numbers are shown in decimal format. (00h padding byte added by hardware) pic18f97j60 family ds39762a-page 250 advance information ? 2006 microchip technology inc. 18.8.6 magic packet filter the magic packet pattern consists of a sync pattern of six ffh bytes, followed by 16 repeats of the destination address (figure 18-14). the magic packet filter checks the destination address and data fields of all incoming packets. if the destination address matches the maadr registers and the data field holds a valid magic packet pattern someplace within it, then the packet will meet the magic packet filter criteria. figure 18-14: sample magic packet? format sa fcs da type/length 11 22 33 44 55 66 00 fe 09 0a 0b 0c 0d 0e received data field 77 88 99 aa bb cc ef 54 32 10 ff ff ff ff ff 00 ff ff ff ff ff ff 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 19 1a 1b 1c 1d 1e data sync pattern sixteen repeats of the station address comments ? 2006 microchip technology inc. advance information ds39762a-page 251 pic18f97j60 family 18.9 direct memory access controller the ethernet module incorporates a dual purpose dma controller, which can be used to copy data between loca- tions within the 8-kbyte memory buffer. it can also be used to calculate a 16-bit checksum which is compatible with various industry standard communication protocols, including tcp, udp, ip, icmp, etc. the dma is controlled using three pointers and a few status/control bits: ? edmasth:edmastl ? source start address ? edmandh:edmandl ? source end address ? edmadsth:edmadstl ? destination start address ? econ1 pic18f97j60 family ds39762a-page 252 advance information ? 2006 microchip technology inc. after the dma module has been initialized and has begun its copy, one instruction cycle (t cy ) will be required for each byte copied. however, if the cpi core executes a read or write instruction on the edata reg- ister, or if the ethernet receive hardware accumulates one byte of data, the dma will stall that cycle, yielding to the higher priority operation. if a maximum size 1518-byte packet was copied while no other memory bandwidth was being used, the dma module would require slightly more than 145.7 s to complete at a core frequency of 41.667 mhz. the time required to copy a minimum size packet of 64 bytes would be approximately 6.2 s (at 41.667 mhz) plus register configuration time. 18.9.2 checksum calculations the checksum calculation logic treats the source data as a series of 16-bit big-endian integers. if the source range contains an odd number of bytes, a padding byte of 00h is effectively added to the end of the series for purposes of calculating the checksum. the calculated checksum is the 16-bit one?s complement of the one?s complement sum of all 16-bit integers. for example, if the bytes included in the checksum were {89h, abh, cdh}, the checksum would begin by computing 89abh + cd00h. a carry out of the 16th bit would occur in the example, so in 16-bit one?s complement arithmetic, it would be added back to the first bit. the resulting value of 56ach would finally be complemented to achieve a checksum of a953h. to calculate a checksum: 1. set the edmast and edmand register pairs to point to the first and last bytes of buffer data to be included in the checksum. care should be taken when programming these pointers to prevent a never-ending checksum calculation due to receive buffer wrapping. 2. to generate an optional interrupt when the checksum calculation is done, set the dmaie (eie<5>) and ethie (pie2<5>) bits and clear the dmaif (eir<5>) bit. 3. start the calculation by setting the csumen (econ1<4>) and dmast (econ1<5>) bits. when the checksum is finished being calculated, the hardware will clear the dmast bit, set the dmaif bit and an interrupt will be generated if enabled. the dma pointers will not be modified, and no memory will be written to. the edmacsh and edmacsl registers will contain the calculated checksum. the application may write this value into a packet, compare this value with zero (to validate a received block of data containing a checksum field in it), or compare it with some other checksum, such as a pseudo header checksum used in various protocols (tcp, udp, etc.). various protocols, such as tcp and ip, have a checksum field inside a range of data which the checksum covers. if a packet is received that requires checksum validation, the user application can do the following: 1. read the checksum from the packet and save it to a temporary location. 2. write zeros to the checksum field. 3. calculate a new checksum using the dma controller. 4. compare the results with the saved checksum from step 1. writing to the receive buffer is permitted when the write address is protected by means of the erxrdpt point- ers. see section 18.5.3 ?receiving packets? for additional information. the ip checksum has unique mathematical properties which may be used in some cases to reduce the processing requirements further. writing to the receive buffer may be unnecessary in some applications. when operating the dma in checksum mode, it takes one instruction cycle (t cy ) for every byte included in the checksum. as a result, if a checksum over 1446 bytes was performed, the dma module would require slightly more than 138.8 s to complete the operation at 41.667 mhz. at the same frequency, a small 20-byte header field would take approximately 1.9s plus dma setup time to calculate a sum. these estimated times assume that the ethernet receive hardware does not need memory access bandwidth and the cpu core does not issue any reads or writes to the edata register while the dma is computing. like the dma copy mode, the checksum operation will not start until the txrts bit (econ1<3>) is clear. this may considerably increase the checksum calculation time if the application transmits a large packet and immediately attempts to validate a checksum on a received packet. ? 2006 microchip technology inc. advance information ds39762a-page 253 pic18f97j60 family table 18-8: summary of registers associated with the dma controller 18.10 module resets the ethernet module provides selective module resets: ? transmit only reset ? receive only reset 18.10.1 power-on reset (por) the ethernet module uses the microcontroller?s power-on reset pulse to start in the initialized state when v dd is adequate for operation. a minimum rise rate for v dd is specified (see section 27.0 ?electrical characteristics? ). after a por, the contents of the ethernet buffer memory will be unknown. all sfr and phy registers will be loaded with their specified reset values. how- ever, the phy registers should not be accessed until the phy start-up timer has expired and the phyrdy bit (estat<0>) becomes set, or at least 1 ms has passed since the ethen bit is set. for more details, see section 18.1.3.1 ?start-up timer? . 18.10.2 transmit only reset the transmit only reset is performed by writing a ? 1 ? to the txrst bit (econ1<7>). this resets the transmit logic only. other register and control blocks, such as buffer management and host interface, are not affected by a transmit only reset event. to return to normal operation, the txrst bit is cleared in software. 18.10.3 receive only reset the receive only reset is performed by writing a ? 1 ? to the rxrst bit (econ1<6>). this action resets receive logic only. other register and control blocks, such as the buffer management and host interface blocks, are not affected by a receive only reset event. to return to normal operation, the rxrst bit is cleared in software. register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page eie ? pktie dmaie linkie txie ? txerie rxerie 63 eir ? pktif dmaif linkif txif ? txerif rxerif 63 econ1 txrst rxrst dmast csumen txrts rxen ? ?60 erxndl receive end register low byte (erxnd<7:0>) 63 erxndh ? ? ? receive end register high byte (erxnd<12:8>) 63 edmastl dma start register low byte (edmast<7:0>) 63 edmasth ? ? ? dma start register high byte (edmast<12:8>) 63 edmandl dma end register low byte (edmand<7:0>) 63 edmandh ? ? ? dma end register high byte (edmand<12:8>) 63 edmadstl dma destination register low byte (edmadst<7:0>) 63 edmadsth ? ? ? dma destination register high byte (edmadst<12:8>) 63 edmacsl dma checksum register low byte (edmacs<7:0>) 63 edmacsh dma checksum register high byte (edmacs<15:8>) 63 legend: ? = unimplemented. shaded cells are not used. pic18f97j60 family ds39762a-page 254 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 255 pic18f97j60 family 19.0 master synchronous serial port (mssp) module 19.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c?) - full master mode - slave mode (with general address call) the i 2 c interface supports the following modes in hardware: ?master mode ? multi-master mode ? slave mode the 64-pin and 80-pin devices of the pic18f97j60 family have one mssp module, designated as mssp1. the 100-pin devices have two mssp modules, desig- nated as mssp1 and mssp2. each module operates independently of the other. 19.2 control registers each mssp module has three associated control registers. these include a status register (sspxstat) and two control registers (sspxcon1 and sspxcon2). the use of these registers and their indi- vidual configuration bits differ significantly depending on whether the mssp module is operating in spi or i 2 c mode. additional details are provided under the individual sections. 19.3 spi mode the spi mode allows 8 bits of data to be synchronously transmitted and received simultaneously. all four modes of spi are supported. to accomplish communication, typically three pins are used: ? serial data out (sdox) ? rc5/sdo1 (or rd4/sdo2 for 100-pin devices) ? serial data in (sdix) ? rc4/sdi1/sda1 (or rd5/sdi2/sda2 for 100-pin devices) ? serial clock (sckx) ? rc3/sck1/scl1 (or rd6/sck2/scl2 for 100-pin devices) additionally, a fourth pin may be used when in a slave mode of operation: ? slave select (ssx ) ? rf7/ss1 (or rd7/ss2 for 100-pin devices) figure 19-1 shows the block diagram of the mssp module when operating in spi mode. figure 19-1: mssp block diagram (spi mode) note: throughout this section, generic refer- ences to an mssp module in any of its operating modes may be interpreted as being equally applicable to mssp1 or mssp2. register names and module i/o signals use the generic designator ?x? to indicate the use of a numeral to distinguish a particular module when required. control bit names are not individuated. note: in devices with more than one mssp module, it is very important to pay close attention to the sspxcon register names. ssp1con1 and ssp1con2 control different operational aspects of the same module, while ssp1con1 and ssp2con1 control the same features for two different modules. ( ) read write internal data bus sspxsr reg sspm3:sspm0 bit 0 shift clock ss x control enable edge select clock select tmr2 output t osc prescaler 4, 16, 64 2 edge select 2 4 data to txx/rxx in sspxsr tris bit 2 smp:cke sdox sspxbuf reg sdix ssx sckx pic18f97j60 family ds39762a-page 256 advance information ? 2006 microchip technology inc. 19.3.1 registers each mssp module has four registers for spi mode operation. these are: ? mssp control register 1 (sspxcon1) ? mssp status register (sspxstat) ? serial receive/transmit buffer register (sspxbuf) ? mssp shift register (sspxsr) ? not directly accessible sspxcon1 and sspxstat are the control and status registers in spi mode operation. the sspxcon1 register is readable and writable. the lower 6 bits of the sspxstat are read-only. the upper two bits of the sspxstat are read/write. sspxsr is the shift register used for shifting data in or out. sspxbuf is the buffer register to which data bytes are written to or read from. in receive operations, sspxsr and sspxbuf together create a double-buffered receiver. when sspxsr receives a complete byte, it is transferred to sspxbuf and the sspxif interrupt is set. during transmission, the sspxbuf is not double-buffered. a write to sspxbuf will write to both sspxbuf and sspxsr. register 19-1: sspxstat: msspx status register (spi mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke (1) d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 smp: sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode. bit 6 cke: spi clock select bit (1) 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state bit 5 d/a : data/address bit used in i 2 c mode only. bit 4 p: stop bit used in i 2 c mode only. this bit is cleared when the mssp module is disabled, sspen is cleared. bit 3 s: start bit used in i 2 c mode only. bit 2 r/w : read/write information bit used in i 2 c mode only. bit 1 ua: update address bit used in i 2 c mode only bit 0 bf: buffer full status bit (receive mode only) 1 = receive complete, sspxbuf is full 0 = receive not complete, sspxbuf is empty note 1: polarity of clock state is set by the ckp bit (sspxcon1<4>). ? 2006 microchip technology inc. advance information ds39762a-page 257 pic18f97j60 family register 19-2: sspxcon1: msspx control register 1 (spi mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov (1) sspen (2) ckp sspm3 (3) sspm2 (3) sspm1 (3) sspm0 (3) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 wcol: write collision detect bit (transmit mode only) 1 = the sspxbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit (1) spi slave mode: 1 = a new byte is received while the sspxbuf register is still holding the previous data. in case of overflow, the data in sspxsr is lost. overflow can only occur in slave mode. the user must read the sspxbuf, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = no overflow bit 5 sspen: master synchronous serial port enable bit (2) 1 = enables serial port and configures sckx, sdox, sdix and ssx as serial port pins 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit 1 = idle state for clock is a high level 0 = idle state for clock is a low level bit 3-0 sspm3:sspm0: master synchronous serial port mode select bits (3) 0101 = spi slave mode, clock = sckx pin, ssx pin control disabled, ssx can be used as i/o pin 0100 = spi slave mode, clock = sckx pin, ssx pin control enabled 0011 = spi master mode, clock = tmr2 output/2 0010 = spi master mode, clock = f osc /64 0001 = spi master mode, clock = f osc /16 0000 = spi master mode, clock = f osc /4 note 1: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspxbuf register. 2: when enabled, these pins must be properly configured as input or output. 3: bit combinations not specifically listed here are either reserved or implemented in i 2 c? mode only. pic18f97j60 family ds39762a-page 258 advance information ? 2006 microchip technology inc. 19.3.2 operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspxcon1<5:0> and sspxstat<7:6>). these control bits allow the following to be specified: ? master mode (sckx is the clock output) ? slave mode (sckx is the clock input) ? clock polarity (idle state of sckx) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sckx) ? clock rate (master mode only) ? slave select mode (slave mode only) each mssp module consists of a transmit/receive shift register (sspxsr) and a buffer register (sspxbuf). the sspxsr shifts the data in and out of the device, msb first. the sspxbuf holds the data that was written to the sspxsr until the received data is ready. once the 8 bits of data have been received, that byte is moved to the sspxbuf register. then, the buffer full detect bit, bf (sspxstat<0>), and the interrupt flag bit, sspxif, are set. this double-buffering of the received data (sspxbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspxbuf register during transmission/reception of data will be ignored and the write collision detect bit, wcol (sspxcon1<7>), will be set. user software must clear the wcol bit so that it can be determined if the following write(s) to the sspxbuf register completed successfully. when the application software is expecting to receive valid data, the sspxbuf should be read before the next byte of data to transfer is written to the sspxbuf. the buffer full bit, bf (sspxstat<0>), indicates when sspxbuf has been loaded with the received data (transmission is complete). when the sspxbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has completed. the sspxbuf must be read and/or written. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. example 19-1 shows the loading of the ssp1buf (ssp1sr) for data transmission. the sspxsr is not directly readable or writable and can only be accessed by addressing the sspxbuf register. additionally, the sspxstat register indicates the various status conditions. example 19-1: loading the ssp1buf (ssp1sr) register loop btfss ssp1stat, bf ;has data been received (transmit complete)? bra loop ;no movf ssp1buf, w ;wreg reg = contents of ssp1buf movwf rxdata ;save in user ram, if data is meaningful movf txdata, w ;w reg = contents of txdata movwf ssp1buf ;new data to xmit ? 2006 microchip technology inc. advance information ds39762a-page 259 pic18f97j60 family 19.3.3 enabling spi i/o to enable the serial port, mssp enable bit, sspen (sspxcon1<5>), must be set. to reset or reconfigure spi mode, clear the sspen bit, reinitialize the sspxcon registers and then set the sspen bit. this configures the sdix, sdox, sckx and ssx pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed as follows: ? sdix is automatically controlled by the spi module ? sdox must have trisc<5> (or trisd<4>) bit cleared ? sckx (master mode) must have trisc<3> (or trisd<6>) bit cleared ? sckx (slave mode) must have trisc<3> (or trisd<6>) bit set ?ss x must have trisf<7> (or trisd<7>) bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. 19.3.4 typical connection figure 19-2 shows a typical connection between two microcontrollers. the master controller (processor 1) initiates the data transfer by sending the sckx signal. data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. both processors should be programmed to the same clock polarity (ckp), then both controllers would send and receive data at the same time. whether the data is meaningful (or dummy data) depends on the application software. this leads to three scenarios for data transmission: ? master sends data ? slave sends dummy data ? master sends data ? slave sends data ? master sends dummy data ? slave sends data figure 19-2: spi master/slave connection serial input buffer (sspxbuf) shift register (sspxsr) msb lsb sdox sdix processor 1 sckx spi master sspm3:sspm0 = 00xxb serial input buffer (sspxbuf) shift register (sspxsr) lsb msb sdix sdox processor 2 sckx spi slave sspm3:sspm0 = 010xb serial clock pic18f97j60 family ds39762a-page 260 advance information ? 2006 microchip technology inc. 19.3.5 master mode the master can initiate the data transfer at any time because it controls the sckx. the master determines when the slave (processor 2, figure 19-2) will broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspxbuf register is written to. if the spi is only going to receive, the sdox output could be disabled (programmed as an input). the sspxsr register will continue to shift in the signal present on the sdix pin at the programmed clock rate. as each byte is received, it will be loaded into the sspxbuf register as if a normal received byte (interrupts and status bits appropriately set). this could be useful in receiver applications as a ?line activity monitor? mode. the clock polarity is selected by appropriately programming the ckp bit (sspxcon1<4>). this then, would give waveforms for spi communication as shown in figure 19-3, figure 19-5 and figure 19-6, where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user-programmable to be one of the following: ?f osc /4 (or t cy ) ?f osc /16 (or 4 ? t cy ) ?f osc /64 (or 16 ? t cy ) ? timer2 output/2 this allows a maximum data rate (at 40 mhz) of 10.00 mbps. figure 19-3 shows the waveforms for master mode. when the cke bit is set, the sdox data is valid before there is a clock edge on sckx. the change of the input sample is shown based on the state of the smp bit. the time when the sspxbuf is loaded with the received data is shown. figure 19-3: spi mode waveform (master mode) sckx (ckp = 0 sckx (ckp = 1 sckx (ckp = 0 sckx (ckp = 1 4 clock modes input sample input sample sdix bit 7 bit 0 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdix sspxif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspxbuf sspxsr to sspxbuf sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) next q4 cycle after q2 bit 0 ? 2006 microchip technology inc. advance information ds39762a-page 261 pic18f97j60 family 19.3.6 slave mode in slave mode, the data is transmitted and received as the external clock pulses appear on sckx. when the last bit is latched, the sspxif interrupt flag bit is set. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sckx pin. the idle state is determined by the ckp bit (sspxcon1<4>). while in slave mode, the external clock is supplied by the external clock source on the sckx pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. when a byte is received, the device will wake-up from sleep. 19.3.7 slave select synchronization the ssx pin allows a synchronous slave mode. the spi must be in slave mode with ssx pin control enabled (sspxcon1<3:0> = 04h). when the ssx pin is low, transmission and reception are enabled and the sdox pin is driven. when the ssx pin goes high, the sdox pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the application. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ssx pin to a high level or clearing the sspen bit. to emulate two-wire communication, the sdox pin can be connected to the sdix pin. when the spi needs to operate as a receiver, the sdox pin can be configured as an input. this disables transmissions from the sdox. the sdix can always be left as an input (sdix function) since it cannot create a bus conflict. figure 19-4: slave synchronization waveform note 1: when the spi is in slave mode with ssx pin control enabled (sspxcon1<3:0> = 0100 ), the spi module will reset if the ssx pin is set to v dd . 2: if the spi is used in slave mode with cke set, then the ssx pin control must be enabled. sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 sdox bit 7 bit 6 bit 7 sspxif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspxbuf sspxsr to sspxbuf ssx flag bit 0 bit 7 bit 0 next q4 cycle after q2 pic18f97j60 family ds39762a-page 262 advance information ? 2006 microchip technology inc. figure 19-5: spi mode waveform (slave mode with cke = 0 ) figure 19-6: spi mode waveform (slave mode with cke = 1 ) sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspxif interrupt (smp = 0 ) cke = 0 ) cke = 0 ) (smp = 0 ) write to sspxbuf sspxsr to sspxbuf ssx flag optional next q4 cycle after q2 bit 0 sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 bit 0 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspxif interrupt (smp = 0 ) cke = 1 ) cke = 1 ) (smp = 0 ) write to sspxbuf sspxsr to sspxbuf ssx flag not optional next q4 cycle after q2 ? 2006 microchip technology inc. advance information ds39762a-page 263 pic18f97j60 family 19.3.8 operation in power-managed modes in spi master mode, module clocks may be operating at a different speed than when in full power mode. in the case of sleep mode, all clocks are halted. in idle modes, a clock is provided to the peripherals. that clock should be from the primary clock source, the secondary clock (timer1 oscillator at 32.768 khz) or the intrc source. see section 2.7 ?clock sources and oscillator switching? for additional information. in most cases, the speed that the master clocks spi data is not important; however, this should be evaluated for each system. if mssp interrupts are enabled, they can wake the controller from sleep mode, or one of the idle modes, when the master completes sending data. if an exit from sleep or idle mode is not desired, mssp interrupts should be disabled. if the sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the devices wakes. after the device returns to run mode, the module will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in any power-managed mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set and if enabled, will wake the device. 19.3.9 effects of a reset a reset disables the mssp module and terminates the current transfer. 19.3.10 bus mode compatibility table 19-1 shows the compatibility between the standard spi modes and the states of the ckp and cke control bits. table 19-1: spi bus modes there is also an smp bit which controls when the data is sampled. 19.3.11 spi clock speed and module interactions because mssp1 and mssp2 are independent modules, they can operate simultaneously at different data rates. setting the sspm3:sspm0 bits of the sspxcon1 register determines the rate for the corresponding module. an exception is when both modules use timer2 as a time base in master mode. in this instance, any changes to the timer2 operation will affect both mssp modules equally. if different bit rates are required for each module, the user should select one of the other three time base options for one of the modules. standard spi mode terminology control bits state ckp cke 0, 0 0 1 0, 1 0 0 1, 0 1 1 1, 1 1 0 pic18f97j60 family ds39762a-page 264 advance information ? 2006 microchip technology inc. table 19-2: registers associated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir3 ssp2if (1) bcl2if rc2if tx2if tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie (1) bcl2ie rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 61 ipr3 ssp2ip (1) bcl2ip rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 61 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 61 trisd trisd7 (1) trisd6 (1) trisd5 (1) trisd4 (1) trisd3 trisd2 trisd1 trisd0 61 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 61 ssp1buf mssp1 receive buffer/transmit register 60 ssp1con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 60 ssp1stat smp cke d/a p s r/w ua bf 60 ssp2buf mssp2 receive buffer/transmit register 63 ssp2con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 63 ssp2stat smp cke d/a p s r/w ua bf 63 legend: shaded cells are not used by the mssp module in spi mode. note 1: these bits are only available in 100-pin devices; otherwise, they are unimplemented and read as ? 0 ?. ? 2006 microchip technology inc. advance information ds39762a-page 265 pic18f97j60 family 19.4 i 2 c mode the mssp module in i 2 c mode fully implements all master and slave functions (including general call support) and provides interrupts on start and stop bits in hardware to determine a free bus (multi-master function). the mssp module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. two pins are used for data transfer: ? serial clock (sclx) ? rc3/sck1/scl1 (or rd6/sck2/scl2 for 100-pin devices) ? serial data (sdax) ? rc4/sdi1/sda1 (or rd5/sdi2/sda2 for 100-pin devices) the user must configure these pins as inputs by setting the trisc<4:3> or trisd<5:4> bits. figure 19-7: mssp block diagram (i 2 c? mode) 19.4.1 registers the mssp module has six registers for i 2 c operation. these are: ? mssp control register 1 (sspxcon1) ? mssp control register 2 (sspxcon2) ? mssp status register (sspxstat) ? serial receive/transmit buffer register (sspxbuf) ? mssp shift register (sspxsr) ? not directly accessible ? mssp address register (sspxadd) sspxcon1, sspxcon2 and sspxstat are the control and status registers in i 2 c mode operation. the sspxcon1 and sspxcon2 registers are readable and writable. the lower 6 bits of the sspxstat are read-only. the upper two bits of the sspxstat are read/write. many of the bits in sspxcon2 assume different functions, depending on whether the module is operat- ing in master or slave mode; bits <5:1> also assume different names in slave mode. the different aspects of sspxcon2 are shown in register 19-5 (for master mode) and register 19-6 (slave mode). sspxsr is the shift register used for shifting data in or out. sspxbuf is the buffer register to which data bytes are written to or read from. sspxadd register holds the slave device address when the mssp is configured in i 2 c slave mode. when the mssp is configured in master mode, the lower seven bits of sspxadd act as the baud rate generator reload value. in receive operations, sspxsr and sspxbuf together create a double-buffered receiver. when sspxsr receives a complete byte, it is transferred to sspxbuf and the sspxif interrupt is set. during transmission, the sspxbuf is not double-buffered. a write to sspxbuf will write to both sspxbuf and sspxsr. read write sspxsr reg match detect sspxadd reg start and stop bit detect sspxbuf reg internal data bus addr match set, reset s, p bits (sspxstat reg) shift clock msb lsb sclx sdax address mask pic18f97j60 family ds39762a-page 266 advance information ? 2006 microchip technology inc. register 19-3: sspxstat: msspx status register (i 2 c? mode) r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a p (1) s (1) r/w (2,3) ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 smp: slew rate control bit in master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high-speed mode (400 khz) bit 6 cke: smbus select bit in master or slave mode: 1 = enable smbus specific inputs 0 = disable smbus specific inputs bit 5 d/a : data/address bit in master mode: reserved. in slave mode: 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (1) 1 = indicates that a stop bit has been detected last 0 = stop bit was not detected last bit 3 s: start bit (1) 1 = indicates that a start bit has been detected last 0 = start bit was not detected last bit 2 r/w : read/write information bit (i 2 c mode only) (2,3) in slave mode: 1 = read 0 = write in master mode: 1 = transmit is in progress 0 = transmit is not in progress bit 1 ua: update address bit (10-bit slave mode only) 1 = indicates that the user needs to update the address in the sspxadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit in transmit mode: 1 = sspxbuf is full 0 = sspxbuf is empty in receive mode: 1 = sspxbuf is full (does not include the ack and stop bits) 0 = sspxbuf is empty (does not include the ack and stop bits) note 1: this bit is cleared on reset and when sspen is cleared. 2: this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit or not ack bit. 3: oring this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in active mode. ? 2006 microchip technology inc. advance information ds39762a-page 267 pic18f97j60 family register 19-4: sspxcon1: msspx control register 1 (i 2 c? mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 wcol: write collision detect bit in master transmit mode: 1 = a write to the sspxbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started (must be cleared in software) 0 = no collision in slave transmit mode: 1 = the sspxbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision in receive mode (master or slave modes): this is a ?don?t care? bit. bit 6 sspov: receive overflow indicator bit in receive mode: 1 = a byte is received while the sspxbuf register is still holding the previous byte (must be cleared in software) 0 = no overflow in transmit mode: this is a ?don?t care? bit in transmit mode. bit 5 sspen: master synchronous serial port enable bit 1 = enables the serial port and configures the sdax and sclx pins as the serial port pins (1) 0 = disables serial port and configures these pins as i/o port pins (1) bit 4 ckp: sckx release control bit in slave mode: 1 = release clock 0 = holds clock low (clock stretch), used to ensure data setup time in master mode: unused in this mode. bit 3-0 sspm3:sspm0: master synchronous serial port mode select bits 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled (2) 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled (2) 1011 = i 2 c firmware controlled master mode (slave idle) (2) 1000 = i 2 c master mode, clock = f osc /(4 * (sspadd + 1)) (2) 0111 = i 2 c slave mode, 10-bit address (2) 0110 = i 2 c slave mode, 7-bit address (2) note 1: when enabled, the sdax and sclx pins must be configured as inputs. 2: bit combinations not specifically listed here are either reserved or implemented in spi mode only. pic18f97j60 family ds39762a-page 268 advance information ? 2006 microchip technology inc. register 19-5: sspxcon2: msspx control register 2 (i 2 c? master mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat ackdt (1) acken (2) rcen (2) pen (2) rsen (2) sen (2) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gcen: general call enable bit (slave mode only) unused in master mode. bit 6 ackstat: acknowledge status bit (master transmit mode only) 1 = acknowledge was not received from slave 0 = acknowledge was received from slave bit 5 ackdt: acknowledge data bit (master receive mode only) (1) 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (2) 1 = initiate acknowledge sequence on sdax and sclx pins and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (master receive mode only) (2) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (2) 1 = initiate stop condition on sdax and sclx pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enable bit (2) 1 = initiate repeated start condition on sdax and sclx pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable/stretch enable bit (2) 1 = initiate start condition on sdax and sclx pins. automatically cleared by hardware. 0 = start condition idle note 1: value that will be transmitted when the user initiates an acknowledge sequence at the end of a receive. 2: if the i 2 c module is active, these bits may not be set (no spooling) and the sspxbuf may not be written (or writes to the sspxbuf are disabled). ? 2006 microchip technology inc. advance information ds39762a-page 269 pic18f97j60 family register 19-6: sspxcon2: msspx control register 2 (i 2 c? slave mode) r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 gcen ackstat admsk5 admsk4 admsk3 admsk2 admsk1 sen (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gcen: general call enable bit (slave mode only) 1 = enable interrupt when a general call address (0000h) is received in the sspxsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit unused in slave mode. bit 5-2 admsk5:admsk2: slave address mask select bits 1 = masking of corresponding bits of sspxadd enabled 0 = masking of corresponding bits of sspxadd disabled bit 1 admsk1: slave address least significant mask select bit(s) i n 7 - bit address mode : 1 = masking of sspxadd<1> only enabled 0 = masking of sspxadd<1> only disabled in 1 0- bit address mode : 1 = masking of sspxadd<1:0> enabled 0 = masking of sspxadd<1:0> disabled bit 0 sen: stretch enable bit (1) 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: if the i 2 c module is active, this bit may not be set (no spooling) and the sspxbuf may not be written (or writes to the sspxbuf are disabled). pic18f97j60 family ds39762a-page 270 advance information ? 2006 microchip technology inc. 19.4.2 operation the mssp module functions are enabled by setting the mssp enable bit, sspen (sspxcon1<5>). the sspxcon1 register allows control of the i 2 c operation. four mode selection bits (sspxcon1<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c master mode, clock = (f osc /4) x (sspxadd + 1) ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c slave mode (7-bit address) with start and stop bit interrupts enabled ?i 2 c slave mode (10-bit address) with start and stop bit interrupts enabled ?i 2 c firmware controlled master mode, slave is idle selection of any i 2 c mode, with the sspen bit set, forces the sclx and sdax pins to be open-drain, provided these pins are programmed to inputs by setting the appropriate trisc or trisd bits. to ensure proper operation of the module, pull-up resistors must be provided externally to the sclx and sdax pins. 19.4.3 slave mode in slave mode, the sclx and sdax pins must be configured as inputs (trisc<4:3> or trisd<5:4> set). the mssp module will override the input state with the output data when required (slave-transmitter). the i 2 c slave mode hardware will always generate an interrupt on an exact address match. in addition, address masking will also allow the hardware to gener- ate an interrupt for more than one address (up to 31 in 7-bit addressing, and up to 63 in 10-bit addressing). through the mode select bits, the user can also choose to interrupt on start and stop bits. when an address is matched, or the data transfer after an address match is received, the hardware auto- matically will generate the acknowledge (ack ) pulse and load the sspxbuf register with the received value currently in the sspxsr register. any combination of the following conditions will cause the mssp module not to give this ack pulse: ? the buffer full bit, bf (sspxstat<0>), was set before the transfer was received. ? the overflow bit, sspov (sspxcon1<6>), was set before the transfer was received. in this case, the sspxsr register value is not loaded into the sspxbuf, but bit sspxif is set. the bf bit is cleared by reading the sspxbuf register, while bit sspov is cleared through software. the sclx clock input must have a minimum high and low for proper operation. the high and low times of the i 2 c specification, as well as the requirement of the mssp module, are shown in timing parameter 100 and parameter 101. 19.4.3.1 addressing once the mssp module has been enabled, it waits for a start condition to occur. following the start condition, the 8 bits are shifted into the sspxsr register. all incoming bits are sampled with the rising edge of the clock (sclx) line. the value of register sspxsr<7:1> is compared to the value of the sspxadd register. the address is compared on the falling edge of the eighth clock (sclx) pulse. if the addresses match and the bf and sspov bits are clear, the following events occur: 1. the sspxsr register value is loaded into the sspxbuf register. 2. the buffer full bit, bf, is set. 3. an ack pulse is generated. 4. the mssp interrupt flag bit, sspxif, is set (and interrupt is generated, if enabled) on the falling edge of the ninth sclx pulse. in 10-bit address mode, two address bytes need to be received by the slave. the five most significant bits (msbs) of the first address byte specify if this is a 10-bit address. bit r/w (sspxstat<2>) must specify a write so the slave device will receive the second address byte. for a 10-bit address, the first byte would equal ? 11110 a9 a8 0 ?, where ? a9 ? and ? a8 ? are the two msbs of the address. the sequence of events for 10-bit address is as follows, with steps 7 through 9 for the slave-transmitter: 1. receive first (high) byte of address (bits sspxif, bf and ua are set). 2. update the sspxadd register with second (low) byte of address (clears bit ua and releases the sclx line). 3. read the sspxbuf register (clears bit bf) and clear flag bit, sspxif. 4. receive second (low) byte of address (bits sspxif, bf and ua are set). 5. update the sspxadd register with the first (high) byte of address. if match releases sclx line, this will clear bit ua. 6. read the sspxbuf register (clears bit bf) and clear flag bit, sspxif. 7. receive repeated start condition. 8. receive first (high) byte of address (bits sspxif and bf are set). 9. read the sspxbuf register (clears bit bf) and clear flag bit sspxif. ? 2006 microchip technology inc. advance information ds39762a-page 271 pic18f97j60 family 19.4.3.2 address masking masking an address bit causes that bit to become a ?don?t care?. when one address bit is masked, two addresses will be acknowledged and cause an interrupt. it is possible to mask more than one address bit at a time, which makes it possible to acknowledge up to 31 addresses in 7-bit mode and up to 63 addresses in 10-bit mode (see example 19-2). the i 2 c slave behaves the same way whether address masking is used or not. however, when address masking is used, the i 2 c slave can acknowledge multiple addresses and cause interrupts. when this occurs, it is necessary to determine which address caused the interrupt by checking sspxbuf. in 7-bit address mode, address mask bits, admsk<5:1> (sspxcon2<5:1>), mask the corresponding address bits in the sspxadd register. for any admsk bits that are set (admsk pic18f97j60 family ds39762a-page 272 advance information ? 2006 microchip technology inc. 19.4.3.3 reception when the r/w bit of the address byte is clear and an address match occurs, the r/w bit of the sspxstat register is cleared. the received address is loaded into the sspxbuf register and the sdax line is held low (ack ). when the address byte overflow condition exists, then the no acknowledge (ack ) pulse is given. an overflow condition is defined as either bit bf (sspxstat<0>) is set, or bit sspov (sspxcon1<6>) is set. an mssp interrupt is generated for each data transfer byte. the interrupt flag bit, sspxif, must be cleared in software. the sspxstat register is used to determine the status of the byte. if sen is enabled (sspxcon2<0> = 1 ), sckx/sclx (rc3 or rd6) will be held low (clock stretch) following each data transfer. the clock must be released by setting bit, ckp (sspxcon1<4>). see section 19.4.4 ?clock stretching? for more details. 19.4.3.4 transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspxstat register is set. the received address is loaded into the sspxbuf register. the ack pulse will be sent on the ninth bit and pin rc3 or rd6 is held low, regardless of sen (see section 19.4.4 ?clock stretching? for more details). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspxbuf register which also loads the sspxsr register. then pin rc3 or rd6 should be enabled by setting bit, ckp (sspxcon1<4>). the eight data bits are shifted out on the falling edge of the sclx input. this ensures that the sdax signal is valid during the sclx high time (figure 19-10). the ack pulse from the master-receiver is latched on the rising edge of the ninth sclx input pulse. if the sdax line is high (not ack ), then the data transfer is complete. in this case, when the ack is latched by the slave, the slave logic is reset (resets sspxstat register) and the slave monitors for another occurrence of the start bit. if the sdax line was low (ack ), the next transmit data must be loaded into the sspxbuf register. again, pin rc3 or rd6 must be enabled by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspxif bit must be cleared in software and the sspxstat register is used to determine the status of the byte. the sspxif bit is set on the falling edge of the ninth clock pulse. ? 2006 microchip technology inc. advance information ds39762a-page 273 pic18f97j60 family figure 19-8: i 2 c? slave mode timing with sen = 0 (reception, 7-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) sspov (sspxcon1<6>) s 12345678912345678912345 789 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspxbuf is read bus master terminates transfer sspov is set because sspxbuf is still full. ack is not sent. d2 6 ckp (ckp does not reset to ? 0 ? when sen = 0 ) pic18f97j60 family ds39762a-page 274 advance information ? 2006 microchip technology inc. figure 19-9: i 2 c? slave mode timing with sen = 0 and admsk<5:1> = 01011 (reception, 7-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) sspov (sspxcon1<6>) s 12345678912345678912345 789 p a7 a6 a5 x a3 x x d7d6 d5d4d3d2d1 d0 d7d6d5d4d3 d1d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspxbuf is read bus master terminates transfer sspov is set because sspxbuf is still full. ack is not sent. d2 6 ckp (ckp does not reset to ? 0 ? when sen = 0 ) note 1: x = don?t care (i.e., address bit can be either a ? 1 ? or a ? 0 ?). 2: in this example, an address equal to a7.a6.a5.x.a3.x.x will be acknowledged and cause an interrupt. ? 2006 microchip technology inc. advance information ds39762a-page 275 pic18f97j60 family figure 19-10: i 2 c? slave mode timing (transmission, 7-bit address) sdax sclx bf (sspxstat<0>) a6 a5 a4 a3 a2 a1 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 sspxbuf is written in software cleared in software data in sampled s ack transmitting data r/w = 0 ack receiving address a7 d7 9 1 d6 d5 d4 d3 d2 d1 d0 2 3 4 5 6 7 8 9 sspxbuf is written in software cleared in software from sspxif isr transmitting data d7 1 ckp p ack ckp is set in software ckp is set in software sclx held low while cpu responds to sspxif sspxif (pir1<3> or pir3<7>) from sspxif isr pic18f97j60 family ds39762a-page 276 advance information ? 2006 microchip technology inc. figure 19-11: i 2 c? slave mode timing with sen = 0 (reception, 10-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5 a4a3a2a1 a0 d7 d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 cleared in software receive second byte of address cleared by hardware when sspxadd is updated with low byte of address ua (sspxstat<1>) clock is held low until update of sspxadd has taken place ua is set indicating that the sspxadd needs to be updated ua is set indicating that sspxadd needs to be updated cleared by hardware when sspxadd is updated with high byte of address sspxbuf is written with contents of sspxsr dummy read of sspxbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspxcon1<6>) sspov is set because sspxbuf is still full. ack is not sent. (ckp does not reset to ? 0 ? when sen = 0 ) clock is held low until update of sspxadd has taken place ? 2006 microchip technology inc. advance information ds39762a-page 277 pic18f97j60 family figure 19-12: i 2 c? slave mode timing with sen = 0 and admsk<5:1> = 01001 (reception, 10-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9 a8 a7 a6 a5 x a3 a2 x x d7 d6 d5 d4 d3 d1 d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 cleared in software receive second byte of address cleared by hardware when sspxadd is updated with low byte of address ua (sspxstat<1>) clock is held low until update of sspxadd has taken place ua is set indicating that the sspxadd needs to be updated ua is set indicating that sspxadd needs to be updated cleared by hardware when sspxadd is updated with high byte of address sspxbuf is written with contents of sspxsr dummy read of sspxbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspxcon1<6>) sspov is set because sspxbuf is still full. ack is not sent. (ckp does not reset to ? 0 ? when sen = 0 ) clock is held low until update of sspxadd has taken place note 1: x = don?t care (i.e., address bit can be either a ? 1 ? or a ? 0 ?). 2: in this example, an address equal to a9.a8.a7.a6.a5.x .a3.a2.x.x will be acknowledged and cause an interrupt. 3: note that the most significant bits of the address are not affected by the bit masking. pic18f97j60 family ds39762a-page 278 advance information ? 2006 microchip technology inc. figure 19-13: i 2 c? slave mode timing (transmission, 10-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) s 12345 6789 12345678 9 12345 7 89 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 1 1 1 1 0 a8 r/w = 1 ack ack r/w = 0 ack receive first byte of address cleared in software bus master terminates transfer a9 6 receive second byte of address cleared by hardware when sspxadd is updated with low byte of address ua (sspxstat<1>) clock is held low until update of sspxadd has taken place ua is set indicating that the sspxadd needs to be updated ua is set indicating that sspxadd needs to be updated cleared by hardware when sspxadd is updated with high byte of address. sspxbuf is written with contents of sspxsr dummy read of sspxbuf to clear bf flag receive first byte of address 12345 789 d7 d6 d5 d4 d3 d1 ack d2 6 transmitting data byte d0 dummy read of sspxbuf to clear bf flag sr cleared in software write of sspxbuf initiates transmit cleared in software completion of clears bf flag ckp (sspxcon1<4>) ckp is set in software ckp is automatically cleared in hardware, holding sclx low clock is held low until update of sspxadd has taken place data transmission clock is held low until ckp is set to ? 1 ? third address sequence bf flag is clear at the end of the ? 2006 microchip technology inc. advance information ds39762a-page 279 pic18f97j60 family 19.4.4 clock stretching both 7-bit and 10-bit slave modes implement automatic clock stretching during a transmit sequence. the sen bit (sspxcon2<0>) allows clock stretching to be enabled during receives. setting sen will cause the sclx pin to be held low at the end of each data receive sequence. 19.4.4.1 clock stretching for 7-bit slave receive mode (sen = 1 ) in 7-bit slave receive mode, on the falling edge of the ninth clock at the end of the ack sequence, if the bf bit is set, the ckp bit in the sspxcon1 register is automatically cleared, forcing the sclx output to be held low. the ckp being cleared to ? 0 ? will assert the sclx line low. the ckp bit must be set in the user?s isr before reception is allowed to continue. by holding the sclx line low, the user has time to service the isr and read the contents of the sspxbuf before the master device can initiate another receive sequence. this will prevent buffer overruns from occurring (see figure 19-15). 19.4.4.2 clock stretching for 10-bit slave receive mode (sen = 1 ) in 10-bit slave receive mode during the address sequence, clock stretching automatically takes place but ckp is not cleared. during this time, if the ua bit is set after the ninth clock, clock stretching is initiated. the ua bit is set after receiving the upper byte of the 10-bit address and following the receive of the second byte of the 10-bit address with the r/w bit cleared to ? 0 ?. the release of the clock line occurs upon updating sspxadd. clock stretching will occur on each data receive sequence as described in 7-bit mode. 19.4.4.3 clock stretching for 7-bit slave transmit mode the 7-bit slave transmit mode implements clock stretching by clearing the ckp bit after the falling edge of the ninth clock, if the bf bit is clear. this occurs regardless of the state of the sen bit. the user?s isr must set the ckp bit before transmission is allowed to continue. by holding the sclx line low, the user has time to service the isr and load the contents of the sspxbuf before the master device can initiate another transmit sequence (see figure 19-10). 19.4.4.4 clock stretching for 10-bit slave transmit mode in 10-bit slave transmit mode, clock stretching is controlled during the first two address sequences by the state of the ua bit, just as it is in 10-bit slave receive mode. the first two addresses are followed by a third address sequence which contains the high-order bits of the 10-bit address and the r/w bit set to ? 1 ?. after the third address sequence is performed, the ua bit is not set, the module is now configured in transmit mode and clock stretching is controlled by the bf flag as in 7-bit slave transmit mode (see figure 19-13). note 1: if the user reads the contents of the sspxbuf before the falling edge of the ninth clock, thus clearing the bf bit, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regard- less of the state of the bf bit. the user should be careful to clear the bf bit in the isr before the next receive sequence in order to prevent an overflow condition. note: if the user polls the ua bit and clears it by updating the sspxadd register before the falling edge of the ninth clock occurs and if the user hasn?t cleared the bf bit by read- ing the sspxbuf register before that time, then the ckp bit will still not be asserted low. clock stretching on the basis of the state of the bf bit only occurs during a data sequence, not an address sequence. note 1: if the user loads the contents of sspxbuf, setting the bf bit before the falling edge of the ninth clock, the ckp bit will not be cleared and clock stretching will not occur. 2: the ckp bit can be set in software regardless of the state of the bf bit. pic18f97j60 family ds39762a-page 280 advance information ? 2006 microchip technology inc. 19.4.4.5 clock synchronization and the ckp bit when the ckp bit is cleared, the sclx output is forced to ? 0 ?. however, clearing the ckp bit will not assert the sclx output low until the sclx output is already sam- pled low. therefore, the ckp bit will not assert the sclx line until an external i 2 c master device has already asserted the sclx line. the sclx output will remain low until the ckp bit is set and all other devices on the i 2 c bus have deasserted sclx. this ensures that a write to the ckp bit will not violate the minimum high time requirement for sclx (see figure 19-14). figure 19-14: clock synchronization timing sdax sclx dx ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspxcon1 ckp master device deasserts clock master device asserts clock ? 2006 microchip technology inc. advance information ds39762a-page 281 pic18f97j60 family figure 19-15: i 2 c? slave mode timing with sen = 1 (reception, 7-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) sspov (sspxcon1<6>) s 1 234 56789 1 2345 67 89 1 2345 7 89 p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d1 d0 ack receiving data ack receiving data r/w = 0 ack receiving address cleared in software sspxbuf is read bus master terminates transfer sspov is set because sspxbuf is still full. ack is not sent. d2 6 ckp ckp written to ? 1 ? in if bf is cleared prior to the falling edge of the 9th clock, ckp will not be reset to ? 0 ? and no clock stretching will occur software clock is held low until ckp is set to ? 1 ? clock is not held low because buffer full bit is clear prior to falling edge of 9th clock clock is not held low because ack = 1 bf is set after falling edge of the 9th clock, ckp is reset to ? 0 ? and clock stretching occurs pic18f97j60 family ds39762a-page 282 advance information ? 2006 microchip technology inc. figure 19-16: i 2 c? slave mode timing with sen = 1 (reception, 10-bit address) sdax sclx sspxif (pir1<3> or pir3<7>) bf (sspxstat<0>) s 123456789 123456789 12345 789 p 1 1 1 1 0 a9a8 a7 a6a5a4a3a2a1 a0 d7d6d5d4d3 d1d0 receive data byte ack r/w = 0 ack receive first byte of address cleared in software d2 6 cleared in software receive second byte of address cleared by hardware when sspxadd is updated with low byte of address after falling edge ua (sspxstat<1>) clock is held low until update of sspxadd has taken place ua is set indicating that the sspxadd needs to be updated ua is set indicating that sspxadd needs to be updated cleared by hardware when sspxadd is updated with high byte of address after falling edge sspxbuf is written with contents of sspxsr dummy read of sspxbuf to clear bf flag ack ckp 12345 789 d7 d6 d5 d4 d3 d1 d0 receive data byte bus master terminates transfer d2 6 ack cleared in software cleared in software sspov (sspxcon1<6>) ckp written to ? 1 ? note: an update of the sspxadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. note: an update of the sspxadd register before the falling edge of the ninth clock will have no effect on ua and ua will remain set. in software clock is held low until update of sspxadd has taken place of ninth clock of ninth clock sspov is set because sspxbuf is still full. ack is not sent. dummy read of sspxbuf to clear bf flag clock is held low until ckp is set to ? 1 ? clock is not held low because ack = 1 ? 2006 microchip technology inc. advance information ds39762a-page 283 pic18f97j60 family 19.4.5 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually determines which device will be the slave addressed by the master. the exception is the general call address, which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is one of eight addresses reserved for specific purposes by the i 2 c protocol. it consists of all ? 0 ?s with r/w = 0 . the general call address is recognized when the general call enable bit, gcen, is enabled (sspxcon2<7> set). following a start bit detect, 8 bits are shifted into the sspxsr and the address is compared against the sspxadd. it is also compared to the general call address and fixed in hardware. if the general call address matches, the sspxsr is transferred to the sspxbuf, the bf flag bit is set (eighth bit) and on the falling edge of the ninth bit (ack bit), the sspxif interrupt flag bit is set. when the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the sspxbuf. the value can be used to determine if the address was device specific or a general call address. in 10-bit address mode, the sspxadd is required to be updated for the second half of the address to match and the ua bit is set (sspxstat<1>). if the general call address is sampled when the gcen bit is set, while the slave is configured in 10-bit address mode, then the second half of the address is not necessary, the ua bit will not be set and the slave will begin receiving data after the acknowledge (figure 19-17). figure 19-17: slave mode general call address sequence (7 or 10-bit address mode) sdax sclx s sspxif bf (sspxstat<0>) sspov (sspxcon1<6>) cleared in software sspxbuf is read r/w = 0 ack general call address address is compared to general call address gcen (sspxcon2<7>) receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt ? 0 ? ? 1 ? pic18f97j60 family ds39762a-page 284 advance information ? 2006 microchip technology inc. 19.4.6 master mode master mode is enabled by setting and clearing the appropriate sspm bits in sspxcon1 and by setting the sspen bit. in master mode, the sclx and sdax lines are manipulated by the mssp hardware. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle, with both the s and p bits clear. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit conditions. once master mode is enabled, the user has six options. 1. assert a start condition on sdax and sclx. 2. assert a repeated start condition on sdax and sclx. 3. write to the sspxbuf register initiating transmission of data/address. 4. configure the i 2 c port to receive data. 5. generate an acknowledge condition at the end of a received byte of data. 6. generate a stop condition on sdax and sclx. the following events will cause the mssp interrupt flag bit, sspxif, to be set (and mssp interrupt, if enabled): ? start condition ? stop condition ? data transfer byte transmitted/received ? acknowledge transmit ? repeated start figure 19-18: mssp block diagram (i 2 c? master mode) note: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspxbuf register to initiate transmission before the start con- dition is complete. in this case, the sspxbuf will not be written to and the wcol bit will be set, indicating that a write to the sspxbuf did not occur. read write sspxsr start bit, stop bit, sspxbuf internal data bus set/reset s, p, wcol (sspxstat, sspxcon1) shift clock msb lsb sdax acknowledge generate stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv sclx sclx in bus collision sdax in receive enable clock cntl clock arbitrate/wcol detect (hold off clock source) sspxadd<6:0> baud set sspxif, bclxif reset ackstat, pen (sspxcon2) rate generator sspm3:sspm0 start bit detect ? 2006 microchip technology inc. advance information ds39762a-page 285 pic18f97j60 family 19.4.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sdax, while sclx outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate the receive bit. serial data is received via sdax, while sclx outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. the baud rate generator used for the spi mode operation is used to set the sclx clock frequency for either 100 khz, 400 khz or 1 mhz i 2 c operation. see section 19.4.7 ?baud rate? for more detail. a typical transmit sequence would go as follows: 1. the user generates a start condition by setting the start enable bit, sen (sspxcon2<0>). 2. sspxif is set. the mssp module will wait the required start time before any other operation takes place. 3. the user loads the sspxbuf with the slave address to transmit. 4. address is shifted out on the sdax pin until all 8 bits are transmitted. 5. the mssp module shifts in the ack bit from the slave device and writes its value into the sspxcon2 register (sspxcon2<6>). 6. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspxif bit. 7. the user loads the sspxbuf with eight bits of data. 8. data is shifted out on the sdax pin until all 8 bits are transmitted. 9. the mssp module shifts in the ack bit from the slave device and writes its value into the sspxcon2 register (sspxcon2<6>). 10. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspxif bit. 11. the user generates a stop condition by setting the stop enable bit, pen (sspxcon2<2>). 12. interrupt is generated once the stop condition is complete. pic18f97j60 family ds39762a-page 286 advance information ? 2006 microchip technology inc. 19.4.7 baud rate in i 2 c master mode, the baud rate generator (brg) reload value is placed in the lower 7 bits of the sspxadd register (figure 19-19). when a write occurs to sspxbuf, the baud rate generator will automatically begin counting. the brg counts down to 0 and stops until another reload has taken place. the brg count is decremented twice per instruction cycle (t cy ) on the q2 and q4 clocks. in i 2 c master mode, the brg is reloaded automatically. once the given operation is complete (i.e., transmis- sion of the last data bit is followed by ack ), the internal clock will automatically stop counting and the sclx pin will remain in its last state. table 19-3 demonstrates clock rates based on instruction cycles and the brg value loaded into sspxadd. 19.4.7.1 baud rate and module interdependence because mssp1 and mssp2 are independent, they can operate simultaneously in i 2 c master mode at different baud rates. this is done by using different brg reload values for each module. because this mode derives its basic clock source from the system clock, any changes to the clock will affect both modules in the same proportion. it may be possible to change one or both baud rates back to a previous value by changing the brg reload value. figure 19-19: baud rate generator block diagram table 19-3: i 2 c? clock rate w/brg sspm3:sspm0 brg down counter clko f osc /4 sspxadd<6:0> sspm3:sspm0 sclx reload control reload f osc brg value f scl (2 rollovers of brg) 41.667 mhz 19h 400 khz (1) 41.667 mhz 67h 100 khz 31.25 mhz 13h 400 khz (1) 31.25 mhz 4dh 100 khz 20.833 mhz 09h 400 khz (1) 20.833 mhz 33h 100 khz note 1: the i 2 c? interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application. ? 2006 microchip technology inc. advance information ds39762a-page 287 pic18f97j60 family 19.4.7.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, deasserts the sclx pin (sclx allowed to float high). when the sclx pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the sclx pin is actually sampled high. when the sclx pin is sampled high, the baud rate generator is reloaded with the contents of sspxadd<6:0> and begins counting. this ensures that the sclx high time will always be at least one brg rollover count in the event that the clock is held low by an external device (figure 19-20). figure 19-20: baud rate generator timing with clock arbitration sdax sclx sclx deasserted but slave holds dx ? 1 dx brg sclx is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value sclx low (clock arbitration) sclx allowed to transition high brg decrements on q2 and q4 cycles pic18f97j60 family ds39762a-page 288 advance information ? 2006 microchip technology inc. 19.4.8 i 2 c master mode start condition timing to initiate a start condition, the user sets the start enable bit, sen (sspxcon2<0>). if the sdax and sclx pins are sampled high, the baud rate generator is reloaded with the contents of sspxadd<6:0> and starts its count. if sclx and sdax are both sampled high when the baud rate generator times out (t brg ), the sdax pin is driven low. the action of the sdax being driven low while sclx is high is the start condi- tion and causes the s bit (sspxstat<3>) to be set. following this, the baud rate generator is reloaded with the contents of sspxadd<6:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit (sspxcon2<0>) will be auto- matically cleared by hardware. the baud rate generator is suspended, leaving the sdax line held low and the start condition is complete. 19.4.8.1 wcol status flag if the user writes the sspxbuf when a start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 19-21: first start bit timing note: if at the beginning of the start condition, the sdax and sclx pins are already sam- pled low, or if during the start condition, the sclx line is sampled low before the sdax line is driven low, a bus collision occurs. the bus collision interrupt flag, bclxif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. note: because queueing of events is not allowed, writing to the lower 5 bits of sspxcon2 is disabled until the start condition is complete. sdax sclx s t brg 1st bit 2nd bit t brg sdax = 1 , at completion of start bit, sclx = 1 write to sspxbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspxstat<3>) and sets sspxif bit ? 2006 microchip technology inc. advance information ds39762a-page 289 pic18f97j60 family 19.4.9 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit (sspxcon2<1>) is programmed high and the i 2 c logic module is in the idle state. when the rsen bit is set, the sclx pin is asserted low. when the sclx pin is sampled low, the baud rate generator is loaded with the contents of sspxadd<6:0> and begins counting. the sdax pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sdax is sampled high, the sclx pin will be deasserted (brought high). when sclx is sampled high, the baud rate generator is reloaded with the contents of sspxadd<6:0> and begins count- ing. sdax and sclx must be sampled high for one t brg . this action is then followed by assertion of the sdax pin (sdax = 0 ) for one t brg while sclx is high. following this, the rsen bit (sspxcon2<1>) will be automatically cleared and the baud rate generator will not be reloaded, leaving the sdax pin held low. as soon as a start condition is detected on the sdax and sclx pins, the s bit (sspxstat<3>) will be set. the sspxif bit will not be set until the baud rate generator has timed out. immediately following the sspxif bit getting set, the user may write the sspxbuf with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. after the first eight bits are transmitted and an ack is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 19.4.9.1 wcol status flag if the user writes the sspxbuf when a repeated start sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 19-22: repeated start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: ? sdax is sampled low when sclx goes from low-to-high. ? sclx goes low before sdax is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. note: because queueing of events is not allowed, writing of the lower 5 bits of sspxcon2 is disabled until the repeated start condition is complete. sdax sclx sr = repeated start write to sspxcon2 write to sspxbuf occurs here on falling edge of ninth clock, end of xmit at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sdax = 1 , sdax = 1 , sclx (no change) sclx = 1 occurs here: t brg t brg and sets sspxif rsen bit set by hardware t brg pic18f97j60 family ds39762a-page 290 advance information ? 2006 microchip technology inc. 19.4.10 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspxbuf register. this action will set the buffer full flag bit, bf, and allow the baud rate generator to begin counting and start the next trans- mission. each bit of address/data will be shifted out onto the sdax pin after the falling edge of sclx is asserted (see data hold time specification parameter 106). sclx is held low for one baud rate generator rollover count (t brg ). data should be valid before sclx is released high (see data setup time specification parameter 107). when the sclx pin is released high, it is held that way for t brg . the data on the sdax pin must remain stable for that duration and some hold time after the next falling edge of sclx. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sdax. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received properly. the status of ack is written into the ackdt bit on the falling edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared; if not, the bit is set. after the ninth clock, the sspxif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspxbuf, leaving sclx low and sdax unchanged (figure 19-23). after the write to the sspxbuf, each bit of the address will be shifted out on the falling edge of sclx until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will deassert the sdax pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sdax pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit (sspxcon2<6>). following the falling edge of the ninth clock transmission of the address, the sspxif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspxbuf takes place, holding sclx low and allowing sdax to float. 19.4.10.1 bf status flag in transmit mode, the bf bit (sspxstat<0>) is set when the cpu writes to sspxbuf, and is cleared when all 8 bits are shifted out. 19.4.10.2 wcol status flag if the user writes to the sspxbuf when a transmit is already in progress (i.e., sspxsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write doesn?t occur) after 2t cy after the sspxbuf write. if sspxbuf is rewritten within 2 t cy , the wcol bit is set and sspxbuf is updated. this may result in a corrupted transfer. the user should verify that the wcol is clear after each write to sspxbuf to ensure the transfer is correct. in all cases, wcol must be cleared in software. 19.4.10.3 ackstat status flag in transmit mode, the ackstat bit (sspxcon2<6>) is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowl- edge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 19.4.11 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen (sspxcon2<3>). the baud rate generator begins counting and on each rollover. the state of the sclx pin changes (high-to-low/low-to-high) and data is shifted into the sspxsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the con- tents of the sspxsr are loaded into the sspxbuf, the bf flag bit is set, the sspxif flag bit is set and the baud rate generator is suspended from counting, holding sclx low. the mssp is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable bit, acken (sspxcon2<4>). 19.4.11.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspxbuf from sspxsr. it is cleared when the sspxbuf register is read. 19.4.11.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspxsr and the bf flag bit is already set from a previous reception. 19.4.11.3 wcol status flag if the user writes the sspxbuf when a receive is already in progress (i.e., sspxsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). note: the mssp module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded. ? 2006 microchip technology inc. advance information ds39762a-page 291 pic18f97j60 family figure 19-23: i 2 c? master mode waveform (transmission, 7 or 10-bit address) sdax sclx sspxif bf (sspxstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared in software service routine sspxbuf is written in software from mssp interrupt after start condition, sen cleared by hardware s sspxbuf written with 7-bit address and r/w start transmit sclx held low while cpu responds to sspxif sen = 0 of 10-bit address write sspxcon2<0> (sen = 1 ) start condition begins from slave, clear ackstat bit (sspxcon2<6>) ackstat in sspxcon2 = 1 cleared in software sspxbuf written pen r/w cleared in software pic18f97j60 family ds39762a-page 292 advance information ? 2006 microchip technology inc. figure 19-24: i 2 c? master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sdax sclx 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w = 0 transmit address to slave sspxif bf ack is not sent write to sspxcon2<0> (sen = 1 ), write to sspxbuf occurs here, ack from slave master configured as a receiver by programming sspxcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared in software start xmit sen = 0 sspov sdax = 0 , sclx = 1 while cpu (sspxstat<0>) ack cleared in software cleared in software set sspxif interrupt at end of receive set p bit (sspxstat<4>) and sspxif ack from master, set sspxif at end set sspxif interrupt at end of acknowledge sequence set sspxif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sdax = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspxcon2<4> to start acknowledge sequence sdax = ackdt (sspxcon2<5>) = 0 rcen cleared automatically acken begin start condition cleared in software sdax = ackdt = 0 last bit is shifted into sspxsr and contents are unloaded into sspxbuf cleared in software sspov is set because sspxbuf is still full responds to sspxif ? 2006 microchip technology inc. advance information ds39762a-page 293 pic18f97j60 family 19.4.12 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken (sspxcon2<4>). when this bit is set, the sclx pin is pulled low and the contents of the acknowledge data bit are presented on the sdax pin. if the user wishes to generate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the sclx pin is deasserted (pulled high). when the sclx pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the sclx pin is then pulled low. following this, the acken bit is auto- matically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode (figure 19-25). 19.4.12.1 wcol status flag if the user writes the sspxbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write doesn?t occur). 19.4.13 stop condition timing a stop bit is asserted on the sdax pin at the end of a receive/transmit by setting the stop sequence enable bit, pen (sspxcon2<2>). at the end of a receive/transmit, the sclx line is held low after the fall- ing edge of the ninth clock. when the pen bit is set, the master will assert the sdax line low. when the sdax line is sampled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the sclx pin will be brought high and one t brg (baud rate generator rollover count) later, the sdax pin will be deasserted. when the sdax pin is sampled high while sclx is high, the p bit (sspxstat<4>) is set. a t brg later, the pen bit is cleared and the sspxif bit is set (figure 19-26). 19.4.13.1 wcol status flag if the user writes the sspxbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write doesn?t occur). figure 19-25: acknowledge sequence waveform figure 19-26: stop cond ition receive or transmit mode note: t brg = one baud rate generator period. sdax sclx sspxif set at acknowledge sequence starts here, write to sspxcon2 acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 sspxif software sspxif set at the end of acknowledge sequence cleared in software ack sclx sdax sdax asserted low before rising edge of clock write to sspxcon2, set pen falling edge of sclx = 1 for t brg , followed by sdax = 1 for t brg 9th clock sclx brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sdax sampled high. p bit (sspxstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspxcon2<2>) is cleared by hardware and the sspxif bit is set pic18f97j60 family ds39762a-page 294 advance information ? 2006 microchip technology inc. 19.4.14 sleep operation while in sleep mode, the i 2 c module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 19.4.15 effects of a reset a reset disables the mssp module and terminates the current transfer. 19.4.16 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit (sspxstat<4>) is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the mssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sdax line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed in hardware with the result placed in the bclxif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 19.4.17 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sdax pin, arbitration takes place when the master outputs a ? 1 ? on sdax, by letting sdax float high and another master asserts a ? 0 ?. when the sclx pin floats high, data should be stable. if the expected data on sdax is a ? 1 ? and the data sampled on the sdax pin = 0 , then a bus collision has taken place. the master will set the bus collision interrupt flag, bclxif and reset the i 2 c port to its idle state (figure 19-27). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sdax and sclx lines are deasserted and the sspxbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sdax and sclx lines are deasserted and the respective control bits in the sspxcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sdax and sclx pins. if a stop condition occurs, the sspxif bit will be set. a write to the sspxbuf will start the transmission of data at the first data bit regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspxstat register, or the bus is idle and the s and p bits are cleared. figure 19-27: bus collision timing for transmit and acknowledge sdax sclx bclxif sdax released sdax line pulled low by another source sample sdax. while sclx is high, data doesn?t match what is driven bus collision has occurred. set bus collision interrupt (bclxif) by the master. by master data changes while sclx = 0 ? 2006 microchip technology inc. advance information ds39762a-page 295 pic18f97j60 family 19.4.17.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sdax or sclx are sampled low at the beginning of the start condition (figure 19-28). b) sclx is sampled low before sdax is asserted low (figure 19-29). during a start condition, both the sdax and the sclx pins are monitored. if the sdax pin is already low, or the sclx pin is already low, then all of the following occur: ? the start condition is aborted; ? the bclxif flag is set; and ? the mssp module is reset to its idle state (figure 19-28). the start condition begins with the sdax and sclx pins deasserted. when the sdax pin is sampled high, the baud rate generator is loaded from sspxadd<6:0> and counts down to 0. if the sclx pin is sampled low while sdax is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sdax pin is sampled low during this count, the brg is reset and the sdax line is asserted early (figure 19-30). if, however, a ? 1 ? is sampled on the sdax pin, the sdax pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to 0. if the sclx pin is sampled as ? 0 ? during this time, a bus collision does not occur. at the end of the brg count, the sclx pin is asserted low. figure 19-28: bus collision during st art condition (sdax only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sdax before the other. this condition does not cause a bus colli- sion because the two masters must be allowed to arbitrate the first address following the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sdax sclx sen sdax sampled low before sdax goes low before the sen bit is set. s bit and sspxif set because mssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspxif set because set sen, enable start condition if sdax = 1 , sclx = 1 sdax = 0 , sclx = 1 . bclxif s sspxif sdax = 0 , sclx = 1 . sspxif and bclxif are cleared in software sspxif and bclxif are cleared in software set bclxif, start condition. set bclxif. pic18f97j60 family ds39762a-page 296 advance information ? 2006 microchip technology inc. figure 19-29: bus collision d uring start condition (sclx = 0 ) figure 19-30: brg reset due to sdax arbitr ation during start condition sdax sclx sen bus collision occurs. set bclxif. sclx = 0 before sdax = 0 , set sen, enable start sequence if sdax = 1 , sclx = 1 t brg t brg sdax = 0 , sclx = 1 bclxif s sspxif interrupt cleared in software bus collision occurs. set bclxif. sclx = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sdax sclx sen set s less than t brg t brg sdax = 0 , sclx = 1 bclxif s sspxif s interrupts cleared in software set sspxif sdax = 0 , sclx = 1 , sclx pulled low after brg time-out set sspxif ? 0 ? sdax pulled low by other master. reset brg and assert sdax. set sen, enable start sequence if sdax = 1 , sclx = 1 ? 2006 microchip technology inc. advance information ds39762a-page 297 pic18f97j60 family 19.4.17.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sdax when sclx goes from low level to high level. b) sclx goes low before sdax is asserted low, indicating that another master is attempting to transmit a data ? 1 ?. when the user deasserts sdax and the pin is allowed to float high, the brg is loaded with sspxadd<6:0> and counts down to 0. the sclx pin is then deasserted and when sampled high, the sdax pin is sampled. if sdax is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, see figure 19-31). if sdax is sampled high, the brg is reloaded and begins counting. if sdax goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sdax at exactly the same time. if sclx goes from high-to-low before the brg times out and sdax has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition (see figure 19-32). if, at the end of the brg time-out, both sclx and sdax are still high, the sdax pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the sclx pin, the sclx pin is driven low and the repeated start condition is complete. figure 19-31: bus collision during a repeat ed start condition (case 1) figure 19-32: bus collision during repeat ed start condition (case 2) sdax sclx rsen bclxif s sspxif sample sdax when sclx goes high. if sdax = 0 , set bclxif and release sdax and sclx. cleared in software ? 0 ? ? 0 ? sdax sclx bclxif rsen s sspxif interrupt cleared in software sclx goes low before sdax, set bclxif. release sdax and sclx. t brg t brg ? 0 ? pic18f97j60 family ds39762a-page 298 advance information ? 2006 microchip technology inc. 19.4.17.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sdax pin has been deasserted and allowed to float high, sdax is sampled low after the brg has timed out. b) after the sclx pin is deasserted, sclx is sampled low before sdax goes high. the stop condition begins with sdax asserted low. when sdax is sampled low, the sclx pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspxadd<6:0> and counts down to 0. after the brg times out, sdax is sampled. if sdax is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? (figure 19-33). if the sclx pin is sampled low before sdax is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? (figure 19-34). figure 19-33: bus collision during a stop condition (case 1) figure 19-34: bus collision during a stop condition (case 2) sdax sclx bclxif pen p sspxif t brg t brg t brg sdax asserted low sdax sampled low after t brg , set bclxif ? 0 ? ? 0 ? sdax sclx bclxif pen p sspxif t brg t brg t brg assert sdax sclx goes low before sdax goes high, set bclxif ? 0 ? ? 0 ? ? 2006 microchip technology inc. advance information ds39762a-page 299 pic18f97j60 family table 19-4: registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir2 oscfif cmif ethif rbcl1if ? tmr3if ccp2if 61 pie2 oscfie cmie ethie rbcl1ie ? tmr3ie ccp2ie 61 ipr2 oscfip cmip ethip rbcl1ip ? tmr3ip ccp2ip 61 pir3 ssp2if (1) bcl2if (1) rc2if tx2if tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie (1) bcl2ie (1) rc2ie tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 61 ipr3 ssp2ip (1) bcl2ip (1) rc2ip tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 61 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 61 trisd trisd7 trisd6 (1) trisd5 (1) trisd4 trisd3 trisd2 trisd1 trisd0 61 ssp1buf mssp1 receive buffer/transmit register 60 ssp1add mssp1 address register (i 2 c? slave mode), mssp1 baud rate reload register (i 2 c master mode) 63 ssp1con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 60 ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 60 gcen ackstat admsk5 (2) admsk4 (2) admsk3 (2) admsk2 (2) admsk1 (2) sen ssp1stat smp cke d/a psr/w ua bf 60 ssp2buf mssp2 receive buffer/transmit register 60 ssp2add mssp2 address register (i 2 c slave mode), mssp2 baud rate reload register (i 2 c master mode) 63 ssp2con1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 63 ssp2con2 gcen ackstat ackdt acken rcen pen rsen sen 63 gcen ackstat admsk5 (2) admsk4 (2) admsk3 (2) admsk2 (2) admsk1 (2) sen ssp2stat smp cke d/a psr/w ua bf 63 legend: ? = unimplemented, read as ? 0 ?, r = reserved. shaded cells are not used by the mssp module in i 2 c? mode. note 1: these bits are only available in 100-pin devices; otherwise, they are unimplemented and read as ? 0 ?. 2: alternate bit definitions in i 2 c? slave mode. pic18f97j60 family ds39762a-page 300 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 301 pic18f97j60 family 20.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) the enhanced universal synchronous asynchronous receiver transmitter (eusart) module is one of two serial i/o modules. (generically, the eusart is also known as a serial communications interface or sci.) the eusart can be configured as a full-duplex asynchronous system that can communicate with peripheral devices, such as crt terminals and personal computers. it can also be configured as a half-duplex synchronous system that can communicate with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms, etc. the enhanced usart module implements additional features, including automatic baud rate detection and calibration, automatic wake-up on sync break reception and 12-bit break character transmit. these features make it ideally suited for use in local interconnect network bus (lin bus) systems. the 64-pin devices of the pic18f97j60 family are equipped with one eusart module, referred to as eusart1. the 80-pin and 100-pin devices each have two independent eusart modules, referred to as eusart1 and eusart2. they can be configured in the following modes: ? asynchronous (full duplex) with: - auto-wake-up on character reception - auto-baud calibration - 12-bit break character transmission ? synchronous ? master (half duplex) with selectable clock polarity ? synchronous ? slave (half duplex) with selectable clock polarity the pins of eusart1 and eusart2 are multiplexed with the functions of portc (rc6/tx1/ck1 and rc7/rx1/dt1) and portg (rg1/tx2/ck2 and rg2/rx2/dt2), respectively. in order to configure these pins as an eusart: ? for eusart1: - bit spen (rcsta1<7>) must be set (= 1 ) - bit trisc<7> must be set (= 1 ) - bit trisc<6> must be cleared (= 0 ) for asynchronous and synchronous master modes - bit trisc<6> must be set (= 1 ) for synchronous slave mode ? for eusart2: - bit spen (rcsta2<7>) must be set (= 1 ) - bit trisg<2> must be set (= 1 ) - bit trisg<1> must be cleared (= 0 ) for asynchronous and synchronous master modes - bit trisc<6> must be set (= 1 ) for synchronous slave mode the operation of each enhanced usart module is controlled through three registers: ? transmit status and control (txstax) ? receive status and control (rcstax) ? baud rate control (baudconx) these are detailed on the following pages in register 20-1, register 20-2 and register 20-3, respectively. note: the eusartx control will automatically reconfigure the pin from input to output as needed. note: throughout this section, references to register and bit names that may be associ- ated with a specific eusart module are referred to generically by the use of ?x? in place of the specific module number. thus, ?rcstax? might refer to the receive status register for either eusart1 or eusart2. pic18f97j60 family ds39762a-page 302 advance information ? 2006 microchip technology inc. register 20-1: txstax: transmit status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-1 r/w-0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 csrc: clock source select bit asynchronous mode: don?t care. synchronous mode: 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: eusartx mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode: 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode: don?t care. bit 2 brgh: high baud rate select bit asynchronous mode: 1 = high speed 0 = low speed synchronous mode: unused in this mode. bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: 9th bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode. ? 2006 microchip technology inc. advance information ds39762a-page 303 pic18f97j60 family register 20-2: rcstax: receive status and control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r-0 r-0 r-x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 spen: serial port enable bit 1 = serial port enabled (configures rxx/dtx and txx/ckx pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode: don?t care. synchronous mode ? m aster: 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? s lave: don?t care. bit 4 cren: continuous receive enable bit asynchronous mode: 1 = enables receiver 0 = disables receiver synchronous mode: 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit 9-bit asynchronous mode ( rx9 = 1 ): 1 = enables address detection, enables interrupt and loads the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit 9-bit asynchronous mode ( rx9 = 0 ): don?t care. bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcregx register and receiving next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: 9th bit of received data this can be an address/data bit or a parity bit and must be calculated by user firmware. pic18f97j60 family ds39762a-page 304 advance information ? 2006 microchip technology inc. register 20-3: baudconx: baud rate control register r/w-0 r-1 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 abdovf rcidl rxdtp txckp brg16 ? wue abden bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 abdovf : auto-baud acquisition rollover status bit 1 = a brg rollover has occurred during auto-baud rate detect mode (must be cleared in software) 0 = no brg rollover has occurred bit 6 rcidl : receive operation idle status bit 1 = receive operation is idle 0 = receive operation is active bit 5 rxdtp : received data polarity select bit asynchronous mode: 1 = rxx data is inverted 0 = rxx data received is not inverted synchronous modes: 1 = ckx clocks are inverted 0 = ckx clocks are not inverted bit 4 txckp : clock and data polarity select bit asynchronous mode: 1 = txx data is inverted 0 = txx data is not inverted synchronous modes: 1 = ckx clocks are inverted 0 = ckx clocks are not inverted bit 3 brg16: 16-bit baud rate register enable bit 1 = 16-bit baud rate generator ? spbrghx and spbrgx 0 = 8-bit baud rate generator ? spbrgx on ly, spbrghx value ignored (compatible mode) bit 2 unimplemented: read as ? 0 ? bit 1 wue: wake-up enable bit asynchronous mode: 1 = eusartx will continue to sample the rxx pin ? interrupt generated on falling edge; bit cleared in hardware on following rising edge 0 = rxx pin not monitored or rising edge detected synchronous mode: unused in this mode. bit 0 abden : auto-baud detect enable bit asynchronous mode: 1 = enable baud rate measurement on the next character. requires reception of a sync field (55h); cleared in hardware upon completion. 0 = baud rate measurement disabled or completed synchronous mode: unused in this mode. ? 2006 microchip technology inc. advance information ds39762a-page 305 pic18f97j60 family 20.1 baud rate generator (brg) the brg is a dedicated 8-bit or 16-bit generator that supports both the asynchronous and synchronous modes of the eusartx. by default, the brg operates in 8-bit mode; setting the brg16 bit (baudconx<3>) selects 16-bit mode. the spbrghx:spbrgx register pair controls the period of a free-running timer. in asynchronous mode, bits brgh (txstax<2>) and brg16 (baudconx<3>) also control the baud rate. in synchronous mode, brgh is ignored. table 20-1 shows the formula for computation of the baud rate for different eusartx modes which only apply in master mode (internally generated clock). given the desired baud rate and f osc , the nearest integer value for the spbrghx:spbrgx registers can be calculated using the formulas in table 20-1. from this, the error in baud rate can be determined. an example calculation is shown in example 20-1. typical baud rates and error values for the various asynchronous modes are shown in table 20-2. it may be advantageous to use the high baud rate (brgh = 1 ), or the 16-bit brg to reduce the baud rate error, or achieve a slow baud rate for a fast oscillator frequency. writing a new value to the spbrghx:spbrgx regis- ters causes the brg timer to be reset (or cleared). this ensures that the brg does not wait for a timer overflow before outputting the new baud rate. 20.1.1 operation in power-managed modes the device clock is used to generate the desired baud rate. when one of the power-managed modes is entered, the new clock source may be operating at a different frequency. this may require an adjustment to the value in the spbrgx register pair. 20.1.2 sampling the data on the rxx pin (either rc7/rx1/dt1 or rg2/rx2/dt2) is sampled three times by a majority detect circuit to determine if a high or a low level is present at the rxx pin. table 20-1: baud rate formulas configuration bits brg/eusartx mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n + 1)] 001 8-bit/asynchronous f osc /[16 (n + 1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n + 1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = don?t care, n = value of spbrghx:spbrgx register pair pic18f97j60 family ds39762a-page 306 advance information ? 2006 microchip technology inc. example 20-1: calculating baud rate error table 20-2: registers associated with baud rate generator for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: desired baud rate = f osc /(64 ([spbrghx:spbrgx] + 1)) solving for spbrghx:spbrgx: x=((f osc /desired baud rate)/64) ? 1 = ((16000000/9600)/64) ? 1 = [25.042] = 25 calculated baud rate = 16000000/(64 (25 + 1)) = 9615 error = (calculated baud rate ? desi red baud rate)/de sired baud rate = (9615 ? 9600)/9600 = 0.16% name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page txstax csrc tx9 txen sync sendb brgh trmt tx9d 61 rcstax spen rx9 sren cren adden ferr oerr rx9d 61 baudconx abdovf rcidl rxdtp txckp brg16 ? wue abden 62 spbrghx eusartx baud rate generator register high byte 62 spbrgx eusartx baud rate generator register low byte 62 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the brg. ? 2006 microchip technology inc. advance information ds39762a-page 307 pic18f97j60 family table 20-3: baud rates for asynchronous modes baud rate (k) sync = 0 , brg16 = 0 , brgh = 0 f osc = 41.667 mhz f osc = 31.25 mhz f osc = 25.000 mhz f osc = 20.833 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2 ? ? ? ?????? 1.271 5.96 255 2.4 2.543 5.96 255 2.405 0.22 202 2.396 -0.15 162 2.393 -0.27 135 9.6 9.574 -0.27 67 9.574 -0.27 50 9.527 -0.76 40 9.574 -0.27 33 19.2 19.148 -0.27 33 19.531 1.73 24 19.531 1.73 19 19.147 -0.27 16 57.6 59.186 2.75 10 61.035 5.96 7 55.804 -3.12 6 54.253 -5.81 5 115.2 108.508 -5.81 5 122.070 5.96 3 130.208 13.03 2 108.505 -5.81 2 baud rate (k) sync = 0 , brg16 = 0 , brgh = 0 f osc = 13.889 mhz f osc = 6.250 mhz f osc = 4.167 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 ? ? ? ? ? ? 0.300 0.01 216 1.2 1.198 -0.08 180 1.206 0.47 80 1.206 0.48 53 2.4 2.411 0.47 89 2.382 -0.76 40 2.411 0.48 26 9.6 9.435 -1.71 22 9.766 1.73 9 9.301 -3.11 6 19.2 19.279 2.75 10 19.531 1.73 4 21.703 13.04 2 57.6 54.254 -5.81 3 48.828 -15.23 1 65.109 13.04 0 115.2 108.508 -5.81 1 97.656 -15.23 0 65.109 -43.48 0 baud rate (k) sync = 0 , brg16 = 0 , brgh = 1 f osc = 41.667 mhz f osc = 31.25 mhz f osc = 25.000 mhz f osc = 20.833 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3???????????? 1.2???????????? 2.4???????????? 9.6 10.172 5.96 255 9.621 0.22 202 9.586 -0.15 162 9.573 -0.27 135 19.2 19.148 -0.27 135 19.148 -0.27 101 19.290 0.47 80 19.147 -0.27 67 57.6 57.871 0.47 44 57.445 -0.27 33 57.870 0.47 26 56.611 -1.72 22 115.2 113.226 -1.71 22 114.890 -0.27 16 111.607 -3.12 13 118.369 2.75 10 baud rate (k) sync = 0 , brg16 = 0 , brgh = 1 f osc = 13.889 mhz f osc = 6.250 mhz f osc = 4.167 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 ? ? ? ? ? ? ??? 1.2 ? ? ? ? ? ? 1.200 0.01 216 2.4 ? ? ? 2.396 -0.15 162 2.389 -0.44 108 9.6 9.645 0.47 89 9.527 -0.76 40 9.645 0.48 26 19.2 19.290 0.47 44 19.531 1.73 19 18.603 -3.11 13 57.6 57.871 0.47 14 55.804 -3.12 6 52.088 -9.57 4 115.2 108.508 -5.81 7 130.208 13.03 2 130.219 13.04 1 pic18f97j60 family ds39762a-page 308 advance information ? 2006 microchip technology inc. baud rate (k) sync = 0 , brg16 = 1 , brgh = 0 f osc = 41.667 mhz f osc = 31.25 mhz f osc = 25.000 mhz f osc = 20.833 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 8680 0.300 0.00 6509 0.300 0.01 5207 0.300 0.00 4339 1.2 1.200 0.01 2169 1.200 -0.02 1627 1.200 0.01 1301 1.200 0.00 1084 2.4 2.400 0.01 1084 2.399 -0.02 813 2.400 0.01 650 2.398 -0.09 542 9.6 9.609 0.10 270 9.621 0.22 202 9.586 -0.15 162 9.574 -0.27 135 19.2 19.148 -0.27 135 19.148 -0.27 101 19.290 0.47 80 19.148 -0.27 67 57.6 57.871 0.47 44 57.444 -0.27 33 57.870 0.47 26 56.611 -1.72 22 115.2 113.226 -1.71 22 114.890 -0.27 16 111.607 -3.12 13 118.369 2.75 10 baud rate (k) sync = 0 , brg16 = 1 , brgh = 0 f osc = 13.889 mhz f osc = 6.250 mhz f osc = 4.167 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 -0.02 2893 0.300 0.01 1301 0.300 0.01 867 1.2 1.201 0.05 722 1.198 -0.15 325 1.200 0.01 216 2.4 2.398 -0.08 361 2.396 -0.15 162 2.389 -0.44 108 9.6 9.645 0.47 89 9.527 -0.76 40 9.646 0.48 26 19.2 19.290 0.47 44 19.531 1.73 19 18.603 -3.11 13 57.6 57.871 0.47 14 55.804 -3.12 6 52.088 -9.57 4 115.2 108.508 -5.81 7 130.208 13.03 2 130.218 13.04 1 baud rate (k) sync = 0 , brg16 = 1 , brgh = 1 or sync = 1 , brg16 = 1 f osc = 41.667 mhz f osc = 31.25 mhz f osc = 25.000 mhz f osc = 20.833 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 34722 0.300 0.00 26041 0.300 0.00 20832 0.300 0.00 17360 1.2 1.200 0.00 8680 1.200 0.01 6509 1.200 0.01 5207 1.200 0.00 4339 2.4 2.400 0.01 4339 2.400 0.01 3254 2.400 0.01 2603 2.400 0.00 2169 9.6 9.601 0.01 1084 9.598 -0.02 813 9.601 0.01 650 9.592 -0.09 542 19.2 19.184 -0.08 542 19.195 -0.02 406 19.172 -0.15 325 19.219 0.10 270 57.6 57.551 -0.08 180 57.445 -0.27 135 57.339 -0.45 108 57.869 0.47 89 115.2 115.742 0.47 89 114.890 -0.27 67 115.741 0.47 53 115.739 0.47 44 baud rate (k) sync = 0 , brg16 = 1 , brgh = 1 or sync = 1 , brg16 = 1 f osc = 13.889 mhz f osc = 6.250 mhz f osc = 4.167 mhz actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) actual rate (k) % error spbrg value (decimal) 0.3 0.300 0.00 11573 0.300 0.01 5207 0.300 -0.01 3472 1.2 1.200 -0.02 2893 1.200 0.01 1301 1.200 0.01 867 2.4 2.400 -0.02 1446 2.400 0.01 650 2.400 0.01 433 9.6 9.592 -0.08 361 9.586 -0.15 162 9.557 -0.44 108 19.2 19.184 -0.08 180 19.290 0.47 80 19.292 0.48 53 57.6 57.870 0.47 59 57.870 0.47 26 57.875 0.48 17 115.2 115.742 0.47 29 111.607 -3.12 13 115.750 0.48 8 table 20-3: baud rates for asynchronous modes (continued) ? 2006 microchip technology inc. advance information ds39762a-page 309 pic18f97j60 family 20.1.3 auto-baud rate detect the enhanced usartx module supports the automatic detection and calibration of baud rate. this feature is active only in asynchronous mode and while the wue bit is clear. the automatic baud rate measurement sequence (figure 20-1) begins whenever a start bit is received and the abden bit is set. the calculation is self-averaging. in the auto-baud rate detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rxx signal, the rxx signal is timing the brg. in abd mode, the internal baud rate generator is used as a counter to time the bit period of the incoming serial byte stream. once the abden bit is set, the state machine will clear the brg and look for a start bit. the auto-baud rate detect must receive a byte with the value 55h (ascii ?u?, which is also the lin bus sync character) in order to calculate the proper bit rate. the measurement is taken over both a low and high bit time in order to minimize any effects caused by asymmetry of the incoming signal. after a start bit, the spbrgx begins counting up, using the preselected clock source on the first rising edge of rxx. after eight bits on the rxx pin or the fifth rising edge, an accumulated value totalling the proper brg period is left in the spbrghx:spbrgx register pair. once the 5th edge is seen (this should correspond to the stop bit), the abden bit is automatically cleared. if a rollover of the brg occurs (an overflow from ffffh to 0000h), the event is trapped by the abdovf status bit (baudconx<7>). it is set in hardware by brg roll- overs and can be set or cleared by the user in software. abd mode remains active after rollover events and the abden bit remains set (figure 20-2). while calibrating the baud rate period, the brg registers are clocked at 1/8th the preconfigured clock rate. note that the brg clock will be configured by the brg16 and brgh bits. independent of the brg16 bit setting, both the spbrgx and spbrghx will be used as a 16-bit counter. this allows the user to verify that no carry occurred for 8-bit modes by checking for 00h in the spbrghx register. refer to table 20-4 for counter clock rates to the brg. while the abd sequence takes place, the eusartx state machine is held in idle. the rcxif interrupt is set once the fifth rising edge on rxx is detected. the value in the rcregx needs to be read to clear the rcxif interrupt. the contents of rcregx should be discarded. table 20-4: brg counter clock rates 20.1.3.1 abd and eusartx transmission since the brg clock is reversed during abd acquisition, the eusartx transmitter cannot be used during abd. this means that whenever the abden bit is set, txregx cannot be written to. users should also ensure that abden does not become set during a transmit sequence. failing to do this may result in unpredictable eusartx operation. note 1: if the wue bit is set with the abden bit, auto-baud rate detection will occur on the byte following the break character. 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusartx baud rates are not possible due to bit error rates. overall system tim- ing and communication baud rates must be taken into consideration when using the auto-baud rate detection feature. brg16 brgh brg counter clock 00 f osc /512 01 f osc /128 10 f osc /128 11 f osc /32 note: during the abd sequence, spbrgx and spbrghx are both used as a 16-bit counter, independent of brg16 setting. pic18f97j60 family ds39762a-page 310 advance information ? 2006 microchip technology inc. figure 20-1: automatic baud rate calculation figure 20-2: brg overflow sequence brg value rxx pin abden bit rcxif bit bit 0 bit 1 (interrupt) read rcregx brg clock start auto-cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 001ch note: the abd sequence requires the eusartx module to be configured in asynchronous mode and wue = 0 . spbrgx xxxxh 1ch spbrghx xxxxh 00h edge #5 stop bit start bit 0 xxxxh 0000h 0000h ffffh brg clock abden bit rxx pin abdovf bit brg value ? 2006 microchip technology inc. advance information ds39762a-page 311 pic18f97j60 family 20.2 eusartx asynchronous mode the asynchronous mode of operation is selected by clearing the sync bit (txstax<4>). in this mode, the eusartx uses standard non-return-to-zero (nrz) format (one start bit, eight or nine data bits and one stop bit). the most common data format is 8 bits. an on-chip, dedicated 8-bit/16-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. the eusartx transmits and receives the lsb first. the eusartx module?s transmitter and receiver are functionally independent but use the same data format and baud rate. the baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the brgh and brg16 bits (txstax<2> and baudconx<3>). parity is not supported by the hardware but can be implemented in software and stored as the 9th data bit. the txckp (baudconx<4>) and rxdtp (baudconx<5>) bits allow the txx and rxx signals to be inverted (polarity reversed). devices that buffer signals between ttl and rs-232 levels also invert the signal. setting the txckp and rxdtp bits allows for the use of circuits that provide buffering without inverting the signal. when operating in asynchronous mode, the eusartx module consists of the following important elements: ? baud rate generator ? sampling circuit ? asynchronous transmitter ? asynchronous receiver ? auto-wake-up on sync break character ? 12-bit break character transmit ? auto-baud rate detection 20.2.1 eusartx asynchronous transmitter the eusartx transmitter block diagram is shown in figure 20-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txregx. the txregx register is loaded with data in software. the tsr register is not loaded until the stop bit has been transmitted from the previous load. as soon as the stop bit is transmitted, the tsr is loaded with new data from the txregx register (if available). once the txregx register transfers the data to the tsr register (occurs in one t cy ), the txregx register is empty and the txxif flag bit is set. this interrupt can be enabled or disabled by setting or clearing the inter- rupt enable bit, txxie. txxif will be set regardless of the state of txxie; it cannot be cleared in software. txxif is also not cleared immediately upon loading txregx, but becomes valid in the second instruction cycle following the load instruction. polling txxif immediately following a load of txregx will return invalid results. while txxif indicates the status of the txregx regis- ter, another bit, trmt (txstax<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr register is empty. no interrupt logic is tied to this bit so the user has to poll this bit in order to determine if the tsr register is empty. to set up an asynchronous transmission: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if the signal from the txx pin is to be inverted, set the txckp bit. 4. if interrupts are desired, set enable bit txxie. 5. if 9-bit transmission is desired, set transmit bit tx9. can be used as address/data bit. 6. enable the transmission by setting bit txen which will also set bit txxif. 7. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 8. load data to the txregx register (starts transmission). 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. note 1: the tsr register is not mapped in data memory, so it is not available to the user. 2: flag bit, txxif, is set when enable bit txen is set. pic18f97j60 family ds39762a-page 312 advance information ? 2006 microchip technology inc. figure 20-3: eusartx transmit block diagram figure 20-4: asynchronous transmission, txckp = 0 (txx not inverted) figure 20-5: asynchronous transmission (back-to-back), txckp = 0 (txx not inverted) txxif txxie interrupt txen baud rate clk spbrgx baud rate generator tx9d msb lsb data bus txregx register tsr register (8) 0 tx9 trmt spen txx pin pin buffer and control 8 ? ? ? spbrghx brg16 txckp word 1 word 1 transmit shift reg start bit bit 0 bit 1 bit 7/8 write to txregx brg output (shift clock) txx (pin) txxif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy stop bit word 1 transmit shift reg. write to txregx brg output (shift clock) txx (pin) txxif bit (interrupt reg. flag) trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy start bit ? 2006 microchip technology inc. advance information ds39762a-page 313 pic18f97j60 family table 20-5: registers associated with asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir3 ssp2if bcl2if rc2if tx2if (1) tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie bcl2ie rc2ie tx2ie (1) tmr4ie ccp5ie ccp4ie ccp3ie 61 ipr3 ssp2ip bcl2ip rc2ip tx2ip (1) tmr4ip ccp5ip ccp4ip ccp3ip 61 rcstax spen rx9 sren cren adden ferr oerr rx9d 61 txregx eusartx transmit register 61 txstax csrc tx9 txen sync sendb brgh trmt tx9d 61 baudconx abdovf rcidl rxdtp txckp brg16 ? wue abden 62 spbrghx eusartx baud rate generator register high byte 62 spbrgx eusartx baud rate generator register low byte 62 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous transmission. note 1: these bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ? 0 ?. pic18f97j60 family ds39762a-page 314 advance information ? 2006 microchip technology inc. 20.2.2 eusartx asynchronous receiver the receiver block diagram is shown in figure 20-6. the data is received on the rxx pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at f osc . this mode would typically be used in rs-232 systems. the rxdtp bit (baudcon<5>) allows the rxx signal to be inverted (polarity reversed). devices that buffer signals from rs-232 to ttl levels also perform an inver- sion of the signal (when rs-232 = positive, ttl = 0 ). inverting the polarity of the rxx pin data by setting the rxdtp bit allows for the use of circuits that provide buffering without inverting the signal. to set up an asynchronous reception: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing bit sync and setting bit spen. 3. if the signal at the rxx pin is to be inverted, set the rxdtp bit. 4. if interrupts are desired, set enable bit rcxie. 5. if 9-bit reception is desired, set bit rx9. 6. enable the reception by setting bit cren. 7. flag bit, rcxif, will be set when reception is complete and an interrupt will be generated if enable bit, rcxie, was set. 8. read the rcstax register to get the 9th bit (if enabled) and determine if any error occurred during reception. 9. read the 8-bit received data by reading the rcregx register. 10. if any error occurred, clear the error by clearing enable bit cren. 11. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. 20.2.3 setting up 9-bit mode with address detect this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if the signal at the rxx pin is to be inverted, set the rxdtp bit. if the signal from the txx pin is to be inverted, set the txckp bit. 4. if interrupts are required, set the rcen bit and select the desired priority level with the rcxip bit. 5. set the rx9 bit to enable 9-bit reception. 6. set the adden bit to enable address detect. 7. enable reception by setting the cren bit. 8. the rcxif bit will be set when reception is complete. the interrupt will be acknowledged if the rcxie and gie bits are set. 9. read the rcstax register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 10. read rcregx to determine if the device is being addressed. 11. if any error occurred, clear the cren bit. 12. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and interrupt the cpu. ? 2006 microchip technology inc. advance information ds39762a-page 315 pic18f97j60 family figure 20-6: eusartx receive block diagram figure 20-7: asynchronous reception, rxdtp = 0 (rxx not inverted) table 20-6: registers associated with asynchronous receptio n name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir3 ssp2if bcl2if rc2if (1) tx2if tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie bcl2ie rc2ie (1) tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 61 ipr3 ssp2ip bcl2ip rc2ip (1) tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 61 rcstax spen rx9 sren cren adden ferr oerr rx9d 61 rcregx eusartx receive register 61 txstax csrc tx9 txen sync sendb brgh trmt tx9d 61 baudconx abdovf rcidl rxdtp txckp brg16 ? wue abden 62 spbrghx eusartx baud rate generator register high byte 62 spbrgx eusartx baud rate generator register low byte 62 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used for asynchronous reception. note 1: these bits are only available in 80-pin and 100-pin dev ices; otherwise, they are unimplemented and read as ? 0 ?. x64 baud rate clk baud rate generator rxx pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcregx register fifo interrupt rcxif rcxie data bus 8 64 16 or stop start (8) 7 1 0 rx9 ? ? ? spbrgx spbrghx brg16 or 4 rxdtp start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rxx (pin) rcv buffer reg rcv shift reg read rcv buffer reg rcregx rcxif (interrupt flag) oerr bit cren word 1 rcregx word 2 rcregx stop bit note: this timing diagram shows three words appearing on the rxx input. the rcregx (receive buffer) is read after the third word causing the oerr (overrun) bit to be set. pic18f97j60 family ds39762a-page 316 advance information ? 2006 microchip technology inc. 20.2.4 auto-wake-up on sync break character during sleep mode, all clocks to the eusartx are suspended. because of this, the baud rate generator is inactive and a proper byte reception cannot be per- formed. the auto-wake-up feature allows the controller to wake-up due to activity on the rxx/dtx line while the eusartx is operating in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit (baudconx<1>). once set, the typical receive sequence on rxx/dtx is disabled and the eusartx remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event con- sists of a high-to-low transition on the rxx/dtx line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) following a wake-up event, the module generates an rcxif interrupt. the interrupt is generated synchro- nously to the q clocks in normal operating modes (figure 20-8) and asynchronously if the device is in sleep mode (figure 20-9). the interrupt condition is cleared by reading the rcregx register. the wue bit is automatically cleared once a low-to-high transition is observed on the rxx line following the wake-up event. at this point, the eusartx module is in idle mode and returns to normal operation. this signals to the user that the sync break event is over. 20.2.4.1 special considerations using auto-wake-up since auto-wake-up functions by sensing rising edge transitions on rxx/dtx, information with any state changes before the stop bit may signal a false end-of-character and cause data or framing errors. to work properly, therefore, the in itial character in the trans- mission must be all ? 0 ?s. this can be 00h (8 bytes) for standard rs-232 devices or 000h (12 bits) for lin bus. oscillator start-up time must also be considered, especially in applications using oscillators with longer start-up intervals (i.e., hs or hspll mode). the sync break (or wake-up signal) character must be of sufficient length and be followed by a sufficient interval to allow enough time for the selected oscillator to start and provide proper initialization of the eusartx. 20.2.4.2 special considerations using the wue bit the timing of wue and rcxif events may cause some confusion when it comes to determining the validity of received data. as noted, setting the wue bit places the eusartx in an idle mode. the wake-up event causes a receive interrupt by setting the rcxif bit. the wue bit is cleared after this when a rising edge is seen on rxx/dtx. the interrupt condition is then cleared by reading the rcregx register. ordinarily, the data in rcregx will be dummy data and should be discarded. the fact that the wue bit has been cleared (or is still set), and the rcxif flag is set, should not be used as an indicator of the integrity of the data in rcregx. users should consider implementing a parallel method in firmware to verify received data integrity. to assure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode. ? 2006 microchip technology inc. advance information ds39762a-page 317 pic18f97j60 family figure 20-8: auto-wake-up bit (wue) timings during normal operation figure 20-9: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit (1) rxx/dtx line rcxif note 1: the eusartx remains in idle while the wue bit is set. bit set by user cleared due to user read of rcregx auto-cleared q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit (2) rxx/dtx line rcxif cleared due to user read of rcregx sleep command executed note 1: if the wake-up event requires long oscillator warm-up time, the auto-clear of the wue bit can occur before the oscillator is re ady. this sequence should not depend on the presence of q clocks. 2: the eusartx remains in idle while the wue bit is set. sleep ends note 1 auto-cleared bit set by user pic18f97j60 family ds39762a-page 318 advance information ? 2006 microchip technology inc. 20.2.5 break character sequence the eusartx module has the capability of sending the special break character sequences that are required by the lin bus standard. the break character transmit consists of a start bit, followed by twelve ? 0 ? bits and a stop bit. the frame break character is sent whenever the sendb and txen bits (txstax<3> and txstax<5>) are set while the transmit shift register is loaded with data. note that the value of data written to txregx will be ignored and all ? 0 ?s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). note that the data value written to the txregx for the break character is ignored. the write simply serves the purpose of initiating the proper sequence. the trmt bit indicates when the transmit operation is active or idle, just as it does during normal transmis- sion. see figure 20-10 for the timing of the break character sequence. 20.2.5.1 break and sync transmit sequence the following sequence will send a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusartx for the desired mode. 2. set the txen and sendb bits to set up the break character. 3. load the txregx with a dummy character to initiate transmission (the value is ignored). 4. write ?55h? to txregx to load the sync character into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware. the sync character now transmits in the preconfigured mode. when the txregx becomes empty, as indicated by the txxif, the next data byte can be written to txregx. 20.2.6 receiving a break character the enhanced usartx module can receive a break character in two ways. the first method forces configuration of the baud rate at a frequency of 9/13 the typical speed. this allows for the stop bit transition to be at the correct sampling location (13 bits for break versus start bit and 8 data bits for typical data). the second method uses the auto-wake-up feature described in section 20.2.4 ?auto-wake-up on sync break character? . by enabling this feature, the eusartx will sample the next two transitions on rxx/dtx, cause an rcxif interrupt and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud rate detect feature. for both methods, the user can set the abden bit once the txxif interrupt is observed. figure 20-10: send break character sequence write to txregx brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break txxif bit (transmit buffer reg. empty flag) txx (pin) trmt bit (transmit shift reg. empty flag) sendb bit (transmit shift reg. empty flag) sendb sampled here auto-cleared dummy write ? 2006 microchip technology inc. advance information ds39762a-page 319 pic18f97j60 family 20.3 eusartx synchronous master mode the synchronous master mode is entered by setting the csrc bit (txstax<7>). in this mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). when transmitting data, the reception is inhibited and vice versa. synchronous mode is entered by setting bit sync (txstax<4>). in addition, enable bit, spen (rcstax<7>), is set in order to configure the txx and rxx pins to ckx (clock) and dtx (data) lines, respectively. clock polarity (ckx) is selected with the txckp bit (baudcon<4>). setting txckp sets the idle state on ckx as high, while clearing the bit sets the idle state as low. data polarity (dtx) is selected with the rxdtp bit (baudconx<5>). setting rxdtp sets the idle state on dtx as high, while clearing the bit sets the idle state as low. dtx is sampled when ckx returns to its idle state. this option is provided to support microwire devices with this module. 20.3.1 eusartx synchronous master transmission the eusartx transmitter block diagram is shown in figure 20-3. the heart of the transmitter is the transmit (serial) shift register (tsr). the shift register obtains its data from the read/write transmit buffer register, txregx. the txregx register is loaded with data in software. the tsr register is not loaded until the last bit has been transmitted from the previous load. as soon as the last bit is transmitted, the tsr is loaded with new data from the txregx (if available). once the txregx register transfers the data to the tsr register (occurs in one t cy ), the txregx is empty and the txxif flag bit is set. the interrupt can be enabled or disabled by setting or clearing the interrupt enable bit, txxie. txxif is set regardless of the state of enable bit txxie; it cannot be cleared in software. it will reset only when new data is loaded into the txregx register. while flag bit txxif indicates the status of the txregx register, another bit, trmt (txstax<1>), shows the status of the tsr register. trmt is a read-only bit which is set when the tsr is empty. no interrupt logic is tied to this bit, so the user must poll this bit in order to determine if the tsr register is empty. the tsr is not mapped in data memory so it is not available to the user. to set up a synchronous master transmission: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. if the signal from the ckx pin is to be inverted, set the txckp bit. if the signal from the dtx pin is to be inverted, set the rxdtp bit. 4. if interrupts are desired, set enable bit txxie. 5. if 9-bit transmission is desired, set bit tx9. 6. enable the transmission by setting bit txen. 7. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 8. start transmission by loading data to the txregx register. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 20-11: synchronous transmission bit 0 bit 1 bit 7 word 1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bit 2 bit 0 bit 1 bit 7 rc7/rx1/dt1 rc6/tx1/ck1 pin write to txreg1 reg tx1if bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrg1 = 0 , continuous transmission of two 8-bit words. this example is equally applicable to eusart2 (rg1/tx2/ck2 and rg2/rx2/dt2). rc6/tx1/ck1 pin (txckp = 0 ) (txckp = 1 ) pic18f97j60 family ds39762a-page 320 advance information ? 2006 microchip technology inc. figure 20-12: synchronous transmis sion (through txen) table 20-7: registers associated with synchronous master transmission rc7/rx1/dt1 pin rc6/tx1/ck1 pin write to txreg1 reg tx1if bit trmt bit txen bit note: this example is equally applicable to eusart2 (rg1/tx2/ck2 and rg2/rx2/dt2). bit 0 bit 1 bit 2 bit 6 bit 7 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir3 ssp2if bcl2if rc2if tx2if (1) tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie bcl2ie rc2ie tx2ie (1) tmr4ie ccp5ie ccp4ie ccp3ie 61 ipr3 ssp2ip bcl2ip rc2ip tx2ip (1) tmr4ip ccp5ip ccp4ip ccp3ip 61 rcstax spen rx9 sren cren adden ferr oerr rx9d 61 txregx eusartx transmit register 61 txstax csrc tx9 txen sync sendb brgh trmt tx9d 61 baudconx abdovf rcidl rxdtp txckp brg16 ? wue abden 62 spbrghx eusartx baud rate generator register high byte 62 spbrgx eusartx baud rate generator register low byte 62 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission. note 1: these bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ? 0 ?. ? 2006 microchip technology inc. advance information ds39762a-page 321 pic18f97j60 family 20.3.2 eusartx synchronous master reception once synchronous mode is selected, reception is enabled by setting either the single receive enable bit, sren (rcstax<5>), or the continuous receive enable bit, cren (rcstax<4>). data is sampled on the rxx pin on the falling edge of the clock. if enable bit sren is set, only a single word is received. if enable bit cren is set, the reception is continuous until cren is cleared. if both bits are set, then cren takes precedence. to set up a synchronous master reception: 1. initialize the spbrghx:spbrgx registers for the appropriate baud rate. set or clear the brg16 bit, as required, to achieve the desired baud rate. 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. ensure bits cren and sren are clear. 4. if the signal from the ckx pin is to be inverted, set the txckp bit. if the signal from the dtx pin is to be inverted, set the rxdtp bit. 5. if interrupts are desired, set enable bit rcxie. 6. if 9-bit reception is desired, set bit rx9. 7. if a single reception is required, set bit sren. for continuous reception, set bit cren. 8. interrupt flag bit, rcxif, will be set when recep- tion is complete and an interrupt will be generated if the enable bit, rcxie, was set. 9. read the rcstax register to get the 9th bit (if enabled) and determine if any error occurred during reception. 10. read the 8-bit received data by reading the rcregx register. 11. if any error occurred, clear the error by clearing bit cren. 12. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. figure 20-13: synchronous reception (master mode, sren) cren bit rc7/rx1/dt1 rc6/tx1/ck1 pin write to bit sren sren bit rc1if bit (interrupt) read rcreg1 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? q1 q2 q3 q4 note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . this example is equally applicable to eusart2 (rg1/tx2/ck2 and rg2/rx2/dt2). rc6/tx1/ck1 pin pin (txckp = 0 ) (txckp = 1 ) pic18f97j60 family ds39762a-page 322 advance information ? 2006 microchip technology inc. table 20-8: registers associated with synchronous master reception 20.4 eusartx synchronous slave mode synchronous slave mode is entered by clearing bit, csrc (txstax<7>). this mode differs from the synchronous master mode in that the shift clock is sup- plied externally at the ckx pin (instead of being supplied internally in master mode). this allows the device to transfer or receive data while in any low-power mode. 20.4.1 eusartx synchronous slave transmission the operation of the synchronous master and slave modes is identical, except in the case of sleep mode. if two words are written to the txregx and then the sleep instruction is executed, the following will occur: a) the first word will immediately transfer to the tsr register and transmit. b) the second word will remain in the txregx register. c) flag bit, txxif, will not be set. d) when the first word has been shifted out of tsr, the txregx register will transfer the second word to the tsr and flag bit, txxif, will now be set. e) if enable bit txxie is set, the interrupt will wake the chip from sleep. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave transmission: 1. enable the synchronous slave serial port by setting bits sync and spen and clearing bit csrc. 2. clear bits cren and sren. 3. if the signal from the ckx pin is to be inverted, set the txckp bit. if the signal from the dtx pin is to be inverted, set the rxdtp bit. 4. if interrupts are desired, set enable bit txxie. 5. if 9-bit transmission is desired, set bit tx9. 6. enable the transmission by setting enable bit txen. 7. if 9-bit transmission is selected, the ninth bit should be loaded in bit tx9d. 8. start transmission by loading data to the txregx register. 9. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir3 ssp2if bcl2if rc2if (1) tx2if tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie bcl2ie rc2ie (1) tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 61 ipr3 ssp2ip bcl2ip rc2ip (1) tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 61 rcstax spen rx9 sren cren adden ferr oerr rx9d 61 rcregx eusartx receive register 61 txstax csrc tx9 txen sync sendb brgh trmt tx9d 61 baudconx abdovf rcidl rxdtp txckp brg16 ? wue abden 62 spbrghx eusartx baud rate generator register high byte 62 spbrgx eusartx baud rate generator register low byte 62 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception. note 1: these bits are only available in 80-pin and 100-pin dev ices; otherwise, they are unimplemented and read as ? 0 ?. ? 2006 microchip technology inc. advance information ds39762a-page 323 pic18f97j60 family table 20-9: registers associated with synchronous slave transmission 20.4.2 eusartx synchronous slave reception the operation of the synchronous master and slave modes is identical, except in the case of sleep or any idle mode, and bit sren, which is a ?don?t care? in slave mode. if receive is enabled by setting the cren bit prior to entering sleep or any idle mode, then a word may be received while in this low-power mode. once the word is received, the rsr register will transfer the data to the rcregx register; if the rcxie enable bit is set, the interrupt generated will wake the chip from the low-power mode. if the global interrupt is enabled, the program will branch to the interrupt vector. to set up a synchronous slave reception: 1. enable the synchronous master serial port by setting bits sync and spen and clearing bit csrc. 2. if interrupts are desired, set enable bit rcxie. 3. if the signal from the ckx pin is to be inverted, set the txckp bit. if the signal from the dtx pin is to be inverted, set the rxdtp bit. 4. if 9-bit reception is desired, set bit rx9. 5. to enable reception, set enable bit cren. 6. flag bit, rcxif, will be set when reception is complete. an interrupt will be generated if enable bit, rcxie, was set. 7. read the rcstax register to get the 9th bit (if enabled) and determine if any error occurred during reception. 8. read the 8-bit received data by reading the rcregx register. 9. if any error occurred, clear the error by clearing bit cren. 10. if using interrupts, ensure that the gie and peie bits in the intcon register (intcon<7:6>) are set. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir3 ssp2if bcl2if rc2if tx2if (1) tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie bcl2ie rc2ie tx2ie (1) tmr4ie ccp5ie ccp4ie ccp3ie 61 ipr3 ssp2ip bcl2ip rc2ip tx2ip (1) tmr4ip ccp5ip ccp4ip ccp3ip 61 rcstax spen rx9 sren cren adden ferr oerr rx9d 61 txregx eusartx transmit register 61 txstax csrc tx9 txen sync sendb brgh trmt tx9d 61 baudconx abdovf rcidl rxdtp txckp brg16 ? wue abden 62 spbrghx eusartx baud rate generator register high byte 62 spbrgx eusartx baud rate generator register low byte 62 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission. note 1: these bits are only available in 80-pin and 100-pin devices; otherwise, they are unimplemented and read as ? 0 ?. pic18f97j60 family ds39762a-page 324 advance information ? 2006 microchip technology inc. table 20-10: registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir3 ssp2if bcl2if rc2if (1) tx2if tmr4if ccp5if ccp4if ccp3if 61 pie3 ssp2ie bcl2ie rc2ie (1) tx2ie tmr4ie ccp5ie ccp4ie ccp3ie 61 ipr3 ssp2ip bcl2ip rc2ip (1) tx2ip tmr4ip ccp5ip ccp4ip ccp3ip 61 rcstax spen rx9 sren cren adden ferr oerr rx9d 61 rcregx eusartx receive register 61 txstax csrc tx9 txen sync sendb brgh trmt tx9d 61 baudconx abdovf rcidl rxdtp txckp brg16 ? wue abden 62 spbrghx eusartx baud rate generator register high byte 62 spbrgx eusartx baud rate generator register low byte 62 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception. note 1: these bits are only available in 80-pin and 100-pin devic es; otherwise, they are unimplemented and read as ? 0 ?. ? 2006 microchip technology inc. advance information ds39762a-page 325 pic18f97j60 family 21.0 10-bit analog-to-digital converter (a/d) module the analog-to-digital (a/d) converter module has 11 inputs for the 64-pin devices, 15 inputs for the 80-pin devices and 16 inputs for the 100-pin devices. this module allows conversion of an analog input signal to a corresponding 10-bit digital number. the module has five registers: ? a/d result high register (adresh) ? a/d result low register (adresl) ? a/d control register 0 (adcon0) ? a/d control register 1 (adcon1) ? a/d control register 2 (adcon2) the adcon0 register, shown in register 21-1, controls the operation of the a/d module. the adcon1 register, shown in register 21-2, configures the functions of the port pins. the adcon2 register, shown in register 21-3, configures the a/d clock source, programmed acquisition time and justification. register 21-1: adcon0: a/d control register 0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adcal ? chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adcal: a/d calibration bit 1 = calibration is performed on next a/d conversion 0 = normal a/d converter operation (no conversion is performed) bit 6 unimplemented: read as ? 0 ? bit 5-2 chs3:chs0: analog channel select bits 0000 = channel 0 (an0) 0001 = channel 1 (an1) 0010 = channel 2 (an2) 0011 = channel 3 (an3) 0100 = channel 4 (an4) 0101 = channel 5 (an5) (1,3) 0110 = channel 6 (an6) 0111 = channel 7 (an7) 1000 = channel 8 (an8) 1001 = channel 9 (an9) 1010 = channel 10 (an10) 1011 = channel 11 (an11) 1100 = channel 12 (an12) (2,3) 1101 = channel 13 (an13) (2,3) 1110 = channel 14 (an14) (2,3) 1111 = channel 15 (an15) (2,3) bit 1 go/done : a/d conversion status bit when adon = 1 : 1 = a/d conversion in progress 0 = a/d idle bit 0 adon: a/d on bit 1 = a/d converter module is enabled 0 = a/d converter module is disabled note 1: this channel is implemented on 100-pin devices only. 2: these channels are not implemented on 80-pin and 100-pin devices only. 3: performing a conversion on unimplemented channels will return random values. pic18f97j60 family ds39762a-page 326 advance information ? 2006 microchip technology inc. register 21-2: adcon1: a/d control register 1 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? vcfg0 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 vcfg0: voltage reference configuration bit (v ref - source) 1 = v ref - (an2) 0 = av ss bit 4 vcfg0: voltage reference configuration bit (v ref + source) 1 = v ref + (an3) 0 = av dd bit 3-0 pcfg3:pcfg0: a/d port configuration control bits: note 1: an12 through an15 are available in 80-pin and 100-pin devices only. 2: an5 is available in 100-pin devices only. a = analog input d = digital i/o pcfg3: pcfg0 an15 (1) an14 (1) an13 (1) an12 (1) an11 an10 an9 an8 an7 an6 an5 (2) an4 an3 an2 an1 an0 0000 aaaaaa aaaaaaaaaa 0001 ddaaaa aaaaaaaaaa 0010 ddda a aaaaaaaaaaa 0011 dddda aaaaaaaaaaa 0100 ddddda aaaaaaaaaa 0101 dddddd aaaaaaaaaa 0110 ddddddd aaaaaaaaa 0111 ddddddddaaaaaaaa 1000 dddddddddaaaaaaa 1001 dddddd ddddaaaaaa 1010 dddddd dddddaaaaa 1011 dddddd ddddddaaaa 1100 dddddd dddddddaaa 1101 dddddd ddddddddaa 1110 dddddd ddddddddda 1111 dddddd dddddddddd ? 2006 microchip technology inc. advance information ds39762a-page 327 pic18f97j60 family register 21-3: adcon2: a/d control register 2 r/w-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 adfm: a/d result format select bit 1 = right justified 0 = left justified bit 6 unimplemented: read as ? 0 ? bit 5-3 acqt2:acqt0: a/d acquisition time select bits 111 = 20 t ad 110 = 16 t ad 101 = 12 t ad 100 = 8 t ad 011 = 6 t ad 010 = 4 t ad 001 = 2 t ad 000 = 0 t ad (1) bit 2-0 adcs2:adcs0: a/d conversion clock select bits 111 = f rc (clock derived from a/d rc oscillator) (1) 110 = f osc /64 101 = f osc /16 100 = f osc /4 011 = f rc (clock derived from a/d rc oscillator) (1) 010 = f osc /32 001 = f osc /8 000 = f osc /2 note 1: if the a/d f rc clock source is selected, a delay of one t cy (instruction cycle) is added before the a/d clock starts. this allows the sleep instruction to be executed before starting a conversion. pic18f97j60 family ds39762a-page 328 advance information ? 2006 microchip technology inc. the analog reference voltage is software selectable to either the device?s positive and negative supply voltage (av dd and av ss ), or the voltage level on the ra3/an3/v ref + and ra2/an2/v ref - pins. the a/d converter has a unique feature of being able to operate while the device is in sleep mode. to operate in sleep, the a/d conversion clock must be derived from the a/d converter?s internal rc oscillator. the output of the sample and hold is the input into the converter, which generates the result via successive approximation. each port pin associated with the a/d converter can be configured as an analog input or as a digital i/o. the adresh and adresl registers contain the result of the a/d conversion. when the a/d conversion is com- plete, the result is loaded into the adresh:adresl register pair, the go/done bit (adcon0<1>) is cleared and a/d interrupt flag bit, adif, is set. a device reset forces all registers to their reset state. this forces the a/d module to be turned off and any conversion in progress is aborted. the value in the adresh:adresl register pair is not modified for a power-on reset. these registers will contain unknown data after a power-on reset. the block diagram of the a/d module is shown in figure 21-1. figure 21-1: a/d block diagram (input voltage) v ain v ref + reference voltage v dd (3) vcfg1:vcfg0 chs3:chs0 an7 an6 an4 an3 an2 an1 an0 0111 0110 0100 0011 0010 0001 0000 10-bit a/d v ref - v ss (3) converter an15 (1) an14 (1) an13 (1) an12 (1) an11 an10 an9 an8 1111 1110 1101 1100 1011 1010 1001 1000 note 1: channels an15 through an12 are not available on 64-pin devices. 2: channel an5 is implemented on 100-pin devices only. 3: i/o pins have diode protection to v dd and v ss . an5 (2) 0101 ? 2006 microchip technology inc. advance information ds39762a-page 329 pic18f97j60 family after the a/d module has been configured as desired, the selected channel must be acquired before the conversion is started. the analog input channels must have their corresponding tris bits selected as inputs. to determine acquisition time, see section 21.1 ?a/d acquisition requirements? . after this acquisition time has elapsed, the a/d conversion can be started. an acquisition time can be programmed to occur between setting the go/done bit and the actual start of the conversion. the following steps should be followed to do an a/d conversion: 1. configure the a/d module: ? configure analog pins, voltage reference and digital i/o (adcon1) ? select a/d input channel (adcon0) ? select a/d acquisition time (adcon2) ? select a/d conversion clock (adcon2) ? turn on a/d module (adcon0) 2. configure a/d interrupt (if desired): ? clear adif bit ? set adie bit ? set gie bit 3. wait the required acquisition time (if required). 4. start conversion: ? set go/done bit (adcon0<1>) 5. wait for a/d conversion to complete, by either: ? polling for the go/done bit to be cleared or ? waiting for the a/d interrupt 6. read a/d result registers (adresh:adresl); clear bit, adif, if required. 7. for next conversion, go to step 1 or step 2, as required. the a/d conversion time per bit is defined as t ad . a minimum wait of 2 t ad is required before next acquisition starts. figure 21-2: analog input model v ain c pin r s anx 5 pf v dd v t = 0.6v v t = 0.6v i leakage r ic 1k sampling switch ss r ss c hold = 25 pf v ss sampling switch (k ) 123 4 v dd 100 na legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance (from dac) various junctions = sampling switch resistance r ss pic18f97j60 family ds39762a-page 330 advance information ? 2006 microchip technology inc. 21.1 a/d acquisition requirements for the a/d converter to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 21-2. the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ). the source impedance affects the offset voltage at the analog input (due to pin leakage current). the maximum recommended impedance for analog sources is 2.5 k . after the analog input channel is selected (changed), the channel must be sampled for at least the minimum acquisition time before starting a conversion. to calculate the minimum acquisition time, equation 21-1 may be used. this equation assumes that 1/2 lsb error is used (1024 steps for the a/d). the 1/2 lsb error is the maximum error allowed for the a/d to meet its specified resolution. equation 21-3 shows the calculation of the minimum required acquisition time, t acq . this calculation is based on the following application system assumptions: c hold =25 pf rs = 2.5 k conversion error 1/2 lsb v dd =3v rss = 2 k temperature = 85 c (system max.) equation 21-1: acquisition time equation 21-2: a/d minimum charging time equation 21-3: calculating the minimum required acquisition time note: when the conversion is started, the holding capacitor is disconnected from the input pin. t acq = amplifier settling time + holding capacitor charging time + temperature coefficient =t amp + t c + t coff v hold = (v ref ? (v ref /2048)) ? (1 ? e (-t c /c hold (r ic + r ss + r s )) ) or t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) t acq =t amp + t c + t coff t amp =0.2 s t coff = (temp ? 25 c)(0.02 s/ c) (85 c ? 25 c)(0.02 s/ c) 1.2 s temperature coefficient is only required for temperatures > 25 c. below 25 c, t coff = 0 ms. t c = -(c hold )(r ic + r ss + r s ) ln(1/2048) s -(25 pf) (1 k + 2 k + 2.5 k ) ln(0.0004883) s 1.05 s t acq =0.2 s + 1 s + 1.2 s 2.4 s ? 2006 microchip technology inc. advance information ds39762a-page 331 pic18f97j60 family 21.2 selecting and configuring automatic acquisition time the adcon2 register allows the user to select an acquisition time that occurs each time the go/done bit is set. when the go/done bit is set, sampling is stopped and a conversion begins. the user is responsible for ensur- ing the required acquisition time has passed between selecting the desired input channel and setting the go/done bit. this occurs when the acqt2:acqt0 bits (adcon2<5:3>) remain in their reset state (? 000 ?) and is compatible with devices that do not offer programmable acquisition times. if desired, the acqt bits can be set to select a programmable acquisition time for the a/d module. when the go/done bit is set, the a/d module continues to sample the input for the selected acquisition time, then automatically begins a conversion. since the acquisition time is programmed, there may be no need to wait for an acquisition time between selecting a channel and setting the go/done bit. in either case, when the conversion is completed, the go/done bit is cleared, the adif flag is set and the a/d begins sampling the currently selected channel again. if an acquisition time is programmed, there is nothing to indicate if the acquisition time has ended or if the conversion has begun. 21.3 selecting the a/d conversion clock the a/d conversion time per bit is defined as t ad . the a/d conversion requires 11 t ad per 10-bit conversion. the source of the a/d conversion clock is software selectable. there are seven possible options for t ad : ?2 t osc ?4 t osc ?8 t osc ?16 t osc ?32 t osc ?64 t osc ? internal rc oscillator for correct a/d conversions, the a/d conversion clock (t ad ) must be as short as possible but greater than the minimum t ad . see a/d parameter 130, table 27-27 ( ?a/d conversion requirements? ) for more information. table 21-1 shows the resultant t ad times derived from the device operating frequencies and the a/d clock source selected. table 21-1: t ad vs. device operating frequencies 21.4 configuring analog port pins the adcon1, trisa, trisf and trish registers control the operation of the a/d port pins. the port pins needed as analog inputs must have their correspond- ing tris bits set (input). if the tris bit is cleared (output), the digital output level (v oh or v ol ) will be converted. the a/d operation is independent of the state of the chs3:chs0 bits and the tris bits. ad clock source (t ad )maximum device frequency operation adcs2:adcs0 2 t osc 000 2.68 mhz 4 t osc 100 5.71 mhz 8 t osc 001 11.43 mhz 16 t osc 101 22.86 mhz 32 t osc 010 41.67 mhz 64 t osc 110 41.67 mhz rc (2) x11 1.00 mhz (1) note 1: the rc source has a typical t ad time of 4ms. 2: see parameter 130 in table 27-27 for a/d rc clock specifications. note 1: when reading the port register, all pins configured as analog input channels will read as cleared (a low level). pins config- ured as digital inputs will convert an analog input. analog levels on a digitally configured input will be accurately converted. 2: analog levels on any pin defined as a digital input may cause the digital input buffer to consume current out of the device?s specification limits. pic18f97j60 family ds39762a-page 332 advance information ? 2006 microchip technology inc. 21.5 a/d conversions figure 21-3 shows the operation of the a/d converter after the go/done bit has been set and the acqt2:acqt0 bits are cleared. a conversion is started after the following instruction to allow entry into sleep mode before the conversion begins. figure 21-4 shows the operation of the a/d converter after the go/done bit has been set, the acqt2:acqt0 bits are set to ? 010 ? and a 4 t ad acquisition time has been selected before the conversion starts. clearing the go/done bit during a conversion will abort the current conversion. the a/d result register pair will not be updated with the partially completed a/d conversion sample. this means the adresh:adresl registers will continue to contain the value of the last completed conversion (or the last value written to the adresh:adresl registers). after the a/d conversion is completed or aborted, a 2t ad wait is required before the next acquisition can be started. after this wait, acquisition on the selected channel is automatically started. 21.6 use of the eccp2 trigger an a/d conversion can be started by the ?special event trigger? of the eccp2 module. this requires that the ccp2m3:ccp2m0 bits (ccp2con<3:0>) be programmed as ? 1011 ? and that the a/d module is enabled (adon bit is set). when the trigger occurs, the go/done bit will be set, starting the a/d acquisition and conversion and the timer1 (or timer3) counter will be reset to zero. timer1 (or timer3) is reset to auto- matically repeat the a/d acquisition period with minimal software overhead (moving adresh/adresl to the desired location). the appropriate analog input channel must be selected and the minimum acquisition period is either timed by the user, or an appropriate t acq time is selected before the special event trigger sets the go/done bit (starts a conversion). if the a/d module is not enabled (adon is cleared), the special event trigger will be ignored by the a/d module but will still reset the timer1 (or timer3) counter. figure 21-3: a/d conversion t ad cycles (acqt2:acqt0 = 000 , t acq = 0 ) figure 21-4: a/d conversion t ad cycles (acqt2:acqt0 = 010 , t acq = 4 t ad ) note: the go/done bit should not be set in the same instruction that turns on the a/d. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad next q4: adresh/adresl is loaded, go/done bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 1 2 3 4 5 6 7 8 11 set go/done bit (holding capacitor is disconnected) 9 10 next q4: adresh:adresl is loaded, go/done bit is cleared, adif bit is set, holding capacitor is reconnected to analog input. conversion starts 1 2 3 4 (holding capacitor continues acquiring input) t acqt cycles t ad cycles automatic acquisition time b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 ? 2006 microchip technology inc. advance information ds39762a-page 333 pic18f97j60 family 21.7 a/d converter calibration the a/d converter in the pic18f97j60 family of devices includes a self-calibration feature which com- pensates for any offset generated within the module. the calibration process is automated and is initiated by setting the adcal bit (adcon0<7>). the next time the go/done bit is set, the module will perform a ?dummy? conversion (that is, with reading none of the input channels) and store the resulting value internally to compensate for offset. thus, subsequent offsets will be compensated. the calibration process assumes that the device is in a relatively steady-state operating condition. if a/d calibration is used, it should be performed after each device reset, or if there are other major changes in operating conditions. 21.8 operation in power-managed modes the selection of the automatic acquisition time and a/d conversion clock is determined in part by the clock source and frequency while in a power-managed mode. if the a/d is expected to operate while the device is in a power-managed mode, the acqt2:acqt0 and adcs2:adcs0 bits in adcon2 should be updated in accordance with the power-managed mode clock that will be used. after the power-managed mode is entered (either of the power-managed run modes), an a/d acquisition or conversion may be started. once an acquisition or conversion is started, the device should continue to be clocked by the same power-managed mode clock source until the conversion has been completed. if desired, the device may be placed into the corresponding power-managed idle mode during the conversion. if the power-managed mode clock frequency is less than 1 mhz, the a/d rc clock source should be selected. operation in sleep mode requires the a/d rc clock to be selected. if bits acqt2:acqt0 are set to ? 000 ? and a conversion is started, the conversion will be delayed one instruction cycle to allow execution of the sleep instruction and entry to sleep mode. the idlen and scs bits in the osccon register must have already been cleared prior to starting the conversion. table 21-2: summary of a/d registers name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir1 pspif adif rc1if tx1if ssp1if ccp1if tmr2if tmr1if 61 pie1 pspie adie rc1ie tx1ie ssp1ie ccp1ie tmr2ie tmr1ie 61 ipr1 pspip adip rc1ip tx1ip ssp1ip ccp1ip tmr2ip tmr1ip 61 pir2 oscfif cmif ethif r bcl1if ? tmr3if ccp2if 61 pie2 oscfie cmie ethie r bcl1ie ? tmr3ie ccp2ie 61 ipr2 oscfip cmip ethip r bcl1ip ? tmr3ip ccp2ip 61 adresh a/d result register high byte 60 adresl a/d result register low byte 60 adcon0 adcal ? chs3 chs3 chs1 chs0 go/done adon 60 adcon1 ? ? vcfg1 vcfg0 pcfg3 pcfg2 pcfg1 pcfg0 60 adcon2 adfm ? acqt2 acqt1 acqt0 adcs2 adcs1 adcs0 60 ccp2con p2m1 p2m0 dc2b1 dc2b0 ccp2m3 ccp2m2 ccp2m1 ccp2m0 60 porta rjpu ? ra5 ra4 ra3 ra2 ra1 ra0 62 trisa ? ? trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 61 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 (1) 62 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 (1) 61 porth (2) rh7 rh6 rh5 rh4 rh3 rh2 rh1 rh0 62 trish (2) trish7 trish6 trish5 trish4 trish3 trish2 trish1 trish0 61 legend: ? = unimplemented, read as ? 0 ?, r = reserved. shaded cells are not used for a/d conversion. note 1: implemented on 100-pin devices only. 2: this register is not implemented on 64-pin devices. pic18f97j60 family ds39762a-page 334 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 335 pic18f97j60 family 22.0 comparator module the analog comparator module contains two comparators that can be configured in a variety of ways. the inputs can be selected from the analog inputs multiplexed with pins rf1 through rf6, as well as the on-chip voltage reference (see section 23.0 ?comparator voltage reference module? ). the digi- tal outputs (normal or inverted) are available at the pin level and can also be read through the control register. the cmcon register (register 22-1) selects the comparator input and output configuration. block diagrams of the various comparator configurations are shown in figure 22-1. register 22-1: cmcon: co mparator control register r-0 r-0 r/w-0 r/w-0 r/w-0 r/w-1 r/w-1 r/w-1 c2out c1out c2inv c1inv cis cm2 cm1 cm0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 c2out : comparator 2 output bit when c2inv = 0 : 1 = c2 v in + > c2 v in - 0 = c2 v in + < c2 v in - when c2inv = 1 : 1 = c2 v in + < c2 v in - 0 = c2 v in + > c2 v in - bit 6 c1out : comparator 1 output bit when c1inv = 0 : 1 = c1 v in + > c1 v in - 0 = c1 v in + < c1 v in - when c1inv = 1 : 1 = c1 v in + < c1 v in - 0 = c1 v in + > c1 v in - bit 5 c2inv : comparator 2 output inversion bit 1 = c2 output inverted 0 = c2 output not inverted bit 4 c1inv : comparator 1 output inversion bit 1 = c1 output inverted 0 = c1 output not inverted bit 3 cis : comparator input switch bit when cm2:cm0 = 110 : 1 =c1 v in - connects to rf5/an10/cv ref c2 v in - connects to rf3/an8 0 =c1 v in - connects to rf6/an11 c2 v in - connects to ra4/an9 bit 2-0 cm2:cm0 : comparator mode bits figure 22-1 shows the comparator modes and the cm2:cm0 bit settings. pic18f97j60 family ds39762a-page 336 advance information ? 2006 microchip technology inc. 22.1 comparator configuration there are eight modes of operation for the compara- tors, shown in figure 22-1. bits cm2:cm0 of the cmcon register are used to select these modes. the trisf register controls the data direction of the comparator pins for each mode. if the comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in section 27.0 ?electrical characteristics? . figure 22-1: comparator i/o operating modes note: comparator interrupts should be disabled during a comparator mode change; otherwise, a false interrupt may occur. c1 v in - v in + off (read as ? 0 ?) comparator outputs disabled a a cm2:cm0 = 000 c2 v in - v in + off (read as ? 0 ?) a a c1 v in - v in + c1out two independent comparators a a cm2:cm0 = 010 c2 v in - v in + c2out a a c1 v in - v in + c1out two common reference comparators a a cm2:cm0 = 100 c2 v in - v in + c2out a d c2 v in - v in + off (read as ? 0 ?) one independent comparator with output d d cm2:cm0 = 001 c1 v in - v in + c1out a a c1 v in - v in + off (read as ? 0 ?) comparators off (por default value) d d cm2:cm0 = 111 c2 v in - v in + off (read as ? 0 ?) d d c1 v in - v in + c1out four inputs multiplexed to two comparators a a cm2:cm0 = 110 c2 v in - v in + c2out a a from v ref module cis = 0 cis = 1 cis = 0 cis = 1 c1 v in - v in + c1out two common reference comparators with outputs a a cm2:cm0 = 101 c2 v in - v in + c2out a d a = analog input, port reads zeros always d = digital input cis (cmcon<3>) is the comparator input switch cv ref c1 v in - v in + c1out two independent comparators with outputs a a cm2:cm0 = 011 c2 v in - v in + c2out a a rf1/an6/c2out* rf2/an7/c1out* * setting the trisf<2:1> bits will disable the comparator outputs by configuring the pins as inputs. rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf2/an7/c1out* rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf1/an6/c2out* rf2/an7/c1out* rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref rf6/an11 rf5/an10/ rf4/an9 rf3/an8 cv ref ? 2006 microchip technology inc. advance information ds39762a-page 337 pic18f97j60 family 22.2 comparator operation a single comparator is shown in figure 22-2, along with the relationship between the analog input levels and the digital output. when the analog input at v in + is less than the analog input v in -, the output of the comparator is a digital low level. when the analog input at v in + is greater than the analog input v in -, the output of the comparator is a digital high level. the shaded areas of the output of the comparator in figure 22-2 represent the uncertainty due to input offsets and response time. 22.3 comparator reference depending on the comparator operating mode, either an external or internal voltage reference may be used. the analog signal present at v in - is compared to the signal at v in + and the digital output of the comparator is adjusted accordingly (figure 22-2). figure 22-2: single comparator 22.3.1 external reference signal when external voltage references are used, the comparator module can be configured to have the com- parators operate from the same or different reference sources. however, threshold detector applications may require the same reference. the reference signal must be between v ss and v dd and can be applied to either pin of the comparator(s). 22.3.2 internal reference signal the comparator module also allows the selection of an internally generated voltage reference from the comparator voltage reference module. this module is described in more detail in section 23.0 ?comparator voltage reference module? . the internal reference is only available in the mode where four inputs are multiplexed to two comparators (cm2:cm0 = 110 ). in this mode, the internal voltage reference is applied to the v in + pin of both comparators. 22.4 comparator response time response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. if the internal ref- erence is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. otherwise, the maximum delay of the comparators should be used (see section 27.0 ?electrical characteristics? ). 22.5 comparator outputs the comparator outputs are read through the cmcon register. these bits are read-only. the comparator outputs may also be directly output to the rf1 and rf2 i/o pins. when enabled, multiplexors in the output path of the rf1 and rf2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. the uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. figure 22-3 shows the comparator output block diagram. the trisf bits will still function as an output enable/ disable for the rf1 and rf2 pins while in this mode. the polarity of the comparator outputs can be changed using the c2inv and c1inv bits (cmcon<5:4>). ? + v in + v in - output output v in - v in + note 1: when reading the port register, all pins configured as analog inputs will read as ? 0 ?. pins configured as digital inputs will convert an analog input according to the schmitt trigger input specification. 2: analog levels on any pin defined as a digital input may cause the input buffer to consume more current than is specified. pic18f97j60 family ds39762a-page 338 advance information ? 2006 microchip technology inc. figure 22-3: comparator output block diagram 22.6 comparator interrupts the comparator interrupt flag is set whenever there is a change in the output value of either comparator. software will need to maintain information about the status of the output bits, as read from cmcon<7:6>, to determine the actual change that occurred. the cmif bit (pir2<6>) is the comparator interrupt flag. the cmif bit must be reset by clearing it. since it is also possible to write a ? 1 ? to this register, a simulated interrupt may be initiated. both the cmie bit (pie2<6>) and the peie bit (intcon<6>) must be set to enable the interrupt. in addition, the gie bit (intcon<7>) must also be set. if any of these bits are clear, the interrupt is not enabled, though the cmif bit will still be set if an interrupt condition occurs. the user, in the interrupt service routine, can clear the interrupt in the following manner: a) any read or write of cmcon will end the mismatch condition. b) clear flag bit cmif. a mismatch condition will continue to set flag bit cmif. reading cmcon will end the mismatch condition and allow flag bit cmif to be cleared. 22.7 comparator operation during sleep when a comparator is active and the device is placed in sleep mode, the comparator remains active and the interrupt is functional, if enabled. this interrupt will wake-up the device from sleep mode, when enabled. each operational comparator will consume additional current, as shown in the comparator specifications. to minimize power consumption while in sleep mode, turn off the comparators (cm2:cm0 = 111 ) before entering sleep. if the device wakes up from sleep, the contents of the cmcon register are not affected. 22.8 effects of a reset a device reset forces the cmcon register to its reset state, causing the comparator modules to be turned off (cm2:cm0 = 111) . however, the input pins (rf3 through rf6) are configured as analog inputs by default on device reset. the i/o configuration for these pins is determined by the setting of the pcfg3:pcfg0 bits (adcon1<3:0>). therefore, device current is minimized when analog inputs are present at reset time. dq en to r f 1 o r rf2 pin bus data set multiplex cmif bit -+ port pins read cmcon reset from other comparator cxinv dq en cl note: if a change in the cmcon register (c1out or c2out) should occur when a read operation is being executed (start of the q2 cycle), then the cmif (pir2 register) interrupt flag may not get set. ? 2006 microchip technology inc. advance information ds39762a-page 339 pic18f97j60 family 22.9 analog input connection considerations a simplified circuit for an analog input is shown in figure 22-4. since the analog pins are connected to a digital output, they have reverse biased diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is forward biased and a latch-up condition may occur. a maximum source impedance of 10 k is recommended for the analog sources. any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current. figure 22-4: comparator analog input model table 22-1: registers associated with comparator module va r s < 10k a in c pin 5 pf v dd v t = 0.6v v t = 0.6v r ic i leakage 500 na v ss legend: c pin = input capacitance v t = threshold voltage i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance va = analog voltage comparator input name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie/gieh peie/giel tmr0ie int0ie rbie tmr0if int0if rbif 59 pir2 oscfif cmif ethif r bcl1if ? tmr3if ccp2if 61 pie2 oscfie cmie ethie r bcl1ie ? tmr3ie ccp2ie 61 ipr2 oscfip cmip ethip r bcl1ip ? tmr3ip ccp2ip 61 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 60 cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 60 portf rf7 rf6 rf5 rf4 rf3 rf2 rf1 rf0 62 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 61 legend: ? = unimplemented, read as ? 0 ?, r = reserved. shaded cells are unused by the comparator module. pic18f97j60 family ds39762a-page 340 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 341 pic18f97j60 family 23.0 comparator voltage reference module the comparator voltage reference is a 16-tap resistor ladder network that provides a selectable reference voltage. although its primary purpose is to provide a reference for the analog comparators, it may also be used independently of them. a block diagram of the module is shown in figure 23-1. the resistor ladder is segmented to provide two ranges of cv ref values and has a power-down function to conserve power when the reference is not being used. the module?s supply reference can be provided from either device v dd /v ss or an external voltage reference. 23.1 configuring the comparator voltage reference the voltage reference module is controlled through the cvrcon register (register 23-1). the comparator voltage reference provides two ranges of output volt- age, each with 16 distinct levels. the range to be used is selected by the cvrr bit (cvrcon<5>). the primary difference between the ranges is the size of the steps selected by the cv ref selection bits (cvr3:cvr0), with one range offering finer resolution. the equations used to calculate the output of the comparator voltage reference are as follows: if cvrr = 1 : cv ref = ((cvr3:cvr0)/24) x (cv rsrc ) if cvrr = 0 : cv ref =(cv rsrc /4) + ((cvr3:cvr0)/32) x (cv rsrc ) the comparator reference supply voltage can come from either v dd and v ss , or the external v ref + and v ref - that are multiplexed with ra2 and ra3. the voltage source is selected by the cvrss bit (cvrcon<4>). the settling time of the comparator voltage reference must be considered when changing the cv ref output (see table 27-3 in section 27.0 ?electrical characteristics? ). register 23-1: cvrcon: comparator vo ltage reference control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 cvren cvroe (1) cvrr cvrss cvr3 cvr2 cvr1 cvr0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 cvren : comparator voltage reference enable bit 1 =cv ref circuit powered on 0 =cv ref circuit powered down bit 6 cvroe : comparator v ref output enable bit (1) 1 =cv ref voltage level is also output on the rf5/an10/cv ref pin 0 =cv ref voltage is disconnected from the rf5/an10/cv ref pin bit 5 cvrr : comparator v ref range selection bit 1 = 0 to 0.667 cv rsrc , with cv rsrc /24 step size (low range) 0 = 0.25 cv rsrc to 0.75 cv rsrc , with cv rsrc /32 step size (high range) bit 4 cvrss : comparator v ref source selection bit 1 = comparator reference source, cv rsrc = (v ref +) ? (v ref -) 0 = comparator reference source, cv rsrc = v dd ? v ss bit 3-0 cvr3:cvr0: comparator v ref value selection bits (0 (cvr3:cvr0) 15) when cvrr = 1 : cv ref = ((cvr3:cvr0)/24) ? (cv rsrc ) when cvrr = 0 : cv ref = (cv rsrc /4) + ((cvr3:cvr0)/32) ? (cv rsrc ) note 1: cvroe overrides the trisf<5> bit setting. pic18f97j60 family ds39762a-page 342 advance information ? 2006 microchip technology inc. figure 23-1: comparator voltage reference block diagram 23.2 voltage reference accuracy/error the full range of voltage reference cannot be realized due to the construction of the module. the transistors on the top and bottom of the resistor ladder network (figure 23-1) keep cv ref from approaching the refer- ence source rails. the voltage reference is derived from the reference source; therefore, the cv ref output changes with fluctuations in that source. the tested absolute accuracy of the voltage reference can be found in section 27.0 ?electrical characteristics? . 23.3 operation during sleep when the device wakes up from sleep through an interrupt, or a watchdog timer time-out, the contents of the cvrcon register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 23.4 effects of a reset a device reset disables the voltage reference by clearing bit, cvren (cvrcon<7>). this reset also disconnects the reference from the ra2 pin by clearing bit, cvroe (cvrcon<6>), and selects the high- voltage range by clearing bit, cvrr (cvrcon<5>). the cvr value select bits are also cleared. 23.5 connection considerations the voltage reference module operates independently of the comparator module. the output of the reference generator may be connected to the rf5 pin if the cvroe bit is set. enabling the voltage reference out- put onto ra2 when it is configured as a digital input will increase current consumption. connecting rf5 as a digital output with cvrss enabled will also increase current consumption. the rf5 pin can be used as a simple d/a output with limited drive capability. due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to v ref . figure 23-2 shows an example buffering technique. 16-to-1 mux cvr3:cvr0 8r r cvren cvrss = 0 v dd v ref + cvrss = 1 8r cvrss = 0 v ref - cvrss = 1 r r r r r r 16 steps cvrr cv ref ? 2006 microchip technology inc. advance information ds39762a-page 343 pic18f97j60 family figure 23-2: comparator voltage reference output buffer example table 23-1: registers associated with comparator voltage reference cv ref output + ? cv ref module voltage reference output impedance r (1) rf5 note 1: r is dependent upon the voltage reference configuration bits, cvrcon<5> and cvrcon<3:0>. pic18fxxj6x name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page cvrcon cvren cvroe cvrr cvrss cvr3 cvr2 cvr1 cvr0 60 cmcon c2out c1out c2inv c1inv cis cm2 cm1 cm0 60 trisf trisf7 trisf6 trisf5 trisf4 trisf3 trisf2 trisf1 trisf0 61 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used with the comparator voltage reference. pic18f97j60 family ds39762a-page 344 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 345 pic18f97j60 family 24.0 special features of the cpu pic18f97j60 family devices include several features intended to maximize reliability and minimize cost through elimination of external components. these are: ? oscillator selection ? resets: - power-on reset (por) - power-up timer (pwrt) - oscillator start-up timer (ost) - brown-out reset (bor) ? interrupts ? watchdog timer (wdt) ? fail-safe clock monitor ? two-speed start-up ? code protection ? in-circuit serial programming the oscillator can be configured for the application depending on frequency, power, accuracy and cost. all of the options are discussed in detail in section 2.0 ?oscillator configurations? . a complete discussion of device resets and interrupts is available in previous sections of this data sheet. in addition to their power-up and oscillator start-up timers provided for resets, the pic18f97j60 family of devices has a configurable watchdog timer which is controlled in software. the inclusion of an internal rc oscillator also provides the additional benefits of a fail-safe clock monitor (fscm) and two-speed start-up. fscm provides for background monitoring of the peripheral clock and automatic switchover in the event of its failure. two-speed start-up enables code to be executed almost immediately on start-up, while the primary clock source completes its start-up delays. all of these features are enabled and configured by setting the appropriate configuration register bits. 24.1 configuration bits the configuration bits can be programmed (read as ? 0 ?) or left unprogrammed (read as ? 1 ?) to select various device configurations. these bits are mapped starting at program memory location 300000h. a complete list is shown in table 24-1. a detailed explanation of the various bit functions is provided in register 24-1 through register 24-8. 24.1.1 considerations for configuring the pic18f97j60 family devices devices of the pic18f97j60 family do not use persis- tent memory registers to store configuration informa- tion. the configuration bytes are implemented as volatile memory which means that configuration data must be programmed each time the device is powered up. configuration data is stored in the four words at the top of the on-chip program memory space, known as the flash configuration words, which are located in the program memory space as shown in table 5-1. the configuration words are stored in the same order shown in table 24-1, with config1l at the lowest address and config3h at the highest. the data is automatically loaded in the proper configuration registers during device power-up. when creating applications for these devices, users should always specifically allocate the location of the flash configuration word for configuration data. this is to make certain that program code is not stored in this address when the code is compiled. the volatile memory cells used for the configuration bits always reset to ? 1 ? on power-on resets. for all other type of reset events, the previously programmed values are maintained and used without reloading from program memory. the four most significant bits of config1h, config2h and config3h in program memory should also be ? 1111 ?. this makes these configuration words appear to be nop instructions in the remote event that their locations are ever executed by accident. since configuration bits are not implemented in the corresponding locations, writing ? 1 ?s to these locations has no effect on device operation. to prevent inadvertent configuration changes during code execution, all programmable configuration bits are write-once. after a bit is initially programmed during a power cycle, it cannot be written to again. changing a device configuration requires that power to the device be cycled. pic18f97j60 family ds39762a-page 346 advance information ? 2006 microchip technology inc. table 24-1: configuration bits and device ids file name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default/ unprogrammed value (1) 300000h config1l debug xinst stvren ? ? ? ?wdten 111- ---1 300001h config1h ? (2) ? (2) ? (2) ? (2) ? (3) cp0 ? ? ---- 01-- 300002h config2l ieso fcmen ? ? ?fosc2fosc1fosc0 11-- -111 300003h config2h ? (2) ? (2) ? (2) ? (2) wdtps3 wdtps2 wdtps1 wdtps0 ---- 1111 300004h config3l wait (4) bw (4) emb1 (4) emb0 (4) eashft (4) ? ? ? 1111 1--- 300005h config3h ? (2) ? (2) ? (2) ? (2) ?ethledeccpmx (5) ccp2mx (5) ---- -111 3ffffeh devid1 dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 xxxx xxxx (6) 3fffffh devid2 dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 xxxx xxxx (6) legend: x = unknown, u = unchanged, - = unimplemented. shaded cells are unimplemented, read as ? 0 ?. note 1: values reflect the unprogrammed state as received from t he factory and following power-on resets. in all other reset states, the configuration bytes maintain their previously programmed states. 2: the value of these bits in program memory should always be ? 1 ?. this ensures that the location is executed as a nop if it is accidentally executed. 3: this bit should always be maintained as ? 0 ?. 4: implemented on 100-pin devices only. 5: implemented on 80-pin and 100-pin devices only. 6: see register 24-7 and register 24-8 for devid values. t hese registers are read-only and cannot be programmed by the user. ? 2006 microchip technology inc. advance information ds39762a-page 347 pic18f97j60 family register 24-1: config1l: configuration register 1 low (byte address 300000h) r/wo-1 r/wo-1 r/wo-0 u-0 u-0 u-0 u-0 r/wo-1 debug xinst stvren ? ? ? ?wdten bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7 debug : background debugger enable bit 1 = background debugger disabled; rb6 and rb7 configured as general purpose i/o pins 0 = background debugger enabled; rb6 and rb7 are dedicated to in-circuit debug bit 6 xinst: extended instruction set enable bit 1 = instruction set extension and indexed addressing mode enabled 0 = instruction set extension and indexed addressing mode disabled (legacy mode) bit 5 stvren : stack overflow/underflow reset enable bit 1 = reset on stack overflow/underflow enabled 0 = reset on stack overflow/underflow disabled bit 4-1 unimplemented: read as ? 0 ? bit 0 wdten: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled (control is placed on swdten bit) register 24-2: config1h: configuration register 1 high (byte address 300001h) u-0 u-0 u-0 u-0 u-0 (1) r/wo-1 u-0 u-0 ? (2) ? (2) ? (2) ? (2) ?cp0 ? ? bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7-3 unimplemented: read as ? 0 ? bit 2 cp0: code protection bit 1 = program memory is not code-protected 0 = program memory is code-protected bit 1-0 unimplemented: read as ? 0 ? note 1: this bit should always be maintained as ? 0 ?. 2: the value of these bits in program memory should always be ? 1 ?. this ensures that the location is executed as a nop if it is accidentally executed. pic18f97j60 family ds39762a-page 348 advance information ? 2006 microchip technology inc. register 24-3: config2l: configuration register 2 low (byte address 300002h) r/wo-1 r/wo-1 u-0 u-0 u-0 r/wo-1 r/wo-1 r/wo-1 ieso fcmen ? ? ?fosc2fosc1fosc0 bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7 ieso: two-speed start-up (internal/external oscillator switchover) control bit 1 = two-speed start-up enabled 0 = two-speed start-up disabled bit 6 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor enabled 0 = fail-safe clock monitor disabled bit 5-3 unimplemented: read as ? 0 ? bit 2 fosc2: default/reset system clock select bit 1 = clock selected by fosc1:fosc0 as system clock is enabled when osccon<1:0> = 00 0 = intrc enabled as system clock when osccon<1:0> = 00 bit 1-0 fosc1:fosc0: oscillator selection bits 11 = ec oscillator, pll enabled and under software control, clko function on osc2 10 = ec oscillator, clko function on osc2 01 = hs oscillator, pll enabled and under software control 00 = hs oscillator ? 2006 microchip technology inc. advance information ds39762a-page 349 pic18f97j60 family register 24-4: config2h: configuration register 2 high (byte address 300003h) u-0 u-0 u-0 u-0 r/wo-1 r/wo-1 r/wo-1 r/wo-1 ? (1) ? (1) ? (1) ? (1) wdtps3 wdtps2 wdtps1 wdtps0 bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 0 ? bit 3-0 wdtps3:wdtps0: watchdog timer postscale select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 note 1: the value of these bits in program memory should always be ? 1 ?. this ensures that the location is executed as a nop if it is accidentally executed. pic18f97j60 family ds39762a-page 350 advance information ? 2006 microchip technology inc. register 24-5: config3l: configuration register 3 low (byte address 300004h) r/wo-1 r/wo-1 r/wo-1 r/wo-1 r/wo-1 u-0 u-0 u-0 wait (1) bw (1) emb1 (1) emb0 (1) eashft (1) ? ? ? bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7 wait: external bus wait enable bit (1) 1 = wait states for operations on external memory bus disabled 0 = wait states for operations on external memory bus enabled and selected by memcon<5:4> bit 6 bw: data bus width select bit (1) 1 = 16-bit data width mode 0 = 8-bit data width mode bit 5-4 emb1:emb0: external memory bus configuration bits (1) 11 = microcontroller mode, external bus disabled 10 = extended microcontroller mode,12-bit address mode 01 = extended microcontroller mode,16-bit address mode 00 = extended microcontroller mode, 20-bit address mode bit 3 eashft: external address bus shift enable bit (1) 1 = address shifting enabled; address on external bus is offset to start at 000000h 0 = address shifting disabled; address on external bus reflects the pc value bit 2-0 unimplemented: read as ? 0 ? note 1: implemented on 100-pin devices only. ? 2006 microchip technology inc. advance information ds39762a-page 351 pic18f97j60 family register 24-6: config3h: configuration register 3 high (byte address 300005h) u-0 u-0 u-0 u-0 u-0 r/wo-1 r/wo-1 r/wo-1 ? (1) ? (1) ? (1) ? (1) ?ethledeccpmx (2) ccp2mx (2) bit 7 bit 0 legend: r = readable bit wo = write-once bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed ?1? = bit is set ?0? = bit is cleared bit 7-3 unimplemented: read as ? 0 ? bit 2 ethled: ethernet led enable bit 1 = ra0/ra1 are multiplexed with leda/ledb when ethernet module is enabled and function as i/o when ethernet is disabled 0 = ra0/ra1 function as i/o regardless of ethernet module status bit 1 eccpmx: eccp mux bit (2) 1 = eccp1 outputs (p1b/p1c) are multiplexed with re6 and re5; eccp3 outputs (p3b/p3c) are multiplexed with re4 and re3 0 = eccp1 outputs (p1b/p1c) are multiplexed with rh7 and rh6; eccp3 outputs (p3b/p3c) are multiplexed with rh5 and rh4 bit 0 ccp2mx: eccp2 mux bit (2) 1 = eccp2/p2a is multiplexed with rc1 0 = eccp2/p2a is multiplexed with re7 in mi crocontroller mode (80-pin and 100-pin devices) or with rb3 in extended microcontroller mode (100-pin devices only) note 1: the value of these bits in program memory should always be ? 1 ?. this ensures that the location is executed as a nop if it is accidentally executed. 2: implemented on 80-pin and 100-pin devices only. pic18f97j60 family ds39762a-page 352 advance information ? 2006 microchip technology inc. register 24-7: devid1: device id register 1 for pic18f97j60 family devices rrrrrrrr dev2 dev1 dev0 rev4 rev3 rev2 rev1 rev0 bit 7 bit 0 legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state bit 7-5 dev2:dev0: device id bits see register 24-8 for a complete listing. bit 4-0 rev4:rev0: revision id bits these bits are used to indicate the device revision. register 24-8: devid2: device id register 2 for pic18f97j60 family devices rrrrrrrr dev10 dev9 dev8 dev7 dev6 dev5 dev4 dev3 bit 7 bit 0 legend: r = read-only bit p = programmable bit u = unimplemented bit, read as ?0? -n = value when device is unprogrammed u = unchanged from programmed state bit 7-0 dev10:dev3: device id bits: dev10:dev3 (devid2<7:0>) dev2:dev0 (devid1<7:5>) device 0001 1000 000 pic18f66j60 0001 1111 000 pic18f66j65 0001 1111 001 pic18f67j60 0001 1000 001 PIC18F86J60 0001 1111 010 pic18f86j65 0001 1111 011 pic18f87j60 0001 1000 010 pic18f96j60 0001 1111 100 pic18f96j65 0001 1111 101 pic18f97j60 ? 2006 microchip technology inc. advance information ds39762a-page 353 pic18f97j60 family 24.2 watchdog timer (wdt) for pic18f97j60 family devices, the wdt is driven by the intrc oscillator. when the wdt is enabled, the clock source is also enabled. the nominal wdt period is 4 ms and has the same stability as the intrc oscillator. the 4 ms period of the wdt is multiplied by a 16-bit postscaler. any output of the wdt postscaler is selected by a multiplexor, controlled by the wdtps bits in configuration register 2h. available periods range from 4 ms to 131.072 seconds (2.18 minutes). the wdt and postscaler are cleared whenever a sleep or clrwdt instruction is executed, or a clock failure (primary or timer1 oscillator) has occurred. 24.2.1 control register the wdtcon register (register 24-9) is a readable and writable register. the swdten bit enables or dis- ables wdt operation. this allows software to override the wdten configuration bit and enable the wdt only if it has been disabled by the configuration bit. figure 24-1: wdt block diagram table 24-2: summary of watchdog timer registers note 1: the clrwdt and sleep instructions clear the wdt and postscaler counts when executed. 2: when a clrwdt instruction is executed, the postscaler count will be cleared. register 24-9: wdtcon: watchdog timer control register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ?swdten (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 unimplemented: read as ? 0 ? bit 0 swdten: software controlled watchdog timer enable bit (1) 1 = watchdog timer is on 0 = watchdog timer is off note 1: this bit has no effect if the configuration bit, wdten, is enabled. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page rcon ipen ? ? ri to pd por bor 60 wdtcon ? ? ? ? ? ? ?swdten 60 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the watchdog timer. intrc oscillator wdt wake-up from reset wdt wdt counter programmable postscaler 1:1 to 1:32,768 enable wdt wdtps3:wdtps0 swdten clrwdt 4 power-managed reset all device resets sleep intrc control 128 modes pic18f97j60 family ds39762a-page 354 advance information ? 2006 microchip technology inc. 24.3 on-chip voltage regulator all of the pic18f97j60 family devices power their core digital logic at a nominal 2.5v. this may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3v. to simplify system design, all devices in the pic18f97j60 family incor- porate an on-chip regulator that allows the device to run its core logic from v dd . the regulator is controlled by the envreg pin. tying v dd to the pin enables the regulator, which in turn, provides power to the core from the other v dd pins. when the regulator is enabled, a low-esr filter capacitor must be connected to the v ddcore /v cap pin (figure 24-2). this helps to maintain the stability of the regulator. the recommended value for the filter capacitor is provided in section 27.3 ?dc characteristics: pic18f97j60 family (industrial)? . if envreg is tied to v ss , the regulator is disabled. in this case, separate power for the core logic at a nomi- nal 2.5v must be supplied to the device on the v ddcore /v cap pin to run the i/o pins at higher voltage levels, typically 3.3v. alternatively, the v ddcore /v cap and v dd pins can be tied together to operate at a lower nominal voltage. refer to figure 24-2 for possible configurations. 24.3.1 on-chip regulator and bor when the on-chip regulator is enabled, pic18f97j60 family devices also have a simple brown-out capability. if the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator reset circuitry will generate a brown-out reset. this event is captured by the bor flag bit (rcon<0>). the operation of the bor is described in more detail in section 4.4 ?brown-out reset (bor)? and section 4.4.1 ?detecting bor? . the brown-out reset voltage levels are specific in section 27.1 ?dc characteristics: supply voltage, pic18f97j60 family (industrial)? . 24.3.2 power-up requirements the on-chip regulator is designed to meet the power-up requirements for the device. if the application does not use the regulator, then strict power-up conditions must be adhered to. while powering up, v ddcore must never exceed v dd by 0.3 volts. figure 24-2: conne ctions for the on-chip regulator v dd envreg v ddcore /v cap v ss pic18fxxj6x 3.3v (1) 2.5v (1) v dd envreg v ddcore /v cap v ss pic18fxxj6x c f 3.3v regulator enabled (envreg tied to v dd ): regulator disabled (envreg tied to ground): v dd envreg v ddcore /v cap v ss pic18fxxj6x 2.5v (1) (v dd > v ddcore ) note 1: these are typical operating voltages. refer to section 27.1 ?dc characteristics: supply voltage? for the full operating ranges of v dd and v ddcore . (v dd = v ddcore ) ? 2006 microchip technology inc. advance information ds39762a-page 355 pic18f97j60 family 24.4 two-speed start-up the two-speed start-up feature helps to minimize the latency period, from oscillator start-up to code execu- tion, by allowing the microcontroller to use the intrc oscillator as a clock source until the primary clock source is available. it is enabled by setting the ieso configuration bit. two-speed start-up should be enabled only if the primary oscillator mode is hs or hspll (crystal-based) modes. since the ec and ecpll modes do not require an ost start-up delay, two-speed start-up should be disabled. when enabled, resets and wake-ups from sleep mode cause the device to configure itself to run from the internal oscillator block as the clock source, following the time-out of the power-up timer after a power-on reset is enabled. this allows almost immediate code execution while the primary oscillator starts and the ost is running. once the ost times out, the device automatically switches to pri_run mode. in all other power-managed modes, two-speed start-up is not used. the device will be clocked by the currently selected clock source until the primary clock source becomes available. the setting of the ieso bit is ignored. 24.4.1 special considerations for using two-speed start-up while using the intrc oscillator in two-speed start-up, the device still obeys the normal command sequences for entering power-managed modes, including serial sleep instructions (refer to section 3.1.4 ?multiple sleep commands? ). in prac- tice, this means that user code can change the scs1:scs0 bit settings or issue sleep instructions before the ost times out. this would allow an applica- tion to briefly wake-up, perform routine ?housekeeping? tasks and return to sleep before the device starts to operate from the primary oscillator. user code can also check if the primary clock source is currently providing the device clocking by checking the status of the osts bit (osccon<3>). if the bit is set, the primary oscillator is providing the clock. otherwise, the internal oscillator block is providing the clock during wake-up from reset or sleep mode. figure 24-3: timing transition for two-speed start-up (intrc to hspll) q1 q3 q4 osc1 peripheral program pc pc + 2 intrc pll clock q1 pc + 6 q2 output q3 q4 q1 cpu clock pc + 4 clock counter q2 q2 q3 note 1: t ost = 1024 t osc ; t pll = 2 ms (approx). these intervals are not shown to scale. wake from interrupt event t pll (1) 12 n-1n clock osts bit set transition t ost (1) pic18f97j60 family ds39762a-page 356 advance information ? 2006 microchip technology inc. 24.5 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the microcontroller to continue operation in the event of an external oscillator failure by automatically switching the device clock to the internal oscillator block. the fscm function is enabled by setting the fcmen configuration bit. when fscm is enabled, the intrc oscillator runs at all times to monitor clocks to peripherals and provide a backup clock in the event of a clock failure. clock monitoring (shown in figure 24-4) is accomplished by creating a sample clock signal which is the intrc out- put divided by 64. this allows ample time between fscm sample clocks for a peripheral clock edge to occur. the peripheral device clock and the sample clock are presented as inputs to the clock monitor latch (cm). the cm is set on the falling edge of the device clock source but cleared on the rising edge of the sample clock. figure 24-4: fscm block diagram clock failure is tested for on the falling edge of the sample clock. if a sample clock falling edge occurs while cm is still set, a clock failure has been detected (figure 24-5). this causes the following: ? the fscm generates an oscillator fail interrupt by setting bit, oscfif (pir2<7>); ? the device clock source is switched to the internal oscillator block (osccon is not updated to show the current clock source ? this is the fail-safe condition); and ?the wdt is reset. during switchover, the postscaler frequency from the internal oscillator block may not be sufficiently stable for timing sensitive applications. in these cases, it may be desirable to select another clock configuration and enter an alternate power-managed mode. this can be done to attempt a partial recovery or execute a controlled shutdown. see section 3.1.4 ?multiple sleep commands? and section 24.4.1 ?special considerations for using two-speed start-up? for more details. the fscm will detect failures of the primary or second- ary clock sources only. if the internal oscillator block fails, no failure would be detected, nor would any action be possible. 24.5.1 fscm and the watchdog timer both the fscm and the wdt are clocked by the intrc oscillator. since the wdt operates with a separate divider and counter, disabling the wdt has no effect on the operation of the intrc oscillator when the fscm is enabled. as already noted, the clock source is switched to the intrc clock when a clock failure is detected. this may mean a substantial change in the speed of code execu- tion. if the wdt is enabled with a small prescale value, a decrease in clock speed allows a wdt time-out to occur and a subsequent device reset. for this reason, fail-safe clock events also reset the wdt and postscaler, allowing it to start timing from when execu- tion speed was changed and decreasing the likelihood of an erroneous time-out. 24.5.2 exiting fail-safe operation the fail-safe condition is terminated by either a device reset or by entering a power-managed mode. on reset, the controller starts the primary clock source specified in configuration register 2h (with any required start-up delays that are required for the oscil- lator mode, such as ost or pll timer). the intrc oscillator provides the device clock until the primary clock source becomes ready (similar to a two-speed start-up). the clock source is then switched to the primary clock (indicated by the osts bit in the osccon register becoming set). the fail-safe clock monitor then resumes monitoring the peripheral clock. the primary clock source may never become ready during start-up. in this case, operation is clocked by the intrc oscillator. the osccon register will remain in its reset state until a power-managed mode is entered. peripheral intrc 64 s c q (32 s) 488 hz (2.048 ms) clock monitor latch (cm) (edge-triggered) clock failure detected source clock q ? 2006 microchip technology inc. advance information ds39762a-page 357 pic18f97j60 family figure 24-5: fscm timing diagram 24.5.3 fscm interrupts in power-managed modes by entering a power-managed mode, the clock multiplexor selects the clock source selected by the osccon register. fail-safe monitoring of the power-managed clock source resumes in the power-managed mode. if an oscillator failure occurs during power-managed operation, the subsequent events depend on whether or not the oscillator failure interrupt is enabled. if enabled (oscfif = 1 ), code execution will be clocked by the intrc multiplexor. an automatic transition back to the failed clock source will not occur. if the interrupt is disabled, subsequent interrupts while in idle mode will cause the cpu to begin executing instructions while being clocked by the intrc source. 24.5.4 por or wake-up from sleep the fscm is designed to detect oscillator failure at any point after the device has exited power-on reset (por) or low-power sleep mode. when the primary device clock is either ec or intrc, monitoring can begin immediately following these events. for hs or hspll modes, the situation is somewhat different. since the oscillator may require a start-up time considerably longer than the fscm sample clock time, a false clock failure may be detected. to prevent this, the internal oscillator block is automatically config- ured as the device clock and functions until the primary clock is stable (the ost and pll timers have timed out). this is identical to two-speed start-up mode. once the primary clock is stable, the intrc returns to its role as the fscm source. as noted in section 24.4.1 ?special considerations for using two-speed start-up? , it is also possible to select another clock configuration and enter an alternate power-managed mode while waiting for the primary clock to become stable. when the new power-managed mode is selected, the primary clock is disabled. oscfif cm output device clock output sample clock failure detected oscillator failure note: the device clock is normally at a much higher frequen cy than the sample clock. the relative frequencies in this example have been chosen for clarity. (q ) cm test cm test cm test note: the same logic that prevents false oscilla- tor failure interrupts on por, or wake from sleep, will also prevent the detection of the oscillator?s failure to start at all follow- ing these events. this can be avoided by monitoring the osts bit and using a timing routine to determine if the oscillator is taking too long to start. even so, no oscillator failure interrupt will be flagged. pic18f97j60 family ds39762a-page 358 advance information ? 2006 microchip technology inc. 24.6 program verification and code protection for all devices in the pic18f97j60 family, the on-chip program memory space is treated as a single block. code protection for this block is controlled by one configuration bit, cp0. this bit inhibits external reads and writes to the program memory space. it has no direct effect in normal execution mode. 24.6.1 configuration register protection the configuration registers are protected against untoward changes or reads in two ways. the primary protection is the write-once feature of the configuration bits which prevents reconfiguration once the bit has been programmed during a power cycle. to safeguard against unpredictable events, configuration bit changes resulting from individual cell level disruptions (such as esd events) will cause a parity error and trigger a device reset. the data for the configuration registers is derived from the flash configuration words in program memory. when the cp0 bit set, the source data for device configuration is also protected as a consequence. 24.7 in-circuit serial programming pic18f97j60 family microcontrollers can be serially programmed while in the end application circuit. this is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. this allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. this also allows the most recent firmware or a custom firmware to be programmed. 24.8 in-circuit debugger when the debug configuration bit is programmed to a ? 0 ?, the in-circuit debugger functionality is enabled. this function allows simple debugging functions when used with mplab ? ide. when the microcontroller has this feature enabled, some resources are not available for general use. table 24-3 shows which resources are required by the background debugger. table 24-3: debugger resources i/o pins: rb6, rb7 stack: 2 levels program memory: 512 bytes data memory: 10 bytes ? 2006 microchip technology inc. advance information ds39762a-page 359 pic18f97j60 family 25.0 instruction set summary the pic18f97j60 family of devices incorporates the standard set of 75 pic18 core instructions, as well as an extended set of 8 new instructions for the optimiza- tion of code that is recursive or that utilizes a software stack. the extended set is discussed later in this section. 25.1 standard instruction set the standard pic18 instruction set adds many enhancements to the previous picmicro ? instruction sets, while maintaining an easy migration from these picmicro instruction sets. most instructions are a single program memory word (16 bits), but there are four instructions that require two program memory locations. each single-word instruction is a 16-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. the instruction set is highly orthogonal and is grouped into four basic categories: ? byte-oriented operations ? bit-oriented operations ? literal operations ? control operations the pic18 instruction set summary in table 25-2 lists byte-oriented , bit-oriented , literal and control operations. table 25-1 shows the opcode field descriptions. most byte-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the destination of the result (specified by ?d?) 3. the accessed memory (specified by ?a?) the file register designator ?f? specifies which file regis- ter is to be used by the instruction. the destination designator ?d? specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the wreg register. if ?d? is one, the result is placed in the file register specified in the instruction. all bit-oriented instructions have three operands: 1. the file register (specified by ?f?) 2. the bit in the file register (specified by ?b?) 3. the accessed memory (specified by ?a?) the bit field designator ?b? selects the number of the bit affected by the operation, while the file register desig- nator ?f? represents the number of the file in which the bit is located. the literal instructions may use some of the following operands: ? a literal value to be loaded into a file register (specified by ?k?) ? the desired fsr register to load the literal value into (specified by ?f?) ? no operand required (specified by ???) the control instructions may use some of the following operands: ? a program memory address (specified by ?n?) ? the mode of the call or return instructions (specified by ?s?) ? the mode of the table read and table write instructions (specified by ?m?) ? no operand required (specified by ???) all instructions are a single word, except for four double-word instructions. these instructions were made double-word to contain the required information in 32 bits. in the second word, the 4 msbs are ? 1 ?s. if this second word is executed as an instruction (by itself), it will execute as a nop . all single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruc- tion. in these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a nop . the double-word instructions execute in two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 s. if a conditional test is true, or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. two-word branch instructions (if true) would take 3 s. figure 25-1 shows the general formats that the instruc- tions can have. all examples use the convention ?nnh? to represent a hexadecimal number. the instruction set summary, shown in table 25-2, lists the standard instructions recognized by the microchip mpasm tm assembler. section 25.1.1 ?standard instruction set? provides a description of each instruction. pic18f97j60 family ds39762a-page 360 advance information ? 2006 microchip technology inc. table 25-1: opcode field descriptions field description a ram access bit: a = 0 : ram location in access ram (bsr register is ignored) a = 1 : ram bank is specified by bsr register bbb bit address within an 8-bit file register (0 to 7). bsr bank select register. used to select the current ram bank. c, dc, z, ov, n alu status bits: c arry, d igit c arry, z ero, ov erflow, n egative. d destination select bit: d = 0 : store result in wreg d = 1 : store result in file register f dest destination: either the wreg register or the specified register file location. f 8-bit register file address (00h to ffh), or 2-bit fsr designator (0h to 3h). f s 12-bit register file address (000h to ff fh). this is the source address. f d 12-bit register file address (000h to fffh). this is the destination address. gie global interrupt enable bit. k literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value). label label name. mm the mode of the tblptr register for the table read and table write instructions. only used with table read and table write instructions: * no change to register (such as tblptr with table reads and writes) *+ post-increment register (such as tblptr with table reads and writes) *- post-decrement register (such as tblptr with table reads and writes) +* pre-increment register (such as tb lptr with table reads and writes) n the relative address (2?s complement number) for relative branch instructions or the direct address for call/branch and return instructions. pc program counter. pcl program counter low byte. pch program counter high byte. pclath program counter high byte latch. pclatu program counter upper byte latch. pd power-down bit. prodh product of multiply high byte. prodl product of multiply low byte. s fast call/return mode select bit: s = 0 : do not update into/from shadow registers s = 1 : certain registers loaded into/from shadow registers (fast mode) tblptr 21-bit table pointer (points to a program memory location). tablat 8-bit table latch. to time-out bit. tos top-of-stack. u unused or unchanged. wdt watchdog timer. wreg working register (accumulator). x don?t care (? 0 ? or ? 1 ?). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. z s 7-bit offset value for indirect addr essing of register files (source). z d 7-bit offset value for indirect addressing of register files (destination). { } optional argument. [text] indicates an indexed address. (text) the contents of text . [expr] ? 2006 microchip technology inc. advance information ds39762a-page 361 pic18f97j60 family figure 25-1: general format for instructions byte-oriented file register operations 15 10 9 8 7 0 d = 0 for result destination to be wreg register opcode d a f (file #) d = 1 for result destination to be file register (f) a = 0 to force access bank bit-oriented file register operations 15 12 11 9 8 7 0 opcode b (bit #) a f (file #) b = 3-bit position of bit in file register (f) literal operations byte to byte move operations (2-word) 15 12 11 0 opcode f (source file #) call, goto and branch operations 15 8 7 0 opcode n<7:0> (literal) n = 20-bit immediate value a = 1 for bsr to select bank f = 8-bit file register address a = 0 to force access bank a = 1 for bsr to select bank f = 8-bit file register address 15 12 11 0 1111 n<19:8> (literal) 15 12 11 0 1111 f (destination file #) f = 12-bit file register address control operations example instruction addwf myreg, w, b movff myreg1, myreg2 bsf myreg, bit, b movlw 7fh goto label 15 8 7 0 opcode n<7:0> (literal) 15 12 11 0 1111 n<19:8> (literal) call myfunc 15 11 10 0 opcode n<10:0> (literal) s = fast bit bra myfunc 15 8 7 0 opcode n<7:0> (literal) bc myfunc s 15 8 7 0 opcode k (literal) k = 8-bit immediate value pic18f97j60 family ds39762a-page 362 advance information ? 2006 microchip technology inc. table 25-2: pic18f97j60 family instruction set mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb byte-oriented operations addwf addwfc andwf clrf comf cpfseq cpfsgt cpfslt decf decfsz dcfsnz incf incfsz infsnz iorwf movf movff movwf mulwf negf rlcf rlncf rrcf rrncf setf subfwb subwf subwfb swapf tstfsz xorwf f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f s , f d f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a add wreg and f add wreg and carry bit to f and wreg with f clear f complement f compare f with wreg, skip = compare f with wreg, skip > compare f with wreg, skip < decrement f decrement f, skip if 0 decrement f, skip if not 0 increment f increment f, skip if 0 increment f, skip if not 0 inclusive or wreg with f move f move f s (source) to 1st word f d (destination) 2nd word move wreg to f multiply wreg with f negate f rotate left f through carry rotate left f (no carry) rotate right f through carry rotate right f (no carry) set f subtract f from wreg with borrow subtract wreg from f subtract wreg from f with borrow swap nibbles in f test f, skip if 0 exclusive or wreg with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 0010 0001 0110 0001 0110 0110 0110 0000 0010 0100 0010 0011 0100 0001 0101 1100 1111 0110 0000 0110 0011 0100 0011 0100 0110 0101 0101 0101 0011 0110 0001 01da 00da 01da 101a 11da 001a 010a 000a 01da 11da 11da 10da 11da 10da 00da 00da ffff ffff 111a 001a 110a 01da 01da 00da 00da 100a 01da 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z, ov, n c, dc, z, ov, n z, n z z, n none none none c, dc, z, ov, n none none c, dc, z, ov, n none none z, n z, n none none none c, dc, z, ov, n c, z, n z, n c, z, n z, n none c, dc, z, ov, n c, dc, z, ov, n c, dc, z, ov, n none none z, n 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1 1, 2 1, 2 1, 2 1, 2 4 1, 2 note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. ? 2006 microchip technology inc. advance information ds39762a-page 363 pic18f97j60 family bit-oriented operations bcf bsf btfsc btfss btg f, b, a f, b, a f, b, a f, b, a f, b, a bit clear f bit set f bit test f, skip if clear bit test f, skip if set bit toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff none none none none none 1, 2 1, 2 3, 4 3, 4 1, 2 control operations bc bn bnc bnn bnov bnz bov bra bz call clrwdt daw goto nop nop pop push rcall reset retfie retlw return sleep n n n n n n n n n n, s ? ? n ? ? ? ? n s k s ? branch if carry branch if negative branch if not carry branch if not negative branch if not overflow branch if not zero branch if overflow branch unconditionally branch if zero call subroutine 1st word 2nd word clear watchdog timer decimal adjust wreg go to address 1st word 2nd word no operation no operation pop top of return stack (tos) push top of return stack (tos) relative call software device reset return from interrupt enable return with literal in wreg return from subroutine go into standby mode 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s kkkk 001s 0011 none none none none none none none none none none to , pd c none none none none none none all gie/gieh, peie/giel none none to , pd 4 table 25-2: pic18f97j60 family instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. pic18f97j60 family ds39762a-page 364 advance information ? 2006 microchip technology inc. literal operations addlw andlw iorlw lfsr movlb movlw mullw retlw sublw xorlw k k k f, k k k k k k k add literal and wreg and literal with wreg inclusive or literal with wreg move literal (12-bit) 2nd word to fsr(f) 1st word move literal to bsr<3:0> move literal to wreg multiply literal with wreg return with literal in wreg subtract wreg from literal exclusive or literal with wreg 1 1 1 2 1 1 1 2 1 1 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z, ov, n z, n z, n none none none none none c, dc, z, ov, n z, n data memory ? program memory operations tblrd* tblrd*+ tblrd*- tblrd+* tblwt* tblwt*+ tblwt*- tblwt+* table read table read with post-increment table read with post-decrement table read with pre-increment table write table write with post-increment table write with post-decrement table write with pre-increment 2 2 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 1010 1011 1100 1101 1110 1111 none none none none none none none none table 25-2: pic18f97j60 family instruction set (continued) mnemonic, operands description cycles 16-bit instruction word status affected notes msb lsb note 1: when a port register is modified as a function of itself (e.g., movf portb, 1, 0 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and, where applicable, d = 1 ), the prescaler will be cleared if assigned. 3: if program counter (pc) is modified or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 4: some instructions are two-word instructions. the second word of these instructions will be executed as a nop unless the first word of the instruction retrieves the information embedded in these 16 bits. this ensures that all program memory locations have a valid instruction. ? 2006 microchip technology inc. advance information ds39762a-page 365 pic18f97j60 family 25.1.1 standard instruction set addlw add literal to w syntax: addlw k operands: 0 k 255 operation: (w) + k w status affected: n, ov, c, dc, z encoding: 0000 1111 kkkk kkkk description: the contents of w are added to the 8-bit literal ?k? and the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: addlw 15h before instruction w = 10h after instruction w = 25h addwf add w to f syntax: addwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) dest status affected: n, ov, c, dc, z encoding: 0010 01da ffff ffff description: add w to register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwf reg, 0, 0 before instruction w = 17h reg = 0c2h after instruction w = 0d9h reg = 0c2h note: all pic18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. if a label is used, the instruction format then becomes: {label} instruction argument(s). pic18f97j60 family ds39762a-page 366 advance information ? 2006 microchip technology inc. addwfc add w and carry bit to f syntax: addwfc f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) + (f) + (c) dest status affected: n,ov, c, dc, z encoding: 0010 00da ffff ffff description: add w, the carry flag and data memory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: addwfc reg, 0, 1 before instruction carry bit = 1 reg = 02h w=4dh after instruction carry bit = 0 reg = 02h w = 50h andlw and literal with w syntax: andlw k operands: 0 k 255 operation: (w) .and. k w status affected: n, z encoding: 0000 1011 kkkk kkkk description: the contents of w are anded with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: andlw 05fh before instruction w=a3h after instruction w = 03h ? 2006 microchip technology inc. advance information ds39762a-page 367 pic18f97j60 family andwf and w with f syntax: andwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) .and. (f) dest status affected: n, z encoding: 0001 01da ffff ffff description: the contents of w are anded with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: andwf reg, 0, 0 before instruction w = 17h reg = c2h after instruction w = 02h reg = c2h bc branch if carry syntax: bc n operands: -128 n 127 operation: if carry bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0010 nnnn nnnn description: if the carry bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bc 5 before instruction pc = address (here) after instruction if carry = 1; pc = address (here + 12) if carry = 0; pc = address (here + 2) pic18f97j60 family ds39762a-page 368 advance information ? 2006 microchip technology inc. bcf bit clear f syntax: bcf f, b {,a} operands: 0 f 255 0 b 7 a [0,1] operation: 0 f status affected: none encoding: 1001 bbba ffff ffff description: bit ?b? in register ?f? is cleared. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bcf flag_reg, 7, 0 before instruction flag_reg = c7h after instruction flag_reg = 47h bn branch if negative syntax: bn n operands: -128 n 127 operation: if negative bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0110 nnnn nnnn description: if the negative bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bn jump before instruction pc = address (here) after instruction if negative = 1; pc = address (jump) if negative = 0; pc = address (here + 2) ? 2006 microchip technology inc. advance information ds39762a-page 369 pic18f97j60 family bnc branch if not carry syntax: bnc n operands: -128 n 127 operation: if carry bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0011 nnnn nnnn description: if the carry bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnc jump before instruction pc = address (here) after instruction if carry = 0; pc = address (jump) if carry = 1; pc = address (here + 2) bnn branch if not negative syntax: bnn n operands: -128 n 127 operation: if negative bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0111 nnnn nnnn description: if the negative bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnn jump before instruction pc = address (here) after instruction if negative = 0; pc = address (jump) if negative = 1; pc = address (here + 2) pic18f97j60 family ds39762a-page 370 advance information ? 2006 microchip technology inc. bnov branch if not overflow syntax: bnov n operands: -128 n 127 operation: if overflow bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0101 nnnn nnnn description: if the overflow bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnov jump before instruction pc = address (here) after instruction if overflow = 0; pc = address (jump) if overflow = 1; pc = address (here + 2) bnz branch if not zero syntax: bnz n operands: -128 n 127 operation: if zero bit is ? 0 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0001 nnnn nnnn description: if the zero bit is ? 0 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bnz jump before instruction pc = address (here) after instruction if zero = 0; pc = address (jump) if zero = 1; pc = address (here + 2) ? 2006 microchip technology inc. advance information ds39762a-page 371 pic18f97j60 family bra unconditional branch syntax: bra n operands: -1024 n 1023 operation: (pc) + 2 + 2n pc status affected: none encoding: 1101 0nnn nnnn nnnn description: add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation example: here bra jump before instruction pc = address (here) after instruction pc = address (jump) bsf bit set f syntax: bsf f, b {,a} operands: 0 f 255 0 b 7 a [0,1] operation: 1 f status affected: none encoding: 1000 bbba ffff ffff description: bit ?b? in register ?f? is set. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: bsf flag_reg, 7, 1 before instruction flag_reg = 0ah after instruction flag_reg = 8ah pic18f97j60 family ds39762a-page 372 advance information ? 2006 microchip technology inc. btfsc bit test file, skip if clear syntax: btfsc f, b {,a} operands: 0 f 255 0 b 7 a [0,1] operation: skip if (f) = 0 status affected: none encoding: 1011 bbba ffff ffff description: if bit ?b? in register ?f? is ? 0 ?, then the next instruction is skipped. if bit ?b? is ? 0 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfsc : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (true) if flag<1> = 1; pc = address (false) btfss bit test file, skip if set syntax: btfss f, b {,a} operands: 0 f 255 0 b < 7 a [0,1] operation: skip if (f) = 1 status affected: none encoding: 1010 bbba ffff ffff description: if bit ?b? in register ?f? is ? 1 ?, then the next instruction is skipped. if bit ?b? is ? 1 ?, then the next instruction fetched during the current instruction execution is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here false true btfss : : flag, 1, 0 before instruction pc = address (here) after instruction if flag<1> = 0; pc = address (false) if flag<1> = 1; pc = address (true) ? 2006 microchip technology inc. advance information ds39762a-page 373 pic18f97j60 family btg bit toggle f syntax: btg f, b {,a} operands: 0 f 255 0 b < 7 a [0,1] operation: (f ) f status affected: none encoding: 0111 bbba ffff ffff description: bit ?b? in data memory location ?f? is inverted. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: btg portc, 4, 0 before instruction: portc = 0111 0101 [75h] after instruction: portc = 0110 0101 [65h] bov branch if overflow syntax: bov n operands: -128 n 127 operation: if overflow bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0100 nnnn nnnn description: if the overflow bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bov jump before instruction pc = address (here) after instruction if overflow = 1; pc = address (jump) if overflow = 0; pc = address (here + 2) pic18f97j60 family ds39762a-page 374 advance information ? 2006 microchip technology inc. bz branch if zero syntax: bz n operands: -128 n 127 operation: if zero bit is ? 1 ? (pc) + 2 + 2n pc status affected: none encoding: 1110 0000 nnnn nnnn description: if the zero bit is ? 1 ?, then the program will branch. the 2?s complement number ?2n? is added to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is then a two-cycle instruction. words: 1 cycles: 1(2) q cycle activity: if jump: q1 q2 q3 q4 decode read literal ?n? process data write to pc no operation no operation no operation no operation if no jump: q1 q2 q3 q4 decode read literal ?n? process data no operation example: here bz jump before instruction pc = address (here) after instruction if zero = 1; pc = address (jump) if zero = 0; pc = address (here + 2) call subroutine call syntax: call k {,s} operands: 0 k 1048575 s [0,1] operation: (pc) + 4 tos, k pc<20:1>, if s = 1 (w) ws, (status) statuss, (bsr) bsrs status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 110s k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: subroutine call of entire 2-mbyte memory range. first, return address (pc+ 4) is pushed onto the return stack. if ?s? = 1 , the w, status and bsr registers are also pushed into their respective shadow registers, ws, statuss and bsrs. if ?s? = 0 , no update occurs (default). then, the 20-bit value ?k? is loaded into pc<20:1>. call is a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, push pc to stack read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: here call there,1 before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 4) ws = w bsrs = bsr statuss = status ? 2006 microchip technology inc. advance information ds39762a-page 375 pic18f97j60 family clrf clear f syntax: clrf f {,a} operands: 0 f 255 a [0,1] operation: 000h f 1 z status affected: z encoding: 0110 101a ffff ffff description: clears the contents of the specified register. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: clrf flag_reg,1 before instruction flag_reg = 5ah after instruction flag_reg = 00h clrwdt clear watchdog timer syntax: clrwdt operands: none operation: 000h wdt, 000h wdt postscaler, 1 to, 1 pd status affected: to , pd encoding: 0000 0000 0000 0100 description: clrwdt instruction resets the watchdog timer. it also resets the postscaler of the wdt. status bits, to and pd , are set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data no operation example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 00h wdt postscaler = 0 to =1 pd =1 pic18f97j60 family ds39762a-page 376 advance information ? 2006 microchip technology inc. comf complement f syntax: comf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f ) dest status affected: n, z encoding: 0001 11da ffff ffff description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: comf reg, 0, 0 before instruction reg = 13h after instruction reg = 13h w=ech cpfseq compare f with w, skip if f = w syntax: cpfseq f {,a} operands: 0 f 255 a [0,1] operation: (f) ? (w), skip if (f) = (w) (unsigned comparison) status affected: none encoding: 0110 001a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if ?f? = w , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfseq reg, 0 nequal : equal : before instruction pc address = here w=? reg = ? after instruction if reg = w; pc = address (equal) if reg w; pc = address (nequal) ? 2006 microchip technology inc. advance information ds39762a-page 377 pic18f97j60 family cpfsgt compare f with w, skip if f > w syntax: cpfsgt f {,a} operands: 0 f 255 a [0,1] operation: (f) ? ( w), skip if (f) > (w) (unsigned comparison) status affected: none encoding: 0110 010a ffff ffff description: compares the contents of data memory location ?f? to the contents of the w by performing an unsigned subtraction. if the contents of ?f? are greater than the contents of wreg , then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfsgt reg, 0 ngreater : greater : before instruction pc = address (here) w= ? after instruction if reg > w; pc = address (greater) if reg w; pc = address (ngreater) cpfslt compare f with w, skip if f < w syntax: cpfslt f {,a} operands: 0 f 255 a [0,1] operation: (f) ? ( w), skip if (f) < (w) (unsigned comparison) status affected: none encoding: 0110 000a ffff ffff description: compares the contents of data memory location ?f? to the contents of w by performing an unsigned subtraction. if the contents of ?f? are less than the contents of w, then the fetched instruction is discarded and a nop is executed instead, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here cpfslt reg, 1 nless : less : before instruction pc = address (here) w= ? after instruction if reg < w; pc = address (less) if reg w; pc = address (nless) pic18f97j60 family ds39762a-page 378 advance information ? 2006 microchip technology inc. daw decimal adjust w register syntax: daw operands: none operation: if [w<3:0> > 9] or [dc = 1 ] then (w<3:0>) + 6 w<3:0>; else (w<3:0>) w<3:0> if [w<7:4> > 9] or [c = 1 ] then (w<7:4>) + 6 w<7:4>; c = 1 ; else (w<7:4>) w<7:4> status affected: c encoding: 0000 0000 0000 0111 description: daw adjusts the eight-bit value in w, resulting from the earlier addition of two variables (each in packed bcd format) and produces a correct packed bcd result. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register w process data write w example 1: daw before instruction w=a5h c=0 dc = 0 after instruction w = 05h c=1 dc = 0 example 2: before instruction w=ceh c=0 dc = 0 after instruction w = 34h c=1 dc = 0 decf decrement f syntax: decf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest status affected: c, dc, n, ov, z encoding: 0000 01da ffff ffff description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: decf cnt, 1, 0 before instruction cnt = 01h z=0 after instruction cnt = 00h z=1 ? 2006 microchip technology inc. advance information ds39762a-page 379 pic18f97j60 family decfsz decrement f, skip if 0 syntax: decfsz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result = 0 status affected: none encoding: 0010 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here decfsz cnt, 1, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt ? 1 if cnt = 0; pc = address (continue) if cnt 0; pc = address (here + 2) dcfsnz decrement f, skip if not 0 syntax: dcfsnz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? 1 dest, skip if result 0 status affected: none encoding: 0100 11da ffff ffff description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here dcfsnz temp, 1, 0 zero : nzero : before instruction temp = ? after instruction temp = temp ? 1, if temp = 0; pc = address (zero) if temp 0; pc = address (nzero) pic18f97j60 family ds39762a-page 380 advance information ? 2006 microchip technology inc. goto unconditional branch syntax: goto k operands: 0 k 1048575 operation: k pc<20:1> status affected: none encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k 19 kkk k 7 kkk kkkk kkkk 0 kkkk 8 description: goto allows an unconditional branch anywhere within entire 2-mbyte memory range. the 20-bit value ?k? is loaded into pc<20:1>. goto is always a two-cycle instruction. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k?<7:0>, no operation read literal ?k?<19:8>, write to pc no operation no operation no operation no operation example: goto there after instruction pc = address (there) incf increment f syntax: incf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest status affected: c, dc, n, ov, z encoding: 0010 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: incf cnt, 1, 0 before instruction cnt = ffh z=0 c=? dc = ? after instruction cnt = 00h z=1 c=1 dc = 1 ? 2006 microchip technology inc. advance information ds39762a-page 381 pic18f97j60 family incfsz increment f, skip if 0 syntax: incfsz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result = 0 status affected: none encoding: 0011 11da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f?. (default) if the result is ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here incfsz cnt, 1, 0 nzero : zero : before instruction pc = address (here) after instruction cnt = cnt + 1 if cnt = 0; pc = address (zero) if cnt 0; pc = address (nzero) infsnz increment f, skip if not 0 syntax: infsnz f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) + 1 dest, skip if result 0 status affected: none encoding: 0100 10da ffff ffff description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if the result is not ? 0 ?, the next instruction which is already fetched is discarded and a nop is executed instead, making it a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here infsnz reg, 1, 0 zero nzero before instruction pc = address (here) after instruction reg = reg + 1 if reg 0; pc = address (nzero) if reg = 0; pc = address (zero) pic18f97j60 family ds39762a-page 382 advance information ? 2006 microchip technology inc. iorlw inclusive or literal with w syntax: iorlw k operands: 0 k 255 operation: (w) .or. k w status affected: n, z encoding: 0000 1001 kkkk kkkk description: the contents of w are ored with the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: iorlw 35h before instruction w=9ah after instruction w=bfh iorwf inclusive or w with f syntax: iorwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) .or. (f) dest status affected: n, z encoding: 0001 00da ffff ffff description: inclusive or w with register ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: iorwf result, 0, 1 before instruction result = 13h w = 91h after instruction result = 13h w = 93h ? 2006 microchip technology inc. advance information ds39762a-page 383 pic18f97j60 family lfsr load fsr syntax: lfsr f, k operands: 0 f 2 0 k 4095 operation: k fsrf status affected: none encoding: 1110 1111 1110 0000 00ff k 7 kkk k 11 kkk kkkk description: the 12-bit literal ?k? is loaded into the file select register pointed to by ?f?. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? msb process data write literal ?k? msb to fsrfh decode read literal ?k? lsb process data write literal ?k? to fsrfl example: lfsr 2, 3abh after instruction fsr2h = 03h fsr2l = abh movf move f syntax: movf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: f dest status affected: n, z encoding: 0101 00da ffff ffff description: the contents of register ?f? are moved to a destination dependent upon the status of ?d?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed back in register ?f? (default). location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write w example: movf reg, 0, 0 before instruction reg = 22h w=ffh after instruction reg = 22h w = 22h pic18f97j60 family ds39762a-page 384 advance information ? 2006 microchip technology inc. movff move f to f syntax: movff f s ,f d operands: 0 f s 4095 0 f d 4095 operation: (f s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1100 1111 ffff ffff ffff ffff ffff s ffff d description: the contents of source register ?f s ? are moved to destination register ?f d ?. location of source ?f s ? can be anywhere in the 4096-byte data space (000h to fffh) and location of destination ?f d ? can also be anywhere from 000h to fffh. either source or destination can be w (a useful special situation). movff is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an i/o port). the movff instruction cannot use the pcl, tosu, tosh or tosl as the destination register words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read register ?f? (src) process data no operation decode no operation no dummy read no operation write register ?f? (dest) example: movff reg1, reg2 before instruction reg1 = 33h reg2 = 11h after instruction reg1 = 33h reg2 = 33h movlb move literal to low nibble in bsr syntax: movlw k operands: 0 k 255 operation: k bsr status affected: none encoding: 0000 0001 kkkk kkkk description: the eight-bit literal ?k? is loaded into the bank select register (bsr). the value of bsr<7:4> always remains ? 0 ? regardless of the value of k 7 :k 4 . words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write literal ?k? to bsr example: movlb 5 before instruction bsr register = 02h after instruction bsr register = 05h ? 2006 microchip technology inc. advance information ds39762a-page 385 pic18f97j60 family movlw move literal to w syntax: movlw k operands: 0 k 255 operation: k w status affected: none encoding: 0000 1110 kkkk kkkk description: the eight-bit literal ?k? is loaded into w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: movlw 5ah after instruction w=5ah movwf move w to f syntax: movwf f {,a} operands: 0 f 255 a [0,1] operation: (w) f status affected: none encoding: 0110 111a ffff ffff description: move data from w to register ?f?. location ?f? can be anywhere in the 256-byte bank. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: movwf reg, 0 before instruction w=4fh reg = ffh after instruction w=4fh reg = 4fh pic18f97j60 family ds39762a-page 386 advance information ? 2006 microchip technology inc. mullw multiply literal with w syntax: mullw k operands: 0 k 255 operation: (w) x k prodh:prodl status affected: none encoding: 0000 1101 kkkk kkkk description: an unsigned multiplication is carried out between the contents of w and the 8-bit literal ?k?. the 16-bit result is placed in prodh:prodl register pair. prodh contains the high byte. w is unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write registers prodh: prodl example: mullw 0c4h before instruction w=e2h prodh = ? prodl = ? after instruction w=e2h prodh = adh prodl = 08h mulwf multiply w with f syntax: mulwf f {,a} operands: 0 f 255 a [0,1] operation: (w) x (f) prodh:prodl status affected: none encoding: 0000 001a ffff ffff description: an unsigned multiplication is carried out between the contents of w and the register file location ?f?. the 16-bit result is stored in the prodh:prodl register pair. prodh contains the high byte. both w and ?f? are unchanged. none of the status flags are affected. note that neither overflow nor carry is possible in this operation. a zero result is possible but not detected. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write registers prodh: prodl example: mulwf reg, 1 before instruction w=c4h reg = b5h prodh = ? prodl = ? after instruction w=c4h reg = b5h prodh = 8ah prodl = 94h ? 2006 microchip technology inc. advance information ds39762a-page 387 pic18f97j60 family negf negate f syntax: negf f {,a} operands: 0 f 255 a [0,1] operation: (f ) + 1 f status affected: n, ov, c, dc, z encoding: 0110 110a ffff ffff description: location ?f? is negated using two?s complement. the result is placed in the data memory location ?f?. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write register ?f? example: negf reg, 1 before instruction reg = 0011 1010 [3ah] after instruction reg = 1100 0110 [c6h] nop no operation syntax: nop operands: none operation: no operation status affected: none encoding: 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx description: no operation. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation example: none. pic18f97j60 family ds39762a-page 388 advance information ? 2006 microchip technology inc. pop pop top of return stack syntax: pop operands: none operation: (tos) bit bucket status affected: none encoding: 0000 0000 0000 0110 description: the tos value is pulled off the return stack and is discarded. the tos value then becomes the previous value that was pushed onto the return stack. this instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation pop tos value no operation example: pop goto new before instruction tos = 0031a2h stack (1 level down) = 014332h after instruction tos = 014332h pc = new push push top of return stack syntax: push operands: none operation: (pc + 2) tos status affected: none encoding: 0000 0000 0000 0101 description: the pc + 2 is pushed onto the top of the return stack. the previous tos value is pushed down on the stack. this instruction allows implementing a software stack by modifying tos and then pushing it onto the return stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode push pc + 2 onto return stack no operation no operation example: push before instruction tos = 345ah pc = 0124h after instruction pc = 0126h tos = 0126h stack (1 level down) = 345ah ? 2006 microchip technology inc. advance information ds39762a-page 389 pic18f97j60 family rcall relative call syntax: rcall n operands: -1024 n 1023 operation: (pc) + 2 tos, (pc) + 2 + 2n pc status affected: none encoding: 1101 1nnn nnnn nnnn description: subroutine call with a jump up to 1k from the current location. first, return address (pc + 2) is pushed onto the stack. then, add the 2?s complement number ?2n? to the pc. since the pc will have incremented to fetch the next instruction, the new address will be pc + 2 + 2n. this instruction is a two-cycle instruction. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?n? push pc to stack process data write to pc no operation no operation no operation no operation example: here rcall jump before instruction pc = address (here) after instruction pc = address (jump) tos = address (here + 2) reset reset syntax: reset operands: none operation: reset all registers and flags that are affected by a mclr reset. status affected: all encoding: 0000 0000 1111 1111 description: this instruction provides a way to execute a mclr reset in software. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode start reset no operation no operation example: reset after instruction registers = reset value flags* = reset value pic18f97j60 family ds39762a-page 390 advance information ? 2006 microchip technology inc. retfie return from interrupt syntax: retfie {s} operands: s [0,1] operation: (tos) pc, 1 gie/gieh or peie/giel, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: gie/gieh, peie/giel. encoding: 0000 0000 0001 000s description: return from interrupt. stack is popped and top-of-stack (tos) is loaded into the pc. interrupts are enabled by setting either the high or low priority global interrupt enable bit. if ?s? = 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation pop pc from stack set gieh or giel no operation no operation no operation no operation example: retfie 1 after interrupt pc = tos w=ws bsr = bsrs status = statuss gie/gieh, peie/giel = 1 retlw return literal to w syntax: retlw k operands: 0 k 255 operation: k w, (tos) pc, pclatu, pclath are unchanged status affected: none encoding: 0000 1100 kkkk kkkk description: w is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). the high address latch (pclath) remains unchanged. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data pop pc from stack, write to w no operation no operation no operation no operation example: call table ; w contains table ; offset value ; w now has ; table value : table addwf pcl ; w = offset retlw k0 ; begin table retlw k1 ; : : retlw kn ; end of table before instruction w = 07h after instruction w = value of kn ? 2006 microchip technology inc. advance information ds39762a-page 391 pic18f97j60 family return return from subroutine syntax: return {s} operands: s [0,1] operation: (tos) pc, if s = 1 (ws) w, (statuss) status, (bsrs) bsr, pclatu, pclath are unchanged status affected: none encoding: 0000 0000 0001 001s description: return from subroutine. the stack is popped and the top of the stack (tos) is loaded into the program counter. if ?s?= 1 , the contents of the shadow registers ws, statuss and bsrs are loaded into their corresponding registers w, status and bsr. if ?s? = 0 , no update of these registers occurs (default). words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation process data pop pc from stack no operation no operation no operation no operation example: return after instruction: pc = tos rlcf rotate left f through carry syntax: rlcf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f pic18f97j60 family ds39762a-page 392 advance information ? 2006 microchip technology inc. rlncf rotate left f (no carry) syntax: rlncf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f ? 2006 microchip technology inc. advance information ds39762a-page 393 pic18f97j60 family rrncf rotate right f (no carry) syntax: rrncf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f pic18f97j60 family ds39762a-page 394 advance information ? 2006 microchip technology inc. sleep enter sleep mode syntax: sleep operands: none operation: 00h wdt, 0 wdt postscaler, 1 to , 0 pd status affected: to , pd encoding: 0000 0000 0000 0011 description: the power-down status bit (pd ) is cleared. the time-out status bit (to ) is set. the watchdog timer and its postscaler are cleared. the processor is put into sleep mode with the oscillator stopped. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode no operation process data go to sleep example: sleep before instruction to =? pd =? after instruction to =1 ? pd =0 ? if wdt causes wake-up, this bit is cleared. subfwb subtract f from w with borrow syntax: subfwb f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) ? (f) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 01da ffff ffff description: subtract register ?f? and carry flag (borrow) from w (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subfwb reg, 1, 0 before instruction reg = 3 w=2 c=1 after instruction reg = ff w=2 c=0 z=0 n = 1 ; result is negative example 2: subfwb reg, 0, 0 before instruction reg = 2 w=5 c=1 after instruction reg = 2 w=3 c=1 z=0 n = 0 ; result is positive example 3: subfwb reg, 1, 0 before instruction reg = 1 w=2 c=0 after instruction reg = 0 w=2 c=1 z = 1 ; result is zero n=0 ? 2006 microchip technology inc. advance information ds39762a-page 395 pic18f97j60 family sublw subtract w from literal syntax: sublw k operands: 0 k 255 operation: k ? (w) w status affected: n, ov, c, dc, z encoding: 0000 1000 kkkk kkkk description: w is subtracted from the eight-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example 1: sublw 02h before instruction w = 01h c=? after instruction w = 01h c = 1 ; result is positive z=0 n=0 example 2: sublw 02h before instruction w = 02h c=? after instruction w = 00h c = 1 ; result is zero z=1 n=0 example 3: sublw 02h before instruction w = 03h c=? after instruction w = ffh ; (2?s complement) c = 0 ; result is negative z=0 n=1 subwf subtract w from f syntax: subwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) dest status affected: n, ov, c, dc, z encoding: 0101 11da ffff ffff description: subtract w from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwf reg, 1, 0 before instruction reg = 3 w=2 c=? after instruction reg = 1 w=2 c = 1 ; result is positive z=0 n=0 example 2: subwf reg, 0, 0 before instruction reg = 2 w=2 c=? after instruction reg = 2 w=0 c = 1 ; result is zero z=1 n=0 example 3: subwf reg, 1, 0 before instruction reg = 1 w=2 c=? after instruction reg = ffh ;(2?s complement) w=2 c = 0 ; result is negative z=0 n=1 pic18f97j60 family ds39762a-page 396 advance information ? 2006 microchip technology inc. subwfb subtract w from f with borrow syntax: subwfb f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f) ? (w) ? (c ) dest status affected: n, ov, c, dc, z encoding: 0101 10da ffff ffff description: subtract w and the carry flag (borrow) from register ?f? (2?s complement method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example 1: subwfb reg, 1, 0 before instruction reg = 19h (0001 1001) w=0dh (0000 1101) c=1 after instruction reg = 0ch (0000 1011) w=0dh (0000 1101) c=1 z=0 n = 0 ; result is positive example 2: subwfb reg, 0, 0 before instruction reg = 1bh (0001 1011) w=1ah (0001 1010) c=0 after instruction reg = 1bh (0001 1011) w = 00h c=1 z = 1 ; result is zero n=0 example 3: subwfb reg, 1, 0 before instruction reg = 03h (0000 0011) w=0eh (0000 1101) c=1 after instruction reg = f5h (1111 0100) ; [2?s comp] w=0eh (0000 1101) c=0 z=0 n = 1 ; result is negative swapf swap f syntax: swapf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> status affected: none encoding: 0011 10da ffff ffff description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset a ddressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: swapf reg, 1, 0 before instruction reg = 53h after instruction reg = 35h ? 2006 microchip technology inc. advance information ds39762a-page 397 pic18f97j60 family tblrd table read syntax: tblrd ( *; *+; *-; +*) operands: none operation: if tblrd *, (prog mem (tblptr)) tablat; tblptr ? no change if tblrd *+, (prog mem (tblptr)) tablat; (tblptr) + 1 tblptr if tblrd *-, (prog mem (tblptr)) tablat; (tblptr) ? 1 tblptr if tblrd +*, (tblptr) + 1 tblptr; (prog mem (tblptr)) tablat status affected: none encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction is used to read the contents of program memory (p.m.). to address the program memory, a pointer called table pointer (tblptr) is used. the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblrd instruction can modify the value of tblptr as follows: ? no change ? post-increment ? post-decrement ? pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read program memory) no operation no operation (write tablat) tblrd table read (continued) example 1: tblrd *+ ; before instruction tablat = 55h tblptr = 00a356h memory(00a356h) = 34h after instruction tablat = 34h tblptr = 00a357h example 2: tblrd +* ; before instruction tablat = aah tblptr = 01a357h memory(01a357h) = 12h memory(01a358h) = 34h after instruction tablat = 34h tblptr = 01a358h pic18f97j60 family ds39762a-page 398 advance information ? 2006 microchip technology inc. tblwt table write syntax: tblwt ( *; *+; *-; +*) operands: none operation: if tblwt*, (tablat) holding register; tblptr ? no change if tblwt*+, (tablat) holding register; (tblptr) + 1 tblptr if tblwt*-, (tablat) holding register; (tblptr) ? 1 tblptr if tblwt+*, (tblptr) + 1 tblptr; (tablat) holding register status affected: none encoding: 0000 0000 0000 11nn nn=0 * =1 *+ =2 *- =3 +* description: this instruction uses the 3 lsbs of tblptr to determine which of the 8 holding registers the tablat is written to. the holding registers are used to program the contents of program memory (p.m.). (refer to section 5.0 ?memory organization? for additional details on programming flash memory.) the tblptr (a 21-bit pointer) points to each byte in the program memory. tblptr has a 2-mbyte address range. the lsb of the tblptr selects which byte of the program memory location to access. tblptr[0] = 0 : least significant byte of program memory word tblptr[0] = 1 : most significant byte of program memory word the tblwt instruction can modify the value of tblptr as follows: ? no change ? post-increment ? post-decrement ? pre-increment words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode no operation no operation no operation no operation no operation (read tablat) no operation no operation (write to holding register) tblwt table write (continued) example 1: tblwt *+; before instruction tablat = 55h tblptr = 00a356h holding register (00a356h) = ffh after instructions (table write completion) tablat = 55h tblptr = 00a357h holding register (00a356h) = 55h example 2: tblwt +*; before instruction tablat = 34h tblptr = 01389ah holding register (01389ah) = ffh holding register (01389bh) = ffh after instruction (table write completion) tablat = 34h tblptr = 01389bh holding register (01389ah) = ffh holding register (01389bh) = 34h ? 2006 microchip technology inc. advance information ds39762a-page 399 pic18f97j60 family tstfsz test f, skip if 0 syntax: tstfsz f {,a} operands: 0 f 255 a [0,1] operation: skip if f = 0 status affected: none encoding: 0110 011a ffff ffff description: if ?f? = 0 , the next instruction fetched during the current instruction execution is discarded and a nop is executed, making this a two-cycle instruction. if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1(2) note: 3 cycles if skip and followed by a 2-word instruction. q cycle activity: q1 q2 q3 q4 decode read register ?f? process data no operation if skip: q1 q2 q3 q4 no operation no operation no operation no operation if skip and followed by 2-word instruction: q1 q2 q3 q4 no operation no operation no operation no operation no operation no operation no operation no operation example: here tstfsz cnt, 1 nzero : zero : before instruction pc = address (here) after instruction if cnt = 00h, pc = address (zero) if cnt 00h, pc = address (nzero) xorlw exclusive or literal with w syntax: xorlw k operands: 0 k 255 operation: (w) .xor. k w status affected: n, z encoding: 0000 1010 kkkk kkkk description: the contents of w are xored with the 8-bit literal ?k?. the result is placed in w. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to w example: xorlw 0afh before instruction w=b5h after instruction w=1ah pic18f97j60 family ds39762a-page 400 advance information ? 2006 microchip technology inc. xorwf exclusive or w with f syntax: xorwf f {,d {,a}} operands: 0 f 255 d [0,1] a [0,1] operation: (w) .xor. (f) dest status affected: n, z encoding: 0001 10da ffff ffff description: exclusive or the contents of w with register ?f?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in the register ?f? (default). if ?a? is ? 0 ?, the access bank is selected. if ?a? is ? 1 ?, the bsr is used to select the gpr bank (default). if ?a? is ? 0 ? and the extended instruction set is enabled, this instruction operates in indexed literal offset addressing mode whenever f 95 (5fh). see section 25.2.3 ?byte-oriented and bit-oriented instructions in indexed literal offset mode? for details. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: xorwf reg, 1, 0 before instruction reg = afh w=b5h after instruction reg = 1ah w=b5h ? 2006 microchip technology inc. advance information ds39762a-page 401 pic18f97j60 family 25.2 extended instruction set in addition to the standard 75 instructions of the pic18 instruction set, the pic18f97j60 family of devices also provide an optional extension to the core cpu function- ality. the added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of indexed literal offset addressing for many of the standard pic18 instructions. the additional features of the extended instruction set are enabled by default on unprogrammed devices. users must properly set or clear the xinst configura- tion bit during programming to enable or disable these features. the instructions in the extended set can all be classified as literal operations, which either manipulate the file select registers, or use them for indexed addressing. two of the instructions, addfsr and subfsr , each have an additional special instantiation for using fsr2. these versions ( addulnk and subulnk ) allow for automatic return after execution. the extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly c. among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. these include: ? dynamic allocation and deallocation of software stack space when entering and leaving subroutines ? function pointer invocation ? software stack pointer manipulation ? manipulation of variables located in a software stack a summary of the instructions in the extended instruc- tion set is provided in table 25-3. detailed descriptions are provided in section 25.2.2 ?extended instruction set? . the opcode field descriptions in table 25-1 (page 360) apply to both the standard and extended pic18 instruction sets. 25.2.1 extended instruction syntax most of the extended instructions use indexed argu- ments, using one of the file select registers and some offset to specify a source or destination register. when an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets (?[ ]?). this is done to indicate that the argument is used as an index or offset. the mpasm? assembler will flag an error if it determines that an index or offset value is not bracketed. when the extended instruction set is enabled, brackets are also used to indicate index arguments in byte-oriented and bit-oriented instructions. this is in addition to other changes in their syntax. for more details, see section 25.2.3.1 ?extended instruction syntax with standard pic18 commands? . table 25-3: extensions to the pic18 instruction set note: the instruction set extension and the indexed literal offset addressing mode were designed for optimizing applications written in c; the user may likely never use these instructions directly in assembler. the syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler. note: in the past, square brackets have been used to denote optional arguments in the pic18 and earlier instruction sets. in this text and going forward, optional arguments are denoted by braces (?{ }?). mnemonic, operands description cycles 16-bit instruction word status affected msb lsb addfsr addulnk callw movsf movss pushl subfsr subulnk f, k k z s , f d z s , z d k f, k k add literal to fsr add literal to fsr2 and return call subroutine using wreg move z s (source) to 1st word f d (destination) 2nd word move z s (source) to 1st word z d (destination) 2nd word store literal at fsr2, decrement fsr2 subtract literal from fsr subtract literal from fsr2 and return 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk none none none none none none none none pic18f97j60 family ds39762a-page 402 advance information ? 2006 microchip technology inc. 25.2.2 extended instruction set addfsr add literal to fsr syntax: addfsr f, k operands: 0 k 63 f [ 0, 1, 2 ] operation: fsr(f) + k fsr(f) status affected: none encoding: 1110 1000 ffkk kkkk description: the 6-bit literal ?k? is added to the contents of the fsr specified by ?f?. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to fsr example: addfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 0422h addulnk add literal to fsr2 and return syntax: addulnk k operands: 0 k 63 operation: fsr2 + k fsr2, (tos) pc status affected: none encoding: 1110 1000 11kk kkkk description: the 6-bit literal ?k? is added to the contents of fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be thought of as a special case of the addfsr instruction, where f = 3 (binary ? 11 ?); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read literal ?k? process data write to fsr no operation no operation no operation no operation example: addulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 0422h pc = (tos) note: all pic18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. if a label is used, the instruction format then becomes: {label} instruction argument(s). ? 2006 microchip technology inc. advance information ds39762a-page 403 pic18f97j60 family callw subroutine call using wreg syntax: callw operands: none operation: (pc + 2) tos, (w) pcl, (pclath) pch, (pclatu) pcu status affected: none encoding: 0000 0000 0001 0100 description first, the return address (pc + 2) is pushed onto the return stack. next, the contents of w are written to pcl; the existing value is discarded. then, the contents of pclath and pclatu are latched into pch and pcu, respectively. the second cycle is executed as a nop instruction while the new next instruction is fetched. unlike call , there is no option to update w, status or bsr. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read wreg push pc to stack no operation no operation no operation no operation no operation example: here callw before instruction pc = address (here) pclath = 10h pclatu = 00h w = 06h after instruction pc = 001006h tos = address (here + 2) pclath = 10h pclatu = 00h w = 06h movsf move indexed to f syntax: movsf [z s ], f d operands: 0 z s 127 0 f d 4095 operation: ((fsr2) + z s ) f d status affected: none encoding: 1st word (source) 2nd word (destin.) 1110 1111 1011 ffff 0zzz ffff zzzz s ffff d description: the contents of the source register are moved to destination register ?f d ?. the actual address of the source register is determined by adding the 7-bit literal offset ?z s ?, in the first word, to the value of fsr2. the address of the destination register is specified by the 12-bit literal ?f d ? in the second word. both addresses can be anywhere in the 4096-byte data space (000h to fffh). the movsf instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode no operation no dummy read no operation write register ?f? (dest) example: movsf [05h], reg2 before instruction fsr2 = 80h contents of 85h = 33h reg2 = 11h after instruction fsr2 = 80h contents of 85h = 33h reg2 = 33h pic18f97j60 family ds39762a-page 404 advance information ? 2006 microchip technology inc. movss move indexed to indexed syntax: movss [z s ], [z d ] operands: 0 z s 127 0 z d 127 operation: ((fsr2) + z s ) ((fsr2) + z d ) status affected: none encoding: 1st word (source) 2nd word (dest.) 1110 1111 1011 xxxx 1zzz xzzz zzzz s zzzz d description the contents of the source register are moved to the destination register. the addresses of the source and destination registers are determined by adding the 7-bit literal offsets ?z s ? or ?z d ?, respectively, to the value of fsr2. both registers can be located anywhere in the 4096-byte data memory space (000h to fffh). the movss instruction cannot use the pcl, tosu, tosh or tosl as the destination register. if the resultant source address points to an indirect addressing register, the value returned will be 00h. if the resultant destination address points to an indirect addressing register, the instruction will execute as a nop . words: 2 cycles: 2 q cycle activity: q1 q2 q3 q4 decode determine source addr determine source addr read source reg decode determine dest addr determine dest addr write to dest reg example: movss [05h], [06h] before instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 11h after instruction fsr2 = 80h contents of 85h = 33h contents of 86h = 33h pushl store literal at fsr2, decrement fsr2 syntax: pushl k operands: 0 k 255 operation: k (fsr2), fsr2 ? 1 fsr2 status affected: none encoding: 1111 1010 kkkk kkkk description: the 8-bit literal ?k? is written to the data memory address specified by fsr2. fsr2 is decremented by 1 after the operation. this instruction allows users to push values onto a software stack. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write to destination example: pushl 08h before instruction fsr2h:fsr2l = 01ech memory (01ech) = 00h after instruction fsr2h:fsr2l = 01ebh memory (01ech) = 08h ? 2006 microchip technology inc. advance information ds39762a-page 405 pic18f97j60 family subfsr subtract literal from fsr syntax: subfsr f, k operands: 0 k 63 f [ 0, 1, 2 ] operation: fsrf ? k fsrf status affected: none encoding: 1110 1001 ffkk kkkk description: the 6-bit literal ?k? is subtracted from the contents of the fsr specified by ?f?. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: subfsr 2, 23h before instruction fsr2 = 03ffh after instruction fsr2 = 03dch subulnk subtract literal from fsr2 and return syntax: subulnk k operands: 0 k 63 operation: fsr2 ? k fsr2 (tos) pc status affected: none encoding: 1110 1001 11kk kkkk description: the 6-bit literal ?k? is subtracted from the contents of the fsr2. a return is then executed by loading the pc with the tos. the instruction takes two cycles to execute; a nop is performed during the second cycle. this may be thought of as a special case of the subfsr instruction, where f = 3 (binary ? 11 ?); it operates only on fsr2. words: 1 cycles: 2 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination no operation no operation no operation no operation example: subulnk 23h before instruction fsr2 = 03ffh pc = 0100h after instruction fsr2 = 03dch pc = (tos) pic18f97j60 family ds39762a-page 406 advance information ? 2006 microchip technology inc. 25.2.3 byte-oriented and bit-oriented instructions in indexed literal offset mode in addition to eight new commands in the extended set, enabling the extended instruction set also enables indexed literal offset addressing ( section 5.6.1 ?indexed addressing with literal offset? ). this has a significant impact on the way that many commands of the standard pic18 instruction set are interpreted. when the extended set is disabled, addresses embed- ded in opcodes are treated as literal memory locations: either as a location in the access bank (a = 0 ) or in a gpr bank designated by the bsr (a = 1 ). when the extended instruction set is enabled and a = 0 , however, a file register argument of 5fh or less is interpreted as an offset from the pointer value in fsr2 and not as a literal address. for practical purposes, this means that all instructions that use the access ram bit as an argument ? that is, all byte-oriented and bit-oriented instructions, or almost half of the core pic18 instruc- tions ? may behave differently when the extended instruction set is enabled. when the content of fsr2 is 00h, the boundaries of the access ram are essentially remapped to their original values. this may be useful in creating backward-compatible code. if this technique is used, it may be necessary to save the value of fsr2 and restore it when moving back and forth between c and assembly routines in order to preserve the stack pointer. users must also keep in mind the syntax requirements of the extended instruction set (see section 25.2.3.1 ?extended instruction syntax with standard pic18 commands? ). although the indexed literal offset mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic opera- tion is carried out on the wrong register. users who are accustomed to the pic18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5fh or less are used for indexed literal offset addressing. representative examples of typical byte-oriented and bit-oriented instructions in the indexed literal offset mode are provided on the following page to show how execution is affected. the operand conditions shown in the examples are applicable to all instructions of these types. 25.2.3.1 extended instruction syntax with standard pic18 commands when the extended instruction set is enabled, the file register argument ?f? in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value ?k?. as already noted, this occurs only when ?f? is less than or equal to 5fh. when an offset value is used, it must be indicated by square brackets (?[ ]?). as with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. omitting the brackets, or using a value greater than 5fh within the brackets, will generate an error in the mpasm assembler. if the index argument is properly bracketed for indexed literal offset addressing, the access ram argument is never specified; it will automatically be assumed to be ? 0 ?. this is in contrast to standard operation (extended instruction set disabled), when ?a? is set on the basis of the target address. declaring the access ram bit in this mode will also generate an error in the mpasm assembler. the destination argument ?d? functions as before. in the latest versions of the mpasm assembler, language support for the extended instruction set must be explicitly invoked. this is done with either the command line option, /y , or the pe directive in the source listing. 25.2.4 considerations when enabling the extended instruction set it is important to note that the extensions to the instruc- tion set may not be beneficial to all users. in particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. additionally, the indexed literal offset addressing mode may create issues with legacy applications written to the pic18 assembler. this is because instructions in the legacy code may attempt to address registers in the access bank below 5fh. since these addresses are interpreted as literal offsets to fsr2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. when porting an application to the pic18f97j60 fam- ily, it is very important to consider the type of code. a large, re-entrant application that is written in c and would benefit from efficient compilation will do well when using the instruction set extensions. legacy applications that heavily use the access bank will most likely not benefit from using the extended instruction set. note: enabling the pic18 instruction set exten- sion may cause legacy applications to behave erratically or fail entirely. ? 2006 microchip technology inc. advance information ds39762a-page 407 pic18f97j60 family addwf add w to indexed (indexed literal offset mode) syntax: addwf [k] {,d} operands: 0 k 95 d [0,1] operation: (w) + ((fsr2) + k) dest status affected: n, ov, c, dc, z encoding: 0010 01d0 kkkk kkkk description: the contents of w are added to the contents of the register indicated by fsr2, offset by the value ?k?. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f? (default). words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write to destination example: addwf [ofst] ,0 before instruction w = 17h ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 20h after instruction w = 37h contents of 0a2ch = 20h bsf bit set indexed (indexed literal offset mode) syntax: bsf [k], b operands: 0 f 95 0 b 7 operation: 1 ((fsr2) + k) status affected: none encoding: 1000 bbb0 kkkk kkkk description: bit ?b? of the register indicated by fsr2, offset by the value ?k?, is set. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read register ?f? process data write to destination example: bsf [flag_ofst], 7 before instruction flag_ofst = 0ah fsr2 = 0a00h contents of 0a0ah = 55h after instruction contents of 0a0ah = d5h setf set indexed (indexed literal offset mode) syntax: setf [k] operands: 0 k 95 operation: ffh ((fsr2) + k) status affected: none encoding: 0110 1000 kkkk kkkk description: the contents of the register indicated by fsr2, offset by ?k?, are set to ffh. words: 1 cycles: 1 q cycle activity: q1 q2 q3 q4 decode read ?k? process data write register example: setf [ofst] before instruction ofst = 2ch fsr2 = 0a00h contents of 0a2ch = 00h after instruction contents of 0a2ch = ffh pic18f97j60 family ds39762a-page 408 advance information ? 2006 microchip technology inc. 25.2.5 special considerations with microchip mplab ? ide tools the latest versions of microchip?s software tools have been designed to fully support the extended instruction set for the pic18f97j60 family. this includes the mplab c18 c compiler, mpasm assembly language and mplab integrated development environment (ide). when selecting a target device for software development, mplab ide will automatically set default configuration bits for that device. the default setting for the xinst configuration bit is ? 0 ?, disabling the extended instruction set and indexed literal offset addressing. for proper execution of applications developed to take advantage of the extended instruction set, xinst must be set during programming. to develop software for the extended instruction set, the user must enable support for the instructions and the indexed addressing mode in their language tool(s). depending on the environment being used, this may be done in several ways: ? a menu option or dialog box within the environment that allows the user to configure the language tool and its settings for the project ? a command line option ? a directive in the source code these options vary between different compilers, assemblers and development environments. users are encouraged to review the documentation accompany- ing their development systems for the appropriate information. ? 2006 microchip technology inc. advance information ds39762a-page 409 pic18f97j60 family 26.0 development support the picmicro ? microcontrollers are supported with a full range of hardware and software development tools: ? integrated development environment - mplab ? ide software ? assemblers/compilers/linkers - mpasm tm assembler - mplab c18 and mplab c30 c compilers -mplink tm object linker/ mplib tm object librarian - mplab asm30 assembler/linker/library ? simulators - mplab sim software simulator ?emulators - mplab ice 2000 in-circuit emulator - mplab ice 4000 in-circuit emulator ? in-circuit debugger - mplab icd 2 ? device programmers - picstart ? plus development programmer - mplab pm3 device programmer - pickit? 2 development programmer ? low-cost demonstration and development boards and evaluation kits 26.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16-bit micro- controller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? visual device initializer for easy register initialization ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as hi-tech software c compilers and iar c compilers the mplab ide allows you to: ? edit your source files (either assembly or c) ? one touch assemble (or compile) and download to picmicro mcu emulator and simulator tools (automatically updates all project information) ? debug using: - source files (assembly or c) - mixed assembly and c - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. pic18f97j60 family ds39762a-page 410 advance information ? 2006 microchip technology inc. 26.2 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for all picmicro mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 26.3 mplab c18 and mplab c30 c compilers the mplab c18 and mplab c30 code development systems are complete ansi c compilers for microchip?s pic18 family of microcontrollers and the dspic30, dspic33 and pic24 family of digital signal controllers. these compilers provide powerful integra- tion capabilities, superior code optimization and ease of use not found with other compilers. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 26.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 26.5 mplab asm30 assembler, linker and librarian mplab asm30 assembler produces relocatable machine code from symbolic assembly language for dspic30f devices. mplab c30 c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire dspic30f instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility 26.6 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the picmicro mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c18 and mplab c30 c compilers, and the mpasm and mplab asm30 assemblers. the software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. ? 2006 microchip technology inc. advance information ds39762a-page 411 pic18f97j60 family 26.7 mplab ice 2000 high-performance in-circuit emulator the mplab ice 2000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for picmicro microcontrollers. software control of the mplab ice 2000 in-circuit emulator is advanced by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 2000 is a full-featured emulator system with enhanced trace, trigger and data monitor- ing features. interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. the architecture of the mplab ice 2000 in-circuit emulator allows expansion to support new picmicro microcontrollers. the mplab ice 2000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft ? windows ? 32-bit operating system were chosen to best make these features available in a simple, unified application. 26.8 mplab ice 4000 high-performance in-circuit emulator the mplab ice 4000 in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for high-end picmicro mcus and dspic dscs. software control of the mplab ice 4000 in-circuit emulator is provided by the mplab integrated development environment, which allows editing, building, downloading and source debugging from a single environment. the mplab ice 4000 is a premium emulator system, providing the features of mplab ice 2000, but with increased emulation memory and high-speed perfor- mance for dspic30f and pic18xxxx devices. its advanced emulator features include complex triggering and timing, and up to 2 mb of emulation memory. the mplab ice 4000 in-circuit emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. the pc platform and microsoft windows 32-bit operating system were chosen to best make these features available in a simple, unified application. 26.9 mplab icd 2 in-circuit debugger microchip?s in-circuit debugger, mplab icd 2, is a powerful, low-cost, run-time development tool, connecting to the host pc via an rs-232 or high-speed usb interface. this tool is based on the flash picmicro mcus and can be used to develop for these and other picmicro mcus and dspic dscs. the mplab icd 2 utilizes the in-circuit debugging capability built into the flash devices. this feature, along with microchip?s in-circuit serial programming tm (icsp tm ) protocol, offers cost-effective, in-circuit flash debugging from the graphical user interface of the mplab integrated development environment. this enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and cpu status and peripheral registers. running at full speed enables testing hardware and applications in real time. mplab icd 2 also serves as a development programmer for selected picmicro devices. 26.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program picmicro devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an sd/mmc card for file storage and secure data applications. pic18f97j60 family ds39762a-page 412 advance information ? 2006 microchip technology inc. 26.11 picstart plus development programmer the picstart plus development programmer is an easy-to-use, low-cost, prototype programmer. it connects to the pc via a com (rs-232) port. mplab integrated development environment software makes using the programmer simple and efficient. the picstart plus development programmer supports most picmicro devices in dip packages up to 40 pins. larger pin count devices, such as the pic16c92x and pic17c76x, may be supported with an adapter socket. the picstart plus development programmer is ce compliant. 26.12 pickit 2 development programmer the pickit? 2 development programmer is a low-cost programmer with an easy-to-use interface for pro- gramming many of microchip?s baseline, mid-range and pic18f families of flash memory microcontrollers. the pickit 2 starter kit includes a prototyping develop- ment board, twelve sequential lessons, software and hi-tech?s picc lite c compiler, and is designed to help get up to speed quickly using pic ? micro- controllers. the kit provides everything needed to program, evaluate and develop applications using microchip?s powerful, mid-range flash memory family of microcontrollers. 26.13 demonstration, development and evaluation boards a wide variety of demonstration, development and evaluation boards for various picmicro mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart ? battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. check the microchip web page (www.microchip.com) and the latest ?product selector guide? (ds00148) for the complete list of demonstration, development and evaluation kits. ? 2006 microchip technology inc. advance information ds39762a-page 413 pic18f97j60 family 27.0 electrical characteristics absolute maximum ratings (?) ambient temperature under bias................................................................................................. ............-40c to +100c storage temperature ............................................................................................................ .................. -65c to +150c voltage on any digital-only input pin or mclr with respect to v ss (except v dd ) ........................................ -0.3v to 6.0v voltage on any combined digital and analog pin with respect to v ss ............................................. -0.3v to (v dd + 0.3v) voltage on v ddcore with respect to v ss ................................................................................................... -0.3v to 2.75v voltage on v dd with respect to v ss ........................................................................................................... -0.3v to 3.6v total power dissipation (note 1) ............................................................................................................................... 1.0w maximum current out of v ss pin ........................................................................................................................... 300 ma maximum current into v dd pin ........................................................................................................................... ...250 ma input clamp current, i ik (v i < 0 or v i > v dd ) (note 3) ........................................................................................................ 0ma output clamp current, i ok (v o < 0 or v o > v dd ) (note 3) ................................................................................................ 0ma maximum output current sunk by any portb and portc i/o pins.................................................................... ..25 ma maximum output current sunk by any portd, porte and portj i/o pins ..........................................................8 ma maximum output current sunk by any porta (2) , portf, portg and porth i/o pins ........................................2 ma maximum output current sourced by any portb and portc i/o pins................................................................. 25 ma maximum output current sourced by any portd, porte and portj i/o pins .....................................................8 ma maximum output current sourced by any porta (2) , portf, portg and porth i/o pins ...................................2 ma maximum current sunk by all ports combined.......................................................................................................200 ma maximum current sourced by all ports combined.................................................................................. ................200 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? i oh } + {(v dd ? v oh ) x i oh } + (v ol x i ol ) + (v tpout x i tpout ) 2: the exceptions are ra0:ra1, which are capable of directly driving leds up to 8 ma. 3: no clamping diodes are present. ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. pic18f97j60 family ds39762a-page 414 advance information ? 2006 microchip technology inc. figure 27-1: pic18f97j60 family voltag e-frequency graph, regulator enabled (envreg tied to v dd ) figure 27-2: pic18f97j60 family voltage-frequency graph, regulator disabled (envreg tied to v ss ) frequency voltage (v dd ) (1) 4.0v 2.0v 41.6667 mhz 3.5v 3.0v 2.5v 3.6v pic18f6xj6x/8xj6x/9xj6x 2.7v 0 note 1: when the on-chip regulator is enabled, its bor circuit will automatically trigger a device reset before v dd reaches a level at which full-speed operation is not possible. frequency voltage (v ddcore ) (1) 3.00v 2.00v 41.6667 mhz 2.75v 2.50v 2.25v 2.7v 4 mhz 2.35v note 1: when the on-chip voltage regulator is disabled, v dd and v ddcore must be maintained so that v ddcore v dd 3.6v. for frequencies between 4 mhz and 41.6667 mhz, f max = (107.619 mhz/v) * (v ddcore ? 2v) + 4 mhz pic18f6xj6x/8xj6x/9xj6x ? 2006 microchip technology inc. advance information ds39762a-page 415 pic18f97j60 family 27.1 dc characteristics: supply voltage, pic18f97j60 family (industrial) pic18f97j60 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min typ max units conditions d001 v dd supply voltage v ddcore 2.65 ? ? 3.6 3.6 v v envreg = 0 envreg = 1 d001b v ddcore external supply for microcontroller core 2.00 ? 2.70 v d001c av dd analog supply voltage v dd ? 0.3 ? v dd + 0.3 v d002 v dr ram data retention voltage (1) 1.5 ? ? v d003 v por v dd power-on reset voltage ??tbdvsee section 4.3 ?power-on reset (por)? for details d004 s vdd v dd rise rate to ensure internal power-on reset 0.05 ? ? v/ms see section 4.3 ?power-on reset (por)? for details note 1: this is the limit to which v dd can be lowered in sleep mode, or during a device reset, without losing ram data. pic18f97j60 family ds39762a-page 416 advance information ? 2006 microchip technology inc. 27.2 dc characteristics: power-down and supply current pic18f97j60 family (industrial) pic18f97j60 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions power-down current (i pd ) (1) all devices tbd tbd a -40c v dd = 2.0v, v ddcore = 2.0v, envreg = 0 ( sleep mode) tbd tbd a +25c tbd tbd a +85c all devices tbd tbd a -40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 ( sleep mode) tbd tbd a +25c tbd tbd a +85c all devices tbd tbd a -40c v dd = 3.3v, envreg = 1 ( sleep mode) tbd tbd a +25c tbd tbd a +85c legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, etc.). 2: the supply current is mainly a function of operating volt age, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. ? 2006 microchip technology inc. advance information ds39762a-page 417 pic18f97j60 family supply current (i dd ) (2,3) all devices tbd tbd a-40c v dd = 2.0v, v ddcore = 2.0v, envreg = 0 f osc = 31 khz ( rc_run mode, internal oscillator source) tbd tbd a +25c tbd tbd a +85c all devices tbd tbd a-40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 tbd tbd a +25c tbd tbd a +85c all devices tbd tbd a-40c v dd = 3.3v, envreg = 1 tbd tbd a +25c tbd tbd a +85c all devices tbd tbd a-40c v dd = 2.0v, v ddcore = 2.0v, envreg = 0 f osc = 31 khz ( rc_idle mode, internal oscillator source) tbd tbd a +25c tbd tbd a +85c all devices tbd tbd a-40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 tbd tbd a +25c tbd tbd a +85c all devices tbd tbd a-40c v dd = 3.3v, envreg = 1 tbd tbd a +25c tbd tbd a +85c 27.2 dc characteristics: power-down and supply current pic18f97j60 family (industrial) (continued) pic18f97j60 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, etc.). 2: the supply current is mainly a function of operating volt age, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. pic18f97j60 family ds39762a-page 418 advance information ? 2006 microchip technology inc. supply current (i dd ) (2,3) all devices tbd tbd a-40c v dd = 2.0v, v ddcore = 2.0v, envreg = 0 f osc = 1 mh z ( pri_run mode, ec oscillator) tbd tbd a +25c tbd tbd a +85c all devices tbd tbd a-40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 tbd tbd a +25c tbd tbd a +85c all devices tbd tbd ma -40c v dd = 3.3v, envreg = 1 tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 f osc = 25 mhz ( pri_run mode, ec oscillator) tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 3.3v, envreg = 1 tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 f osc = 41.6667 mh z ( pri_run mode, ec oscillator) tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 3.3v, envreg = 1 tbd tbd ma +25c tbd tbd ma +85c 27.2 dc characteristics: power-down and supply current pic18f97j60 family (industrial) (continued) pic18f97j60 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, etc.). 2: the supply current is mainly a function of operating volt age, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. ? 2006 microchip technology inc. advance information ds39762a-page 419 pic18f97j60 family supply current (i dd ) (2) all devices tbd tbd ma -40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 f osc = 25 mh z . 2.7778 mhz internal ( pri_run hs mode) tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 3.3v, envreg = 1 f osc = 25 mh z , 2.7778 mhz internal ( pri_run hs mode) tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 f osc = 25 mh z . 13.8889 mhz internal ( pri_run hspll mode) tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 3.3v, envreg = 1 f osc = 25 mh z , 13.8889 mhz internal ( pri_run hspll mode) tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 f osc = 25 mh z . 25 mhz internal ( pri_run hs mode) tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 3.3v, envreg = 1 f osc = 25 mh z , 25 mhz internal ( pri_run hs mode) tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 f osc = 25 mh z , 41.6667 mhz internal ( pri_run hspll mode) tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 3.3v, envreg = 1 f osc = 25 mh z , 41.6667 mhz internal ( pri_run hspll mode) tbd tbd ma +25c tbd tbd ma +85c 27.2 dc characteristics: power-down and supply current pic18f97j60 family (industrial) (continued) pic18f97j60 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, etc.). 2: the supply current is mainly a function of operating volt age, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. pic18f97j60 family ds39762a-page 420 advance information ? 2006 microchip technology inc. supply current (i dd ) (2,3) all devices tbd tbd a-40c v dd = 2.0v, v ddcore = 2.0v, envreg = 0 f osc = 1 mhz ( pri_idle mode, ec oscillator) tbd tbd a +25c tbd tbd a +85c all devices tbd tbd a-40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 tbd tbd a +25c tbd tbd a +85c all devices tbd tbd a-40c v dd = 3.3v, envreg = 1 tbd tbd a +25c tbd tbd a +85c all devices tbd tbd a-40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 f osc = 25 mh z ( pri_idle mode, ec oscillator ) tbd tbd a +25c tbd tbd a +85c all devices tbd tbd ma -40c v dd = 3.3v, envreg = 1 tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 f osc = 41.6667 mhz ( pri_idle mode, ec oscillator) tbd tbd ma +25c tbd tbd ma +85c all devices tbd tbd ma -40c v dd = 3.3v, envreg = 1 tbd tbd ma +25c tbd tbd ma +85c 27.2 dc characteristics: power-down and supply current pic18f97j60 family (industrial) (continued) pic18f97j60 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, etc.). 2: the supply current is mainly a function of operating volt age, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. ? 2006 microchip technology inc. advance information ds39762a-page 421 pic18f97j60 family supply current (i dd ) (2,3) all devices tbd tbd a-10c v dd = 2.0v, v ddcore = 2.0v, envreg = 0 f osc = 32 khz (4) ( sec_run mode, timer1 as clock) tbd tbd a +25c tbd tbd a +70c all devices tbd tbd a-10c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 tbd tbd a +25c tbd tbd a +70c all devices tbd tbd a-10c v dd = 3.3v, envreg = 1 tbd tbd a +25c tbd tbd a +70c all devices tbd tbd a-10c v dd = 2.0v, v ddcore = 2.0v, envreg = 0 f osc = 32 khz (4) ( sec_idle mode, timer1 as clock) tbd tbd a +25c tbd tbd a +70c all devices tbd tbd a-10c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 tbd tbd a +25c tbd tbd a +70c all devices tbd tbd a-10c v dd = 3.3v, envreg = 1 tbd tbd a +25c tbd tbd a +70c 27.2 dc characteristics: power-down and supply current pic18f97j60 family (industrial) (continued) pic18f97j60 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, etc.). 2: the supply current is mainly a function of operating volt age, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. pic18f97j60 family ds39762a-page 422 advance information ? 2006 microchip technology inc. module differential currents ( i wdt , i oscb , i ad , i eth ) d022 ( i wdt ) watchdog timer tbd tbd a-40c v dd = 2.0v, v ddcore = 2.0v, envreg = 0 tbd tbd a +25c tbd tbd a +85c tbd tbd a-40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 tbd tbd a +25c tbd tbd a +85c tbd tbd a-40c v dd = 3.3v, envreg = 1 tbd tbd a +25c tbd tbd a +85c d025 ( i oscb ) timer1 oscillator tbd tbd a-40c v dd = 2.0v, v ddcore = 2.0v, envreg = 0 32 khz on timer1 (3) tbd tbd a +25c tbd tbd a +85c tbd tbd a-40c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 32 khz on timer1 (3) tbd tbd a +25c tbd tbd a +85c tbd tbd a-40c v dd = 3.3v, envreg = 1 32 khz on timer1 (3) tbd tbd a +25c tbd tbd a +85c d026 ( i ad ) a/d converter v dd = 2.0v, v ddcore = 2.0v, envreg = 0 a/d on, not converting tbd tbd a -40c to +85c v dd = 2.5v, v ddcore = 2.5v, envreg = 0 tbd tbd a -40c to +85c tbd tbd a -40c to +85c v dd = 3.3v, envreg = 1 d027 i eth ethernet module v dd = 3.3v, envreg = 1 includes current sunk through t pout + and t pout -, leda and ledb disabled 140 tbd ma -40c to +85c 27.2 dc characteristics: power-down and supply current pic18f97j60 family (industrial) (continued) pic18f97j60 family (industrial) standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. device typ max units conditions legend: tbd = to be determined note 1: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd or v ss and all features that add delta current disabled (such as wdt, timer1 oscillator, etc.). 2: the supply current is mainly a function of operating volt age, frequency and mode. other factors, such as i/o pin loading and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on the current consumption. the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-ra il; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt enabled/disabled as specified. 3: standard, low-cost 32 khz crystals have an operating temper ature range of -10c to + 70c. extended temperature crystals are available at a much higher cost. ? 2006 microchip technology inc. advance information ds39762a-page 423 pic18f97j60 family 27.3 dc characteristics: pic18f97j60 family (industrial) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min max units conditions v il input low voltage i/o ports: d030 with ttl buffer v ss 0.15 v dd v d031 with schmitt trigger buffer v ss 0.2 v dd v d032 mclr v ss 0.2 v dd v d033 osc1 v ss 0.3 v dd v hs, hspll modes d033a d034 osc1 t13cki v ss v ss 0.2 v dd 0.3 v v ec modes v ih input high voltage i/o ports: d040 with ttl buffer 0.25 v dd + 0.8v v dd v d041 with schmitt trigger buffer 0.8 v dd v dd v d042 mclr 0.8 v dd v dd v d043 osc1 0.7 v dd v dd v hs, hspll modes d043a d044 osc1 t13cki 0.8 v dd 1.6 v dd v dd v v ec mode i il input leakage current (1) d060 i/o ports ? 1 av ss v pin v dd , pin at high-impedance d061 mclr ? 1 avss v pin v dd d063 osc1 ? 1 avss v pin v dd i pu weak pull-up current d070 i purb portb weak pull-up current 30 250 av dd = 3.3v, v pin = v ss note 1: negative current is defined as current sourced by the pin. pic18f97j60 family ds39762a-page 424 advance information ? 2006 microchip technology inc. v ol output low voltage d080 i/o ports ? 0.6 v i ol = 8.5 ma, v dd = 3.3v, -40 c to +85 c d083 osc2/clko (ec, ecpll modes) ?0.6vi ol = 1.6 ma, v dd = 3.3v, -40 c to +85 c v oh output high voltage (1) d090 i/o ports v dd ? 0.7 ? v i oh = -3.0 ma, v dd = 3.3v, -40 c to +85 c d092 osc2/clko (internal rc, ec, ecpll modes) v dd ? 0.7 ? v i oh = -1.3 ma, v dd = 3.3v, -40 c to +85 c capacitive loading specs on output pins d100 cosc2 osc2 pin ? 15 pf in hs mode when external clock is used to drive osc1 d101 c io all i/o pins and osc2 (in internal rc mode, ec, ecpll) ? 50 pf to meet the ac timing specifications d102 c b sclx, sdax ? 400 pf i 2 c? specification 27.3 dc characteristics: pic18f97j60 family (industrial) (continued) dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. symbol characteristic min max units conditions note 1: negative current is defined as current sourced by the pin. ? 2006 microchip technology inc. advance information ds39762a-page 425 pic18f97j60 family table 27-1: memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial param no. sym characteristic min typ? max units conditions program flash memory d130 e p cell endurance 100 1k ? e/w -40 c to +85 c d131 v pr v dd for read v min ?3.6vv min = minimum operating voltage d132b v pew v dd for self-timed write v min ?3.6vv min = minimum operating voltage d133a t iw self-timed write cycle time ? 2.8 ? ms d134 t retd characteristic retention 20 ? ? year provided no other specifications are violated d135 i ddp supply current during programming ?10?ma ? data in ?typ? column is at 3.3v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. pic18f97j60 family ds39762a-page 426 advance information ? 2006 microchip technology inc. table 27-2: comparator specifications table 27-3: voltage reference specifications table 27-4: internal voltage regulator specifications operating conditions: 3.0v v dd 3.6v, -40c t a +85c (unless otherwise stated) param no. sym characteristics min typ max units comments d300 v ioff input offset voltage ? 5.0 10 mv d301 v icm input common mode voltage* 0 ? av dd ? 1.5 v d302 cmrr common mode rejection ratio* 55 ? ? db 300 t resp response time (1)* ? 150 400 ns 301 t mc 2 ov comparator mode change to output valid* ?? 10 s * these parameters are characterized but not tested. note 1: response time measured with one comparator input at (av dd ? 1.5)/2, while the other input transitions from v ss to av dd . operating conditions: 3.0v v dd 3.6v, -40c t a +85c (unless otherwise stated) param no. sym characteristics min typ max units comments d310 v res resolution v dd /24 ? v dd /32 lsb d311 vr aa absolute accuracy ? ? 1/2 lsb d312 vr ur unit resistor value (r) ? 2k ? 310 t set settling time (1) ? ? 10 s note 1: settling time measured while cvrr = 1 and cvr3:cvr0 transitions from ? 0000 ? to ? 1111 ?. operating conditions: -40c t a +85c (unless otherwise stated) param no. sym characteristics min typ max units comments v rgout regulator output voltage ? 2.5 ? v c efc external filter capacitor value 110? f capacitor must be low series resistance * these parameters are characterized but not tested. parameter numbers not yet assigned for these specifications. ? 2006 microchip technology inc. advance information ds39762a-page 427 pic18f97j60 family 27.4 ac (timing) characteristics 27.4.1 timing parameter symbology the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency t time lowercase letters (pp) and their meanings: pp cc eccp1 osc osc1 ck clko rd rd cs cs x rw rd or wr di sdix sc sckx do sdox ss ss x dt data in t0 t0cki io i/o port t1 t13cki mc mclr wr wr uppercase letters and their meanings: s f fall p period hhigh rrise i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition pic18f97j60 family ds39762a-page 428 advance information ? 2006 microchip technology inc. 27.4.2 timing conditions the temperature and voltages specified in table 27-5 apply to all timing specifications unless otherwise noted. figure 27-3 specifies the load conditions for the timing specifications. table 27-5: temperature and voltage specifications ? ac figure 27-3: load conditions for devi ce timing specifications ac characteristics standard operating conditions (unless otherwise stated) operating temperature -40c t a +85c for industrial operating voltage v dd range as described in dc spec section 27.1 and section 27.3 . v dd /2 c l r l pin pin v ss v ss c l r l =464 c l = 50 pf for all pins except osc2/clko and including d and e outputs as ports c l = 15 pf for osc2/clko load condition 1 load condition 2 ? 2006 microchip technology inc. advance information ds39762a-page 429 pic18f97j60 family 27.4.3 timing diagrams and specifications figure 27-4: external clock timing (all modes except pll) table 27-6: external clock timing requirements osc1 clko q4 q1 q2 q3 q4 q1 1 2 3 3 4 4 param. no. symbol characteristic min max units conditions 1a f osc external clki frequency (1) dc 41.6667 mhz ec oscillator mode oscillator frequency (1) 6 25 mhz hs oscillator mode 1t osc external clki period (1) 24 ? ns hs oscillator mode oscillator period (1) 40 167 ns hs oscillator mode 2t cy instruction cycle time (1) 96 ? ns t cy = 4/f osc , industrial 3t os l, t os h external clock in (osc1) high or low time 10 ? ns ec oscillator mode 4t os r, t os f external clock in (osc1) rise or fall time ? 7.5 ns ec oscillator mode 5 clock frequency tolerance ? 50 ppm ethernet module enabled note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period for all configurations except pll. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices are tested to operate at ?min.? values with an external clock applied to the osc1/clki pin. when an external clock input is used, the ?max.? cycle time limit is ?dc? (no clock) for all devices. pic18f97j60 family ds39762a-page 430 advance information ? 2006 microchip technology inc. table 27-7: pll clock timing specifications (v dd = 2.6v to 3.6v) table 27-8: ac characteristics: internal rc accuracy pic18f97j60 family (industrial) param no. sym characteristic min typ? max units conditions f10 f osc oscillator frequency range 8 ? 25 mhz hspll mode 8 ? 37.5 mhz ecpll mode f11 f sys on-chip vco system frequency 20 ? 62.5 mhz f12 t rc pll start-up time (lock time) ? ? 2 ms f13 clk clko stability (jitter) -2 ? +2 % ? data in ?typ? column is at 3.3v, 25 c, unless otherwise stated. these parameters are for design guidance only and are not tested. param no. characteristic min typ max units conditions intrc accuracy @ freq = 31 khz (1) 21.7 ? 40.3 khz note 1: intrc frequency changes as v ddcore changes. ? 2006 microchip technology inc. advance information ds39762a-page 431 pic18f97j60 family figure 27-5: clko and i/o timing table 27-9: clko and i/o timing requirements note: refer to figure 27-3 for load conditions. osc1 clko i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 19 18 15 11 12 16 old value new value param no. symbol characteristic min typ max units conditions 10 t os h2 ck losc1 to clko ? 75 200 ns 11 t os h2 ck hosc1 to clko ? 75 200 ns 12 t ck rclko rise time ? 15 30 ns 13 t ck fclko fall time ? 15 30 ns 14 t ck l2 io vclko to port out valid ? ? 0.5 t cy + 20 ns 15 t io v2 ck h port in valid before clko 0.25 t cy + 25 ? ? ns 16 t ck h2 io i port in hold after clko 0??ns 17 t os h2 io vosc1 (q1 cycle) to port out valid ? 50 150 ns 18 t os h2 io iosc1 (q2 cycle) to port input invalid (i/o in hold time) 100 ? ? ns 19 t io v2 os h port input valid to osc1 (i/o in setup time) 0??ns 20 t io r port output rise time ? ? 6 ns 21 t io f port output fall time ? ? 5 ns 22? t inp intx pin high or low time t cy ??ns 23? t rbp rb7:rb4 change intx high or low time t cy ??ns ? these parameters are asynchronous events not related to any internal clock edges. pic18f97j60 family ds39762a-page 432 advance information ? 2006 microchip technology inc. figure 27-6: program memo ry read timing diagram table 27-10: clko and i/o timing requirements param. no symbol characteristics min typ max units 150 tadv2all address out valid to ale (address setup time) 0.25 t cy ? 10 ? ? ns 151 tall2adl ale to address out invalid (address hold time) 5??ns 155 tall2oel ale to oe 10 0.125 t cy ?ns 160 tadz2oel ad high-z to oe (bus release to oe )0??ns 161 toeh2add oe to ad driven 0.125 t cy ? 5 ? ? ns 162 tadv2oeh least significant data valid before oe (data setup time) 20 ? ? ns 163 toeh2adl oe to data in invalid (data hold time) 0 ? ? ns 164 talh2all ale pulse width ? t cy ?ns 165 toel2oeh oe pulse width 0.5 t cy ? 5 0.5 t cy ?ns 166 talh2alh ale to ale (cycle time) ? 0.25 t cy ?ns 167 tacc address valid to data valid 0.75 t cy ? 25 ? ? ns 168 toe oe to data valid ? 0.5 t cy ? 25 ns 169 tall2oeh ale to oe 0.625 t cy ? 10 ? 0.625 t cy + 10 ns 171 talh2csl chip enable active to ale 0.25 t cy ? 20 ? ? ns 171a tubl2oeh ad valid to chip enable active ? ? 10 ns q1 q2 q3 q4 q1 q2 osc1 ale oe address data from external 164 166 160 165 161 151 162 163 ad<15:0> 167 168 155 address address 150 a<19:16> address 169 ba0 ce 171 171a operating conditions: 2.0v < v cc < 3.6v, -40c < t a < +125c unless otherwise stated. ? 2006 microchip technology inc. advance information ds39762a-page 433 pic18f97j60 family figure 27-7: program memory write timing diagram table 27-11: program memory write timing requirements param. no symbol characteristics min typ max units 150 tadv2all address out valid to ale (address setup time) 0.25 t cy ? 10 ? ? ns 151 tall2adl ale to address out invalid (address hold time) 5 ? ? ns 153 twrh2adl wrn to data out invalid (data hold time) 5 ? ? ns 154 twrl wrn pulse width 0.5 t cy ? 5 0.5 t cy ?ns 156 tadv2wrh data valid before wrn (data setup time) 0.5 t cy ? 10 ? ? ns 157 tbsv2wrl byte select valid before wrn (byte select setup time) 0.25 t cy ??ns 157a twrh2bsi wrn to byte select invalid (byte select hold time) 0.125 t cy ? 5 ? ? ns 166 talh2alh ale to ale (cycle time) ? 0.25 t cy ?ns 171 talh2csl chip enable active to ale 0.25 t cy ? 20 ? ? ns 171a tubl2oeh ad valid to chip enable active ? ? 10 ns q1 q2 q3 q4 q1 q2 osc1 ale address data 156 150 151 153 ad<15:0> address wrh or wrl ub or lb 157 154 157a address a<19:16> address ba0 166 ce 171 171a operating conditions: 2.0v < v cc < 3.6v, -40c < t a < +125c unless otherwise stated. pic18f97j60 family ds39762a-page 434 advance information ? 2006 microchip technology inc. figure 27-8: reset, watchdog timer, oscillator start-up timer and power-up timer timing figure 27-9: brown-out reset timing table 27-12: reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements param. no. symbol characteristic min typ max units conditions 30 t mc lmclr pulse width (low) 2 ? ? s 31 t wdt watchdog timer time-out period (no postscaler) 2.8 4.1 5.4 ms 32 t ost oscillation start-up timer period 1024 t osc ? 1024 t osc ?t osc = osc1 period 33 t pwrt power-up timer period 46.2 66 85.8 ms 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ?2? s 38 t csd cpu start-up time ? tbd ? s legend: tbd = to be determined v dd mclr internal por pwrt time-out oscillator time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 note: refer to figure 27-3 for load conditions. v dd bv dd 35 v bgap = 1.2v v irvst enable internal internal reference 36 reference voltage voltage stable ? 2006 microchip technology inc. advance information ds39762a-page 435 pic18f97j60 family figure 27-10: timer0 and timer1 external clock timings table 27-13: timer0 and timer1 external clock requirements note: refer to figure 27-3 for load conditions. 46 47 45 48 41 42 40 t0cki t1oso/t13cki tmr0 or tmr1 param no. symbol characteristic min max units conditions 40 t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 41 t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 42 t t 0p t0cki period no prescaler t cy + 10 ? ns with prescaler greater of: 20 ns or (t cy + 40)/n ?nsn = prescale value (1, 2, 4,..., 256) 45 t t 1h t13cki high time synchronous, no prescaler 0.5 t cy + 20 ? ns synchronous, with prescaler 10 ? ns asynchronous 30 ? ns 46 t t 1l t13cki low time synchronous, no prescaler 0.5 t cy + 5 ? ns synchronous, with prescaler 10 ? ns asynchronous 30 ? ns 47 t t 1p t13cki input period synchronous greater of: 20 ns or (t cy + 40)/n ?nsn = prescale value (1, 2, 4, 8) asynchronous 60 ? ns f t 1 t13cki oscillator input frequency range dc 50 khz 48 t cke 2 tmr i delay from external t13cki clock edge to timer increment 2 t osc 7 t osc ? pic18f97j60 family ds39762a-page 436 advance information ? 2006 microchip technology inc. figure 27-11: capture/compare/pwm timing s (including eccp modules) table 27-14: capture/compare/pwm requ irements (including eccp modules) table 27-15: parallel slave port requirements note: refer to figure 27-3 for load conditions. ccpx (capture mode) 50 51 52 ccpx 53 54 (compare or pwm mode) param no. symbol characteristic min max units conditions 50 t cc l ccpx input low time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 51 t cc h ccpx input high time no prescaler 0.5 t cy + 20 ? ns with prescaler 10 ? ns 52 t cc p ccpx input period 3 t cy + 40 n ? ns n = prescale value (1, 4 or 16) 53 t cc r ccpx output fall time ? 25 ns 54 t cc f ccpx output fall time ? 25 ns param. no. symbol characteristic min max units conditions 62 tdtv2wrh data in valid before wr or cs (setup time) 20 ? ns 63 twrh2dti wr or cs to data?in invalid (hold time) 20 ? ns 64 trdl2dtv rd and cs to data?out valid ? 80 ns 65 trdh2dti rd or cs to data?out invalid 10 30 ns 66 tibfinh inhibit of the ibf flag bit being cleared from wr or cs ?3 t cy ? 2006 microchip technology inc. advance information ds39762a-page 437 pic18f97j60 family figure 27-12: example spi master mode timing (cke = 0 ) table 27-16: example spi mode requirements (master mode, cke = 0 ) ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix 70 71 72 73 74 75, 76 78 79 80 79 78 msb lsb bit 6 - - - - - - 1 msb in lsb in bit 6 - - - - 1 note: refer to figure 27-3 for load conditions. param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input t cy ?ns 71 t sc h sckx input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sckx input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 100 ? ns 75 t do r sdox data output rise time ? 25 ns 76 t do f sdox data output fall time ? 25 ns 78 t sc r sckx output rise time (master mode) ? 25 ns 79 t sc f sckx output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ? 50 ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. pic18f97j60 family ds39762a-page 438 advance information ? 2006 microchip technology inc. figure 27-13: example spi master mode timing (cke = 1 ) table 27-17: example spi mode requirements (master mode, cke = 1 ) ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix 81 71 72 74 75, 76 78 80 msb 79 73 msb in bit 6 - - - - - - 1 lsb in bit 6 - - - - 1 lsb note: refer to figure 27-3 for load conditions. param. no. symbol characteristic min max units conditions 71 t sc h sckx input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sckx input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the 1st clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 100 ? ns 75 t do r sdox data output rise time ? 25 ns 76 t do f sdox data output fall time ? 25 ns 78 t sc r sckx output rise time (master mode) ? 25 ns 79 t sc f sckx output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ? 50 ns 81 t do v2 sc h, t do v2 sc l sdox data output setup to sckx edge t cy ?ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ? 2006 microchip technology inc. advance information ds39762a-page 439 pic18f97j60 family figure 27-14: example spi slave mode timing (cke = 0 ) table 27-18: example spi mode requirements (slave mode timing, cke = 0 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input t cy ?ns 71 t sc h sckx input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sckx input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73 t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 100 ? ns 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 100 ? ns 75 t do r sdox data output rise time ? 25 ns 76 t do f sdox data output fall time ? 25 ns 77 t ss h2 do z ssx to sdox output high-impedance 10 50 ns 78 t sc r sckx output rise time (master mode) ? 25 ns 79 t sc f sckx output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ? 50 ns 83 t sc h2 ss h, t sc l2 ss h ssx after sckx edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi 70 71 72 73 74 75, 76 77 78 79 80 79 78 sdix msb lsb bit 6 - - - - - - 1 msb in bit 6 - - - - 1 lsb in 83 note: refer to figure 27-3 for load conditions. pic18f97j60 family ds39762a-page 440 advance information ? 2006 microchip technology inc. figure 27-15: example spi slave mode timing (cke = 1 ) table 27-19: example spi slave mode requirements (cke = 1 ) param no. symbol characteristic min max units conditions 70 t ss l2 sc h, t ss l2 sc l ssx to sckx or sckx input t cy ?ns 71 t sc h sckx input high time (slave mode) continuous 1.25 t cy + 30 ? ns 71a single byte 40 ? ns (note 1) 72 t sc l sckx input low time (slave mode) continuous 1.25 t cy + 30 ? ns 72a single byte 40 ? ns (note 1) 73a t b 2 b last clock edge of byte 1 to the first clock edge of byte 2 1.5 t cy + 40 ? ns (note 2) 74 t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 100 ? ns 75 t do r sdox data output rise time ? 25 ns 76 t do f sdox data output fall time ? 25 ns 77 t ss h2 do z ssx to sdox output high-impedance 10 50 ns 78 t sc r sckx output rise time (master mode) ? 25 ns 79 t sc f sckx output fall time (master mode) ? 25 ns 80 t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge ? 50 ns 82 t ss l2 do v sdox data output valid after ssx edge ? 50 ns 83 t sc h2 ss h, t sc l2 ss h ssx after sckx edge 1.5 t cy + 40 ? ns note 1: requires the use of parameter #73a. 2: only if parameter #71a and #72a are used. ss x sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdi 70 71 72 82 sdix 74 75, 76 msb bit 6 - - - - - - 1 lsb 77 msb in bit 6 - - - - 1 lsb in 80 83 note: refer to figure 27-3 for load conditions. ? 2006 microchip technology inc. advance information ds39762a-page 441 pic18f97j60 family figure 27-16: i 2 c? bus start/stop bits timing table 27-20: i 2 c? bus start/stop bits requirements (slave mode) figure 27-17: i 2 c? bus data timing note: refer to figure 27-3 for load conditions. 91 92 93 sclx sdax start condition stop condition 90 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 4700 ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? 91 t hd : sta start condition 100 khz mode 4000 ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? 92 t su : sto stop condition 100 khz mode 4700 ? ns setup time 400 khz mode 600 ? 93 t hd : sto stop condition 100 khz mode 4000 ? ns hold time 400 khz mode 600 ? note: refer to figure 27-3 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 sclx sdax in sdax out pic18f97j60 family ds39762a-page 442 advance information ? 2006 microchip technology inc. table 27-21: i 2 c? bus data requirements (slave mode) param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 4.0 ? s pic18f97j60 family must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? s pic18f97j60 family must operate at a minimum of 10 mhz mssp module 1.5 t cy ? 101 t low clock low time 100 khz mode 4.7 ? s pic18f97j60 family must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? s pic18f97j60 family must operate at a minimum of 10 mhz mssp module 1.5 t cy ? 102 t r sdax and sclx rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 103 t f sdax and sclx fall time 100 khz mode ? 300 ns 400 khz mode 20 + 0.1 c b 300 ns c b is specified to be from 10 to 400 pf 90 t su : sta start condition setup time 100 khz mode 4.7 ? s only relevant for repeated start condition 400 khz mode 0.6 ? s 91 t hd : sta start condition hold time 100 khz mode 4.0 ? s after this period, the first clock pulse is generated 400 khz mode 0.6 ? s 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 s 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 92 t su : sto stop condition setup time 100 khz mode 4.7 ? s 400 khz mode 0.6 ? s 109 t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns 110 t buf bus free time 100 khz mode 4.7 ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? s d102 c b bus capacitive loading ? 400 pf note 1: as a transmitter, the device must provi de this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of sclx to avoid unint ended generation of start or stop conditions. 2: a fast mode i 2 c? bus device can be us ed in a standard mode i 2 c bus system, but the requirement, t su : dat 250 ns, must then be met. this will automatically be the case if the device does not stretch the low period of the sclx signal. if such a device does stretch the low period of the sclx si gnal, it must output the next data bit to the sdax line, t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the sclx line is released. ? 2006 microchip technology inc. advance information ds39762a-page 443 pic18f97j60 family figure 27-18: master ssp i 2 c? bus start/stop bits timing waveforms table 27-22: master ssp i 2 c? bus start/stop bits requirements figure 27-19: master ssp i 2 c? bus data timing note: refer to figure 27-3 for load conditions. 91 93 sclx sdax start condition stop condition 90 92 param. no. symbol characteristic min max units conditions 90 t su : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns only relevant for repeated start condition setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 91 t hd : sta start condition 100 khz mode 2(t osc )(brg + 1) ? ns after this period, the first clock pulse is generated hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 92 t su : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns setup time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? 93 t hd : sto stop condition 100 khz mode 2(t osc )(brg + 1) ? ns hold time 400 khz mode 2(t osc )(brg + 1) ? 1 mhz mode (1) 2(t osc )(brg + 1) ? note 1: maximum pin capacitance = 10 pf for all i 2 c? pins. note: refer to figure 27-3 for load conditions. 90 91 92 100 101 103 106 107 109 109 110 102 sclx sdax in sdax out pic18f97j60 family ds39762a-page 444 advance information ? 2006 microchip technology inc. table 27-23: master ssp i 2 c? bus data requirements param. no. symbol characteristic min max units conditions 100 t high clock high time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 101 t low clock low time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 102 t r sdax and sclx rise time 100 khz mode ? 1000 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 300 ns 103 t f sdax and sclx fall time 100 khz mode ? 300 ns c b is specified to be from 10 to 400 pf 400 khz mode 20 + 0.1 c b 300 ns 1 mhz mode (1) ? 100 ns 90 t su : sta start condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms only relevant for repeated start condition 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 91 t hd : sta start condition hold time 100 khz mode 2(t osc )(brg + 1) ? ms after this period, the first clock pulse is generated 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 106 t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ms 1 mhz mode (1) tbd ? ns 107 t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns 1 mhz mode (1) tbd ? ns 92 t su : sto stop condition setup time 100 khz mode 2(t osc )(brg + 1) ? ms 400 khz mode 2(t osc )(brg + 1) ? ms 1 mhz mode (1) 2(t osc )(brg + 1) ? ms 109 t aa output valid from clock 100 khz mode ? 3500 ns 400 khz mode ? 1000 ns 1 mhz mode (1) ??ns 110 t buf bus free time 100 khz mode 4.7 ? ms time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ms 1 mhz mode (1) tbd ? ms d102 c b bus capacitive loading ? 400 pf legend: tbd = to be determined note 1: maximum pin capacitance = 10 pf for all i 2 c? pins. 2: a fast mode i 2 c bus device can be used in a standard mode i 2 c bus system, but parameter #107 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the sclx signal. if such a device does stretch the low period of the sclx signal, it must output the next data bit to the sdax line, parameter #102 + parameter #107 = 1000 + 250 = 1250 ns (for 100 khz mode), before the sclx line is released. ? 2006 microchip technology inc. advance information ds39762a-page 445 pic18f97j60 family figure 27-20: eusart synchronous transmission (master/slave) timing table 27-24: eusart synchronous transmission requirements figure 27-21: eusart synchronous receive (master/slave) timing table 27-25: eusart synchronous receive requirements 121 121 120 122 txx/ckx rxx/dtx pin pin note: refer to figure 27-3 for load conditions. param no. symbol characteristic min max units conditions 120 t ck h2 dt v sync xmit (master and slave) clock high to data out valid ? 40 ns 121 t ckrf clock out rise time and fall time (master mode) ? 20 ns 122 t dtrf data out rise time and fall time ? 20 ns 125 126 txx/ckx rxx/dtx pin pin note: refer to figure 27-3 for load conditions. param. no. symbol characteristic min max units conditions 125 t dt v2 ckl sync rcv (master and slave) data hold before ckx (dtx hold time) 10 ? ns 126 t ck l2 dtl data hold after ckx (dtx hold time) 15 ? ns pic18f97j60 family ds39762a-page 446 advance information ? 2006 microchip technology inc. table 27-26: a/d converter characteristics: pic18f97j60 family (industrial) figure 27-22: a/d conversion timing param no. symbol characteristic min typ max units conditions a01 n r resolution ? ? 10 bit v ref 2.0v a03 e il integral linearity error ? ? <1 lsb v ref 2.0v a04 e dl differential linearity error ? ? <1 lsb v ref 2.0v a06 e off offset error ? ? <3 lsb v ref 2.0v a07 e gn gain error ? ? <3 lsb v ref 2.0v a10 ? monotonicity guaranteed (1) ?v ss v ain v ref a20 v ref reference voltage range (v refh ? v refl ) 1.8 3 ? ? ? ? v v v dd < 3.0v v dd 3.0v v refsum reference voltage sum (v refh + v refl ) ??av dd +0.5 v a21 v refh reference voltage high v refl ?av dd v a22 v refl reference voltage low av ss ?v refh v a25 v ain analog input voltage v refl ?v refh v a30 z ain recommended impedance of analog voltage source ??2.5k a50 i ref v ref input current (2) ? ? ? ? 5 1000 a a during v ain acquisition. during a/d conversion cycle. note 1: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 2: v refh current is from ra3/an3/v ref + pin or av dd , whichever is selected as the v refh source. v refl current is from ra2/an2/v ref - pin or av ss , whichever is selected as the v refl source. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data (note 2) 987 21 0 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 2: this is a minimal rc delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. . . . . . . t cy ? 2006 microchip technology inc. advance information ds39762a-page 447 pic18f97j60 family table 27-27: a/d conversion requirements 27.5 ethernet specifications and requirements table 27-28: requirements for ethernet transceiver external magnetics param no. symbol characteristic min max units conditions 130 t ad a/d clock period 0.7 25.0 (1) st osc based, v ref 2.0v tbd 1 s a/d rc mode 131 t cnv conversion time (not including acquisition time) (note 2) 11 12 t ad 132 t acq acquisition time (note 3) 1.4 tbd ? ? s s -40 c to +85 c 0 c to +85 c 135 t swc switching time from convert sample ? (note 4) tbd t dis discharge time 0.2 ? s legend: tbd = to be determined note 1: the time of the a/d clock period is dependent on the device frequency and the t ad clock divider. 2: adres registers may be read on the following t cy cycle. 3: the time for the holding capacitor to acquire the ?new? input voltage when the voltage changes full scale after the conversion (v dd to v ss or v ss to v dd ). the source impedance ( r s ) on the input channels is 50 . 4: on the following cycle of the device clock. parameter min norm max units conditions rxx turns ratio ? 1:1 ? ? txx turns ratio ? 1:1 ? ? transformer center tap = 3.3v insertion loss 0.0 0.6 1.1 db primary inductance 350 ? ? h8 ma bias transformer isolation ? 1.5 ? kvrms differential to common mode rejection 40 ? ? db 0.1 to 10 mhz return loss -16 ? ? db pic18f97j60 family ds39762a-page 448 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 449 pic18f97j60 family 28.0 dc and ac characteristics graphs and tables graphs and tables are not available at this time. pic18f97j60 family ds39762a-page 450 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 451 pic18f97j60 family 29.0 packaging information 29.1 package marking information 64-lead tqfp xxxxxxxxxx xxxxxxxxxx xxxxxxxxxx yywwnnn example 18f67j60- i/pt 0610017 80-lead tqfp xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic18f87j60- i/pt 0610017 100-lead tqfp xxxxxxxxxxxx xxxxxxxxxxxx yywwnnn example pic18f97j60- i/pf 0610017 legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 3 e 3 e 3 e pic18f97j60 family ds39762a-page 452 advance information ? 2006 microchip technology inc. 29.2 package details the following sections give the technical details of the packages. 64-lead plastic thin-quad flatpack (pt) 10x10x1 mm body, 1.0/0.10 mm lead form (tqfp) 15 10 5 15 10 5 mold draft angle bottom 15 10 5 15 10 5 mold draft angle top 0.27 0.22 0.17 .011 .009 .007 b lead width 0.23 0.18 0.13 .009 .007 .005 c lead thickness 16 16 n1 pins per side 10.10 10.00 9.90 .398 .394 .390 d1 molded package length 10.10 10.00 9.90 .398 .394 .390 e1 molded package width 12.25 12.00 11.75 .482 .472 .463 d overall length 12.25 12.00 11.75 .482 .472 .463 e overall width 7 3.5 0 7 3.5 0 foot angle 0.75 0.60 0.45 .030 .024 .018 l foot length 0.25 0.15 0.05 .010 .006 .002 a1 standoff 1.05 1.00 0.95 .041 .039 .037 a2 molded package thickness 1.20 1.10 1.00 .047 .043 .039 a overall height 0.50 .020 p pitch 64 64 n number of pins max nom min max nom min dimension limits millimeters * inches units footprint f .039 ref. 1.00 ref. pin 1 corner chamfer ch .025 .035 .045 0.64 0.89 1.14 ref: reference dimension, usually without tolerance, for information purposes only. revised 07-22-05 dimensions d and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" (0.254mm) per si de. see asme y14.5m * controlling parameter jedec equivalent: ms-026 notes: c 2 1 n d d1 b p #leads=n1 e1 e a2 a1 a l ch x 45 f drawing no. c04-085 ? 2006 microchip technology inc. advance information ds39762a-page 453 pic18f97j60 family 80-lead plastic thin-quad flatpack (pt) 12x12x1 mm body, 1.0/0.10 mm lead form (tqfp) f e e1 #leads=n1 p b d1 d n 1 2 c l a a1 a2 ch x 45 1.10 1.00 .043 .039 1.14 0.89 0.64 .045 .035 .025 ch pin 1 corner chamfer 1.00 ref. .039 ref. f footprint units inches millimeters * dimension limits min nom max min nom max number of pins n 80 80 pitch p .020 bsc 0.50 bsc overall height a .047 1.20 molded package thickness a2 .037 .039 .041 0.95 1.00 1.05 standoff a1 .002 .004 .006 0.05 0.10 0.15 foot length l .018 .024 .030 0.45 0.60 0.75 foot angle 0 3.5 7 0 3.5 7 overall width e .551 bsc 14.00 bsc overall length d .551 bsc 14.00 bsc molded package width e1 .472 bsc 12.00 bsc molded package length d1 .472 bsc 12.00 bsc pins per side n1 20 20 lead thickness c .004 .006 .008 0.09 0.15 0.20 lead width b .007 .009 .011 0.17 0.22 0.27 mold draft angle top 5 10 15 5 10 15 mold draft angle bottom 5 10 15 5 10 15 notes: jedec equivalent: ms-026 revised 07-22-05 * controlling parameter ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" (0.254mm) per s ide. see asme y14.5m see asme y14.5m drawing no. c04-092 pic18f97j60 family ds39762a-page 454 advance information ? 2006 microchip technology inc. 100-lead plastic thin-quad flatpack (pf) 14x14x1 mm body, 1.0/0.10 mm lead form (tqfp) d d1 e e1 #leads=n1 p b l c 2 n 1 f a a1 a2 dimensions d1 and e1 do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010" (0.254mm) per s ide. .630 bsc nom inches .630 bsc .551 bsc .551 bsc overall width overall length foot angle foot length pins per side overall height number of pins lead width revised 07-21-05 lead thickness molded package thickness * controlling parameter jedec equivalent: ms-026 mold draft angle bottom mold draft angle top molded package width molded package length footprint notes: pitch standoff 11 dimension limits b d1 e1 c d e f l 11 .007 .004 .018 0 min a a1 a2 n1 p units n .037 .002 12 11 12 13 12 .009 3.5 .039 ref .024 .011 .008 13 .030 7 25 .020 bsc .039 100 .041 .006 .047 max 16.00 bsc 16.00 bsc 14.00 bsc 14.00 bsc 0.17 0.09 11 0.45 0 0.22 12 1.00 ref 0.60 3.5 millimeters * 0.95 0.05 min 0.50 bsc 1.00 25 nom 100 13 0.27 0.20 13 0.75 7 1.05 0.15 1.20 max ref: reference dimension, usually without tolerance, for information purposes only. bsc: basic dimension. theoretically exact value shown without tolerances. see asme y14.5m see asme y14.5m drawing no. c04-110 ? 2006 microchip technology inc. advance information ds39762a-page 455 pic18f97j60 family appendix a: revision history revision a (march 2006) original data sheet for the pic18f97j60 family of devices. appendix b: device differences the differences between the devices listed in this data sheet are shown in table b-1. table b-1: device differences between pic18f97j60 family members features pic18f66j60 pic18f66j65 pic18f67j60 PIC18F86J60 pic18f86j65 pic18f87j60 pic18f96j60 pic18f96j65 pic18f97j60 program memory (bytes) 64k 96k 128k 64k 96k 128k 64k 96k 128k program memory (instructions) 32764 49148 65532 32764 49148 65532 32764 49148 65532 interrupt sources 26 27 29 i/o ports (pins) ports a, b, c, d, e, f, g (39) ports a, b, c, d, e, f, g, h, j (55) ports a, b, c, d, e, f, g, h, j (70) enhanced usart modules 1 2 mssp modules 1 2 parallel slave port communications (psp) no yes external memory bus no yes 10-bit analog-to-digital module 11 input channels 15 input channels 16 input channels packages 64-pin tqfp 80-pin tqfp 100-pin tqfp pic18f97j60 family ds39762a-page 456 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 457 pic18f97j60 family index a a/d ................................................................................... 325 a/d converter interrupt, configuring ....................... 329 acquisition requirements ........................................ 330 adcal bit ................................................................ 333 adcon0 register .................................................... 325 adcon1 register .................................................... 325 adcon2 register .................................................... 325 adresh register ............................................ 325, 328 adresl register .................................................... 325 analog port pins, configuring .................................. 331 associated registers ............................................... 333 automatic acquisition time ...................................... 331 calibration ................................................................ 333 configuring the module ............................................ 329 conversion clock (t ad ) ........................................... 331 conversion requirements ....................................... 447 conversion status (go/done bit) .......................... 328 conversions ............................................................. 332 converter characteristics ........................................ 446 operation in power-managed modes ...................... 333 special event trigger (eccp) ......................... 192, 332 use of the eccp2 trigger ....................................... 332 absolute maximum ratings ............................................. 413 ac (timing) characteristics ............................................. 427 load conditions for device timing specifications ................................................... 428 parameter symbology ............................................. 427 temperature and voltage specific ations ................. 428 timing conditions .................................................... 428 access bank mapping with indexed literal offset mode ................. 93 ackstat ........................................................................ 290 ackstat status flag ..................................................... 290 adcal bit ........................................................................ 333 adcon0 register ............................................................ 325 go/done bit ........................................................... 328 adcon1 register ............................................................ 325 adcon2 register ............................................................ 325 addfsr .......................................................................... 402 addlw ............................................................................ 365 addulnk ........................................................................ 402 addwf ............................................................................ 365 addwfc ......................................................................... 366 adresh register ............................................................ 325 adresl register .................................................... 325, 328 affected instructions .......................................................... 91 analog-to-digital converter. see a/d. andlw ............................................................................ 366 andwf ............................................................................ 367 assembler mpasm assembler .................................................. 410 auto-wake-up on sync break character ......................... 316 b baud rate generator ....................................................... 286 bc .................................................................................... 367 bcf .................................................................................. 368 bf .................................................................................... 290 bf status flag ................................................................. 290 block diagrams 16-bit byte select mode .......................................... 111 16-bit byte write mode ............................................ 109 16-bit word write mode .......................................... 110 8-bit multiplexed mode ............................................ 113 a/d ........................................................................... 328 analog input model .................................................. 329 baud rate generator .............................................. 286 capture mode operation ......................................... 183 comparator analog input model .............................. 339 comparator i/o operating modes ........................... 336 comparator output .................................................. 338 comparator voltage reference ............................... 342 comparator voltage reference output buffer example ................................................ 343 compare mode operation ....................................... 184 connections for on-chip voltage regulator ........... 354 device clock .............................................................. 39 enhanced pwm ....................................................... 193 ethernet interrupt logic ........................................... 225 ethernet module ...................................................... 205 eusart receive .................................................... 315 eusart transmit ................................................... 312 external power-on reset circuit (slow v dd power-up) ........................................ 55 fail-safe clock monitor ........................................... 356 generic i/o port operation ...................................... 135 interrupt logic .......................................................... 120 mssp (i 2 c master mode) ........................................ 284 mssp (i 2 c mode) .................................................... 265 mssp (spi mode) ................................................... 255 on-chip reset circuit ................................................ 53 pic18f66j60/66j65/67j60 ....................................... 11 PIC18F86J60/86j65/87j60 ....................................... 12 pic18f96j60/96j65/97j60 ....................................... 13 portd and porte (parallel slave port) ............... 160 pwm operation (simplified) .................................... 186 reads from flash program memory ......................... 99 required external components for ethernet ........... 207 single comparator ................................................... 337 table read operation ............................................... 95 table write operation ............................................... 96 table writes to flash program memory .................. 101 timer0 in 16-bit mode ............................................. 164 timer0 in 8-bit mode ............................................... 164 timer1 ..................................................................... 168 timer1 (16-bit read/write mode) ............................ 168 timer2 ..................................................................... 174 timer3 ..................................................................... 176 timer3 (16-bit read/write mode) ............................ 176 timer4 ..................................................................... 180 watchdog timer ...................................................... 353 bn .................................................................................... 368 bnc ................................................................................. 369 bnn ................................................................................. 369 bnov .............................................................................. 370 bnz ................................................................................. 370 bor. see brown-out reset. bov ................................................................................. 373 bra ................................................................................. 371 break character (12-bit) transmit and receive .............. 318 brg. see baud rate generator. pic18f97j60 family ds39762a-page 458 advance information ? 2006 microchip technology inc. brown-out reset (bor) ..................................................... 55 and on-chip voltage regulator ............................... 354 disabling in sleep mode ............................................ 55 bsf .................................................................................. 371 bsr .................................................................................... 93 btfsc ............................................................................. 372 btfss .............................................................................. 372 btg .................................................................................. 373 bz ..................................................................................... 374 c c compilers mplab c18 ............................................................. 410 mplab c30 ............................................................. 410 calibration (a/d converter) .............................................. 333 call ................................................................................ 374 callw ............................................................................. 403 capture (ccp module) ..................................................... 183 associated registers ............................................... 185 ccp pin configuration ............................................. 183 ccprxh:ccprxl registers ................................... 183 prescaler .................................................................. 183 software interrupt .................................................... 183 timer1/timer3 mode selection ................................ 183 capture (eccp module) .................................................. 192 capture/compare/pwm (ccp) ........................................ 181 capture mode. see capture. ccp mode and timer resources ............................ 182 ccprxh register .................................................... 182 ccprxl register ..................................................... 182 compare mode. see compare. interconnect configurations ..................................... 182 module configuration ............................................... 182 clock sources default system clock on reset ................................. 44 oscillator switching .................................................... 42 clrf ................................................................................ 375 clrwdt .......................................................................... 375 code examples 16 x 16 signed multiply routine .............................. 118 16 x 16 unsigned multiply routine .......................... 118 8 x 8 signed multiply routine .................................. 117 8 x 8 unsigned multiply routine .............................. 117 changing between capture prescalers ................... 183 computed goto using an offset value ................... 73 erasing a flash program memory row ................... 100 fast register stack .................................................... 73 how to clear ram (bank 1) using indirect addressing ............................................ 88 implementing a real-time clock using a timer1 interrupt service ............................... 171 initializing porta .................................................... 136 initializing portb .................................................... 138 initializing portc .................................................... 141 initializing portd .................................................... 144 initializing porte .................................................... 148 initializing portf .................................................... 151 initializing portg ................................................... 153 initializing porth .................................................... 156 initializing portj .................................................... 158 loading the ssp1buf (ssp1sr) register ............. 258 reading a flash program memory word .................. 99 saving status, wreg and bsr registers in ram ............................................. 134 writing to flash program memory ........................... 102 code protection ............................................................... 345 comf .............................................................................. 376 comparator ...................................................................... 335 analog input connection considerations ................ 339 associated registers ............................................... 339 configuration ........................................................... 336 effects of a reset .................................................... 338 interrupts ................................................................. 338 operation ................................................................. 337 operation during sleep ........................................... 338 outputs .................................................................... 337 reference ................................................................ 337 external signal ................................................ 337 internal signal .................................................. 337 response time ........................................................ 337 comparator specifications ............................................... 426 comparator voltage reference ....................................... 341 accuracy and error .................................................. 342 associated registers ............................................... 343 configuring .............................................................. 341 connection considerations ...................................... 342 effects of a reset .................................................... 342 operation during sleep ........................................... 342 compare (ccp module) .................................................. 184 associated registers ............................................... 185 ccp pin configuration ............................................. 184 ccprx register ...................................................... 184 software interrupt .................................................... 184 timer1/timer3 mode selection ................................ 184 compare (eccp module) ................................................ 192 special event trigger .............................. 177, 192, 332 computed goto ............................................................... 73 configuration bits ............................................................ 345 configuration register protection .................................... 358 context saving during interrupts ..................................... 134 core features easy migration ............................................................. 7 expanded memory ....................................................... 7 extended instruction set ............................................. 7 external memory bus .................................................. 7 nanowatt technology .................................................. 7 oscillator options ........................................................ 7 cpfseq .......................................................................... 376 cpfsgt .......................................................................... 377 cpfslt ........................................................................... 377 crystal oscillator/ ceramic resonators (hs modes) ................................................................ 40 customer change notification service ............................ 468 customer notification service ......................................... 468 customer support ............................................................ 468 d data addressing modes .................................................... 88 comparing addressing modes with the extended instruction set enabled ..................... 92 direct ......................................................................... 88 indexed literal offset ................................................ 91 indirect ....................................................................... 88 inherent and literal .................................................... 88 ? 2006 microchip technology inc. advance information ds39762a-page 459 pic18f97j60 family data memory ..................................................................... 76 access bank .............................................................. 78 bank select register (bsr) ....................................... 76 ethernet sfrs ........................................................... 80 extended instruction set ............................................ 90 general purpose register file ................................... 78 map for pic18f97j60 family .................................... 77 special function registers ........................................ 79 daw ................................................................................. 378 dc and ac characteristics graphs and tables .................................................. 449 dc characteristics ........................................................... 423 power-down and supply current ............................ 416 supply voltage ......................................................... 415 dcfsnz .......................................................................... 379 decf ............................................................................... 378 decfsz ........................................................................... 379 default system clock ......................................................... 44 development support ...................................................... 409 device differences ........................................................... 455 device overview .................................................................. 7 details on individual family members ......................... 8 features (100-pin devices) ....................................... 10 features (64-pin devices) ........................................... 9 features (80-pin devices) ........................................... 9 direct addressing ............................................................... 89 e effect on standard pic instructions ................................. 406 effects of power-managed modes on various clock sources ............................................... 44 electrical characteristics .................................................. 413 requirements for ethernet transceiver external magnetics .......................................... 447 enhanced capture/compare/pwm (eccp) .................... 189 associated registers ............................................... 204 capture and compare modes .................................. 192 capture mode. see capture (eccp module). eccp1/eccp3 outputs and program memory mode ................................... 190 eccp2 outputs and program memory modes ........ 190 enhanced pwm mode ............................................. 193 outputs and configuration ....................................... 190 pin configurations for eccp1 ................................. 191 pin configurations for eccp2 ................................. 191 pin configurations for eccp3 ................................. 192 pwm mode. see pwm (eccp module). standard pwm mode ............................................... 192 timer resources ...................................................... 190 use of ccp4/ccp5 with eccp1/eccp3 ................ 190 enhanced universal synchronous asynchronous receiver transmitter (eusart). see eusart. envreg pin .................................................................... 354 equations a/d acquisition time ................................................ 330 a/d minimum charging time ................................... 330 calculating the a/d minimum required acquisition time .............................................. 330 random access address calculation ...................... 239 receive buffer free space calculation ................... 240 errata ................................................................................... 6 ethernet module ............................................................... 205 associated registers, direct memory access controller ............................................. 253 associated registers, flow control ......................... 244 associated registers, reception ............................. 241 associated registers, transmission ....................... 241 buffer and buffer pointers ....................................... 209 buffer organization .................................................. 210 crc ......................................................................... 234 direct memory access controller ............................ 251 checksum calculations ................................... 252 copying memory ............................................. 251 disabling .................................................................. 232 duplex mode configuration ..................................... 242 erevid register ..................................................... 217 ethernet and microcontroller memory relationship ....................................... 208 ethernet control registers ...................................... 211 flow control ............................................................ 243 initializing ................................................................. 231 interrupts ................................................................. 225 led configuration ................................................... 206 mac and mii registers ........................................... 213 magnetics, termination and other external components ...................................... 207 oscillator requirements ........... ............................... 206 packet format ......................................................... 233 per-packet control byte .......................................... 235 phid registers ........................................................ 217 phstat registers .................................................. 217 phy register summary .......................................... 219 phy registers ......................................................... 217 phy start-up timer ................................................. 206 receive filters ......................................................... 245 broadcast ........................................................ 245 hash table ...................................................... 245 magic packet ................................................... 245 multicast .......................................................... 245 pattern match .................................................. 245 unicast ............................................................ 245 resets ..................................................................... 253 power-on reset (por) .................................... 253 receive only ................................................... 253 transmit only .................................................. 253 signal and power interfaces .................................... 206 special function registers (sfrs) ......................... 211 transmitting and receiving data ............................ 233 packet field definitions ........................... 233?234 reading received packets ............................. 239 receive buffer space ...................................... 240 receive packet layout .................................... 238 receive status vectors ................................... 239 receiving packets ........................................... 238 transmit packet layout ................................... 236 transmitting packets ....................................... 235 ethernet operation, microcontroller clock ......................... 41 ethernet special function registers map ............................................................................ 80 eusart asynchronous mode ................................................ 311 12-bit break transmit and receive ................. 318 associated registers, receive ........................ 315 associated registers, transmit ....................... 313 auto-wake-up on sync break ......................... 316 receiver .......................................................... 314 setting up 9-bit mode with address detect ........................................ 314 transmitter ...................................................... 311 baud rate generator operation in power-managed mode ................ 305 pic18f97j60 family ds39762a-page 460 advance information ? 2006 microchip technology inc. baud rate generator (brg) .................................... 305 associated registers ....................................... 306 auto-baud rate detect .................................... 309 baud rate error, calculating ........................... 306 baud rates, asynchronous modes .................. 307 high baud rate select (brgh bit) .................. 305 sampling .......................................................... 305 synchronous master mode ...................................... 319 associated registers, receive ........................ 322 associated registers, transmit ....................... 320 reception ......................................................... 321 transmission .................................................... 319 synchronous slave mode ........................................ 322 associated registers, receive ........................ 324 associated registers, transmit ....................... 323 reception ......................................................... 323 transmission .................................................... 322 extended instruction set addfsr .................................................................. 402 addulnk ................................................................ 402 callw ..................................................................... 403 movsf .................................................................... 403 movss .................................................................... 404 pushl ..................................................................... 404 subfsr .................................................................. 405 subulnk ................................................................ 405 extended microcontroller mode ....................................... 108 external clock input (ec modes) ....................................... 40 external memory bus ....................................................... 105 16-bit byte select mode .......................................... 111 16-bit byte write mode ............................................ 109 16-bit data width modes ......................................... 108 16-bit mode timing .................................................. 112 16-bit word write mode ........................................... 110 21-bit addressing ..................................................... 107 8-bit data width mode ............................................. 113 8-bit mode timing .................................................... 114 address and data line usage (table) ...................... 107 address and data width .......................................... 107 address shifting ....................................................... 107 and program memory modes .................................. 108 control ..................................................................... 106 i/o port functions .................................................... 105 operation in power-managed modes ...................... 115 wait states ............................................................... 108 weak pull-ups on port pins ..................................... 108 f fail-safe clock monitor ............................................ 345, 356 and the watchdog timer .......................................... 356 exiting operation ..................................................... 356 interrupts in power-managed modes ....................... 357 por or wake-up from sleep ................................... 357 fast register stack ............................................................ 73 firmware instructions ....................................................... 359 flash configuration words ......................................... 68, 345 flash program memory ...................................................... 95 associated registers ............................................... 103 control registers ....................................................... 96 eecon1 and eecon2 ..................................... 96 tablat (table latch) register ......................... 98 tblptr (table pointer) register ...................... 98 erase sequence ...................................................... 100 erasing ..................................................................... 100 operation during code-protect ............................... 103 reading ...................................................................... 99 table pointer boundaries based on operation ....................... 98 table pointer boundaries .......................................... 98 table reads and table writes .................................. 95 write sequence ....................................................... 101 writing ..................................................................... 101 protection against spurious writes ................. 103 unexpected termination ................................. 103 write verify ...................................................... 103 fscm. see fail-safe clock monitor. g goto .............................................................................. 380 h hardware multiplier .......................................................... 117 introduction .............................................................. 117 operation ................................................................. 117 performance comparison ........................................ 117 i i/o ports ........................................................................... 135 pin capabilities ........................................................ 135 i 2 c mode (mssp) acknowledge sequence timing .............................. 293 associated registers ............................................... 299 baud rate generator .............................................. 286 bus collision during a repeated start condition .................. 297 during a stop condition .................................. 298 clock arbitration ...................................................... 287 clock rate w/brg ................................................... 286 clock stretching ....................................................... 279 10-bit slave receive mode (sen = 1) ............ 279 10-bit slave transmit mode ............................ 279 7-bit slave receive mode (sen = 1) .............. 279 7-bit slave transmit mode .............................. 279 clock synchronization and the ckp bit ................... 280 effects of a reset .................................................... 294 general call address support ................................. 283 master mode ............................................................ 284 baud rate generator ...................................... 286 operation ......................................................... 285 reception ........................................................ 290 repeated start condition timing .................... 289 start condition timing ..................................... 288 transmission ................................................... 290 multi-master communication, bus collision and arbitration ................................................. 294 multi-master mode ................................................... 294 operation ................................................................. 270 read/write bit information (r/w bit) ............... 270, 272 registers ................................................................. 265 serial clock (sckx/sclx) ....................................... 272 slave mode .............................................................. 270 address masking ............................................. 271 addressing ....................................................... 270 reception ........................................................ 272 transmission ................................................... 272 sleep operation ....................................................... 294 stop condition timing ............................................. 293 incf ................................................................................ 380 incfsz ............................................................................ 381 in-circuit debugger .......................................................... 358 in-circuit serial programming (icsp) ...................... 345, 358 ? 2006 microchip technology inc. advance information ds39762a-page 461 pic18f97j60 family indexed literal offset addressing and standard pic18 instructions ............................. 406 indexed literal offset mode ................................. 91, 93, 406 indirect addressing ............................................................ 89 infsnz ............................................................................ 381 initialization conditions for all registers ...................... 59?65 instruction cycle ................................................................ 74 clocking scheme ....................................................... 74 flow/pipelining ........................................................... 74 instruction set .................................................................. 359 addlw .................................................................... 365 addwf .................................................................... 365 addwf (indexed literal offset mode) .................... 407 addwfc ................................................................. 366 andlw .................................................................... 366 andwf .................................................................... 367 bc ............................................................................ 367 bcf .......................................................................... 368 bn ............................................................................ 368 bnc ......................................................................... 369 bnn ......................................................................... 369 bnov ....................................................................... 370 bnz .......................................................................... 370 bov ......................................................................... 373 bra .......................................................................... 371 bsf .......................................................................... 371 bsf (indexed literal offset mode) .......................... 407 btfsc ..................................................................... 372 btfss ..................................................................... 372 btg .......................................................................... 373 bz ............................................................................ 374 call ........................................................................ 374 clrf ........................................................................ 375 clrwdt .................................................................. 375 comf ...................................................................... 376 cpfseq .................................................................. 376 cpfsgt .................................................................. 377 cpfslt ................................................................... 377 daw ......................................................................... 378 dcfsnz .................................................................. 379 decf ....................................................................... 378 decfsz ................................................................... 379 extended instructions .............................................. 401 considerations when enabling ........................ 406 syntax .............................................................. 401 use with mplab ide tools ............................. 408 general format ........................................................ 361 goto ...................................................................... 380 incf ......................................................................... 380 incfsz .................................................................... 381 infsnz .................................................................... 381 iorlw ..................................................................... 382 iorwf ..................................................................... 382 lfsr ........................................................................ 383 movf ....................................................................... 383 movff .................................................................... 384 movlb .................................................................... 384 movlw ................................................................... 385 movwf ................................................................... 385 mullw .................................................................... 386 mulwf .................................................................... 386 negf ....................................................................... 387 nop ......................................................................... 387 pop ......................................................................... 388 push ....................................................................... 388 rcall ..................................................................... 389 reset ..................................................................... 389 retfie .................................................................... 390 retlw .................................................................... 390 return .................................................................. 391 rlcf ....................................................................... 391 rlncf ..................................................................... 392 rrcf ....................................................................... 392 rrncf .................... ................................................ 393 setf ....................................................................... 393 setf (indexed literal offset mode) ........................ 407 sleep ..................................................................... 394 standard instructions ............................................... 359 subfwb ................................................................. 394 sublw .................................................................... 395 subwf .................................................................... 395 subwfb ................................................................. 396 swapf .................................................................... 396 tblrd ..................................................................... 397 tblwt .................................................................... 398 tstfsz ................................................................... 399 xorlw ................................................................... 399 xorwf ................................................................... 400 intcon register rbif bit ................................................................... 138 intcon registers ........................................................... 121 inter-integrated circuit. see i 2 c mode. internal oscillator block ..................................................... 41 internal rc oscillator use with wdt .......................................................... 353 internal voltage regulator specifications ........................ 426 internet address .............................................................. 468 interrupt sources ............................................................. 345 a/d conversion complete ....................................... 329 capture complete (ccp) ........................................ 183 compare complete (ccp) ...................................... 184 interrupt-on-change (rb7:rb4) .............................. 138 intx pin ................................................................... 134 portb, interrupt-on-change .................................. 134 tmr0 ....................................................................... 134 tmr0 overflow ........................................................ 165 tmr1 overflow ........................................................ 167 tmr2 to pr2 match (pwm) .................................... 193 tmr3 overflow ................................................ 175, 177 tmr4 to pr4 match ................................................ 180 tmr4 to pr4 match (pwm) .................................... 179 interrupts ......................................................................... 119 interrupts, flag bits interrupt-on-change (rb7:rb4) flag (rbif bit) ................................................. 138 intosc, intrc. see internal oscillator block. iorlw ............................................................................. 382 iorwf ............................................................................. 382 ipr registers ................................................................... 130 l lfsr ............................................................................... 383 m master clear (mclr ) ......................................................... 55 master synchronous serial port (mssp). see mssp. memory organization ........................................................ 67 data memory ............................................................. 76 program memory ....................................................... 67 memory programming requirements .............................. 425 microchip internet web site ............................................. 468 pic18f97j60 family ds39762a-page 462 advance information ? 2006 microchip technology inc. microcontroller mode ........................................................ 108 movf ............................................................................... 383 movff ............................................................................. 384 movlb ............................................................................. 384 movlw ............................................................................ 385 movsf ............................................................................ 403 movss ............................................................................ 404 movwf ........................................................................... 385 mplab asm30 assembler, linker, librarian .................. 410 mplab icd 2 in-circuit debugger ................................... 411 mplab ice 2000 high-performance universal in-circuit emulator ................................... 411 mplab ice 4000 high-performance universal in-circuit emulator ................................... 411 mplab integrated development environment software .............................................. 409 mplab pm3 device programmer .................................... 411 mplink object linker/mplib object librarian ............... 410 mssp ack pulse ........................................................ 270, 272 control registers (general) ...................................... 255 module overview ..................................................... 255 spi master/slave connection .................................. 259 sspxbuf register .................................................. 260 sspxsr register ..................................................... 260 tmr4 output for clock ............................................ 180 mullw ............................................................................ 386 mulwf ............................................................................ 386 n negf ............................................................................... 387 nop ................................................................................. 387 o opcode field descriptions ............................................... 360 organizationally unique identifier (oui) .......................... 234 oscillator configuration ...................................................... 39 ec .............................................................................. 39 ecpll ........................................................................ 39 hs .............................................................................. 39 hspll ........................................................................ 39 internal oscillator block ............................................. 41 intrc ........................................................................ 39 oscillator selection .......................................................... 345 oscillator start-up timer (ost) ......................................... 44 oscillator transitions .......................................................... 44 oscillator, timer1 ..................................................... 167, 177 oscillator, timer3 ............................................................. 175 oui. see organizationally unique identifier. p packaging ........................................................................ 451 details ...................................................................... 452 marking .................................................................... 451 parallel slave port (psp) ................................................. 160 associated registers ............................................... 162 portd .................................................................... 160 select (pspmode bit) ............................................ 160 picstart plus development programmer .................... 412 pie registers ................................................................... 127 pin functions av dd .............................................................. 20, 28, 38 av ss .............................................................. 20, 28, 38 envreg ........................................................ 20, 28, 38 mclr ............................................................. 14, 21, 29 osc1/clki .................................................... 14, 21, 29 osc2/clko .................................................. 14, 21, 29 ra0/leda/an0 ............................................. 14, 21, 29 ra1/ledb/an1 ............................................. 14, 21, 29 ra2/an2/v ref - ............................................. 14, 21, 29 ra3/an3/v ref + ............................................ 14, 21, 29 ra4/t0cki .................................................... 14, 21, 29 ra5/an4 ........................................................ 14, 21, 29 rb0/int0/flt0 .............................................. 15, 22, 30 rb1/int1 ....................................................... 15, 22, 30 rb2/int2 ....................................................... 15, 22, 30 rb3/int3 ............................................................. 15, 22 rb3/int3/eccp2/p2a .............................................. 30 rb4/kbi0 ....................................................... 15, 22, 30 rb5/kbi1 ....................................................... 15, 22, 30 rb6/kbi2/pgc .............................................. 15, 22, 30 rb7/kbi3/pgd .............................................. 15, 22, 30 rbias ............................................................ 20, 28, 38 rc0/t1oso/t13cki ..................................... 16, 23, 31 rc1/t1osi/eccp2/p2a ............................... 16, 23, 31 rc2/eccp1/p1a ........................................... 16, 23, 31 rc3/sck1/scl1 ........................................... 16, 23, 31 rc4/sdi1/sda1 ............................................ 16, 23, 31 rc5/sdo1 ..................................................... 16, 23, 31 rc6/tx1/ck1 ................................................ 16, 23, 31 rc7/rx1/dt1 ................................................ 16, 23, 31 rd0 ........................................................................... 24 rd0/ad0/psp0 ......................................................... 32 rd0/p1b .................................................................... 17 rd1 ........................................................................... 24 rd1/ad1/psp1 ......................................................... 32 rd1/eccp3/p3a ....................................................... 17 rd2 ........................................................................... 24 rd2/ad2/psp2 ......................................................... 32 rd2/ccp4/p3d ......................................................... 17 rd3/ad3/psp3 ......................................................... 32 rd4/ad4/psp4/sdo2 ............................................... 32 rd5/ad5/psp5/sdi2/sda2 ...................................... 32 rd6/ad6/psp6/sck2/scl2 ..................................... 32 rd7/ad7/psp7/ss2 .................................................. 32 re0/ad8/rd /p2d ...................................................... 33 re0/p2d .............................................................. 18, 24 re1/ad9/wr /p2c ..................................................... 33 re1/p2c .............................................................. 18, 24 re2/ad10/cs /p2b .................................................... 33 re2/p2b .............................................................. 18, 24 re3/ad11/p3c .......................................................... 33 re3/p3c .............................................................. 18, 24 re4/ad12/p3b .......................................................... 33 re4/p3b .............................................................. 18, 24 re5/ad13/p1c .......................................................... 33 re5/p1c .............................................................. 18, 24 re6/ad14/p1b .......................................................... 33 re6/p1b .................................................................... 24 re7/ad15/eccp2/p2a ............................................. 33 re7/eccp2/p2a ....................................................... 24 rf0/an5 .................................................................... 34 rf1/an6/c2out ........................................... 19, 25, 34 rf2/an7/c1out ........................................... 19, 25, 34 rf3/an8 ........................................................ 19, 25, 34 rf4/an9 ........................................................ 19, 25, 34 rf5/an10/cv ref .......................................... 19, 25, 34 rf6/an11 ...................................................... 19, 25, 34 rf7/ss1 ........................................................ 19, 25, 34 rg0/eccp3/p3a ................................................. 26, 35 rg1/tx2/ck2 ...................................................... 26, 35 ? 2006 microchip technology inc. advance information ds39762a-page 463 pic18f97j60 family rg2/rx2/dt2 ...................................................... 26, 35 rg3/ccp4/p3d ................................................... 26, 35 rg4/ccp5/p1d ............................................. 20, 26, 35 rg5 ............................................................................ 35 rg6 ............................................................................ 35 rg7 ............................................................................ 35 rh0 ............................................................................ 27 rh0/a16 .................................................................... 36 rh1 ............................................................................ 27 rh1/a17 .................................................................... 36 rh2 ............................................................................ 27 rh2/a18 .................................................................... 36 rh3 ............................................................................ 27 rh3/a19 .................................................................... 36 rh4/an12/p3c .................................................... 27, 36 rh5/an13/p3b .................................................... 27, 36 rh6/an14/p1c .................................................... 27, 36 rh7/an15/p1b .................................................... 27, 36 rj0/ale ..................................................................... 37 rj1/oe ...................................................................... 37 rj2/wrl .................................................................... 37 rj3/wrh ................................................................... 37 rj4 ............................................................................. 28 rj4/ba0 ..................................................................... 37 rj5 ............................................................................. 28 rj5/ce ....................................................................... 37 rj6/lb ....................................................................... 37 rj7/ub ....................................................................... 37 tpin- .............................................................. 20, 28, 38 tpin+ ............................................................. 20, 28, 38 tpout- .......................................................... 20, 28, 38 tpout+ ......................................................... 20, 28, 38 v dd ................................................................ 20, 28, 38 v ddcore /v cap ............................................... 20, 28, 38 v ddpll ........................................................... 20, 28, 38 v ddrx ............................................................ 20, 28, 38 v ddtx ............................................................. 20, 28, 38 v ss ................................................................. 20, 28, 38 v sspll ............................................................ 20, 28, 38 v ssrx ............................................................. 20, 28, 38 v sstx ............................................................. 20, 28, 38 pinout i/o descriptions pic18f66j60/66j65/67j60 ....................................... 14 PIC18F86J60/86j65/87j60 ....................................... 21 pic18f96j60/96j65/97j60 ....................................... 29 pir registers ................................................................... 124 pll block ........................................................................... 41 clock speeds for various configurations .................. 42 pop ................................................................................. 388 por. see power-on reset. porta associated registers ............................................... 137 lata register .......................................................... 136 porta register ...................................................... 136 trisa register ........................................................ 136 portb associated registers ............................................... 140 latb register .......................................................... 138 portb register ...................................................... 138 rb7:rb4 interrupt-on-change flag (rbif bit) ......................................................... 138 trisb register ........................................................ 138 portc associated registers ............................................... 143 latc register ......................................................... 141 portc register ...................................................... 141 rc3/sck1/scl1 pin ............................................... 272 trisc register ....................................................... 141 portd associated registers ............................................... 147 latd register ......................................................... 144 portd register ...................................................... 144 trisd register ....................................................... 144 porte associated registers ............................................... 150 late register ......................................................... 148 porte register ...................................................... 148 psp mode select (pspmode bit) .......................... 160 re0/ad8/rd /p2d pin ............................................. 160 re1/ad9/wr /p2c pin ............................................ 160 re2/ad10/cs /p2b pin ............................................ 160 trise register ........................................................ 148 portf associated registers ............................................... 152 latf register ......................................................... 151 portf register ...................................................... 151 trisf register ........................................................ 151 portg associated registers ............................................... 155 latg register ......................................................... 153 portg register ..................................................... 153 trisg register ....................................................... 153 porth associated registers ............................................... 157 lath register ......................................................... 156 porth register ...................................................... 156 trish register ....................................................... 156 portj associated registers ............................................... 159 latj register .......................................................... 158 portj register ...................................................... 158 trisj register ........................................................ 158 power-managed modes ..................................................... 45 and eusart operation .......................................... 305 and spi operation ................................................... 263 clock sources ........................................................... 45 clock transitions and status indicators .................... 46 entering ..................................................................... 45 exiting idle and sleep modes .................................... 51 by interrupt ........................................................ 51 by reset ............................................................ 51 by wdt time-out .............................................. 51 without an oscillator start-up delay ................. 51 idle modes ................................................................. 49 pri_idle .......................................................... 50 rc_idle ........................................................... 51 sec_idle ......................................................... 50 multiple sleep commands ......................................... 46 run modes ................................................................ 46 pri_run ........................................................... 46 rc_run ............................................................ 48 sec_run ......................................................... 46 selecting .................................................................... 45 sleep mode ............................................................... 49 summary (table) ........................................................ 45 pic18f97j60 family ds39762a-page 464 advance information ? 2006 microchip technology inc. power-on reset (por) ...................................................... 55 power-up timer (pwrt) ........................................... 56 time-out sequence .................................................... 56 power-up delays ................................................................ 44 power-up timer (pwrt) .............................................. 44, 56 prescaler timer2 ...................................................................... 194 prescaler, timer0 ............................................................. 165 prescaler, timer2 ............................................................. 187 pri_idle mode ................................................................. 50 pri_run mode ................................................................. 46 program counter ................................................................ 71 pcl, pch and pcu registers ................................... 71 pclath and pclatu registers .............................. 71 program memory extended instruction set ............................................ 90 instructions ................................................................. 75 two-word .......................................................... 75 interrupt vector .......................................................... 68 look-up tables .......................................................... 73 maps program memory modes ................................... 70 memory maps ............................................................ 67 hard vectors and configuration words ............. 68 modes ........................................................................ 69 address shifting (extended microcontroller) ......................... 70 extended microcontroller ................................... 69 memory access (table) ...................................... 70 microcontroller ................................................... 69 reset vector .............................................................. 68 program memory modes operation of the external memory bus .................... 108 program verification and code protection ....................... 358 programming, device instructions ................................... 359 psp. see parallel slave port. pulse-width modulation. see pwm (ccp module) and pwm (eccp module). push ............................................................................... 388 push and pop instructions .............................................. 72 pushl ............................................................................. 404 pwm (ccp module) associated registers ............................................... 188 duty cycle ................................................................ 186 example frequencies/resolutions .......................... 187 operation setup ....................................................... 187 period ....................................................................... 186 tmr2 to pr2 match ................................................ 193 tmr4 to pr4 match ................................................ 179 pwm (eccp module) ...................................................... 193 ccpr1h:ccpr1l registers ................................... 193 direction change in full-bridge output mode .................................................... 198 duty cycle ................................................................ 194 effects of a reset ..................................................... 203 enhanced pwm auto-shutdown ............................. 200 example frequencies/resolutions .......................... 194 full-bridge application example .............................. 198 full-bridge mode ...................................................... 197 half-bridge mode ..................................................... 196 half-bridge output mode applications example ...... 196 output configurations .............................................. 194 output relationships (active-high) .......................... 195 output relationships (active-low) ........................... 195 period ....................................................................... 193 programmable dead-band delay ............................ 200 setup for pwm operation ........................................ 203 start-up considerations ........................................... 201 q q clock .................................................................... 187, 194 r ram. see data memory. rc_idle mode .................................................................. 51 rc_run mode .................................................................. 48 rcall ............................................................................. 389 rcon register bit status during initialization .................................... 58 reader response ............................................................ 469 receive filters and logic flow ....................................................... 248 magic packet format ............................................... 250 or logic flow ......................................................... 247 pattern match filter format ..................................... 249 register file summary ................................................ 81?86 registers adcon0 (a/d control 0) ......................................... 325 adcon1 (a/d control 1) ......................................... 326 adcon2 (a/d control 2) ......................................... 327 baudconx (baud rate control) ............................ 304 ccpxcon (capture/compare/pwm control, ccp4 and ccp5) ............................................ 181 ccpxcon (enhanced capture/compare/pwm control, eccp1/eccp2/eccp3) .................... 189 cmcon (comparator control) ................................ 335 config1h (configuration 1 high) .......................... 347 config1l (configuration 1 low) ........................... 347 config2h (configuration 2 high) .......................... 349 config2l (configuration 2 low) ........................... 348 config3h (configuration 3 high) .......................... 351 config3l (configuration 3 low) ..................... 69, 350 cvrcon (comparator voltage reference control) .......................................... 341 devid1 (device id 1) .............................................. 352 devid2 (device id 2) .............................................. 352 eccpxas (eccpx auto-shutdown configuration) .................................................. 201 eccpxdel (eccpx dead-band delay) ................. 200 econ1 (ethernet control 1) .................................... 211 econ2 (ethernet control 2) .................................... 212 eecon1 (eeprom control 1) ................................. 97 eflocon (ethernet flow control) ......................... 244 eie (ethernet interrupt enable) ............................... 226 eir (ethernet interrupt request, flag) .................... 227 erxfcon (ethernet receive filter control) ........... 246 estat (ethernet status) ......................................... 212 intcon (interrupt control) ...................................... 121 intcon2 (interrupt control 2) ................................. 122 intcon3 (interrupt control 3) ................................. 123 ipr1 (peripheral interrupt priority 1) ....................... 130 ipr2 (peripheral interrupt priority 2) ....................... 131 ipr3 (peripheral interrupt priority 3) ....................... 132 mabbipg (mac back-to-back inter-packet gap) ............................................ 232 macon1 (mac control 1) ...................................... 213 macon3 (mac control 3) ...................................... 214 macon4 (mac control 4) ...................................... 215 memcon (external memory bus control) .............. 106 micmd (mii command) ........................................... 216 micon (mii control) ................................................ 215 2006 microchip technology inc. advance information ds39762a-page 465 pic18f97j60 family mistat (mii status) ................................................ 216 osccon (oscillator control) .................................... 43 osctune (pll block control) ................................. 41 phcon1 (phy control 1) ........................................ 220 phcon2 (phy control 2) ........................................ 222 phie (phy interrupt enable) ................................... 228 phir (phy interrupt request, flag) ........................ 228 phlcon (phy module led control) ...................... 224 phstat1 (physical layer status 1) ........................ 221 phstat2 (physical layer status 2) ........................ 223 pie1 (peripheral interrupt enable 1) ........................ 127 pie2 (peripheral interrupt enable 2) ........................ 128 pie3 (peripheral interrupt enable 3) ........................ 129 pir1 (peripheral interrupt request (flag) 1) ........... 124 pir2 (peripheral interrupt request (flag) 2) ........... 125 pir3 (peripheral interrupt request (flag) 3) ........... 126 pspcon (parallel slave port control) .................... 161 rcon (reset control) ....................................... 54, 133 rcstax (receive status and control) .................... 303 sspxcon1 (msspx control 1, i 2 c mode) .............. 267 sspxcon1 (msspx control 1, spi mode) ............. 257 sspxcon2 (msspx control 2, i 2 c master mode) ................................................... 268 sspxcon2 (msspx control 2, i 2 c slave mode) ..................................................... 269 sspxstat (msspx status, i 2 c mode) ................... 266 sspxstat (msspx status, spi mode) .................. 256 status ..................................................................... 87 stkptr (stack pointer) ............................................ 72 t0con (timer0 control) .......................................... 163 t1con (timer1 control) .......................................... 167 t2con (timer2 control) .......................................... 173 t3con (timer3 control) .......................................... 175 t4con (timer4 control) .......................................... 179 txstax (transmit status and control) ................... 302 wdtcon (watchdog timer control) ...................... 353 reset ............................................................................. 389 reset .................................................................................. 53 brown-out reset (bor) ............................................. 53 mclr reset, during power-managed modes ........... 53 mclr reset, normal operation ................................ 53 power-on reset (por) .............................................. 53 stack full reset ......................................................... 53 stack underflow reset .............................................. 53 state of registers ...................................................... 58 watchdog timer (wdt) reset ................................... 53 resets .............................................................................. 345 brown-out reset (bor) ........................................... 345 oscillator start-up timer (ost) ............................... 345 power-on reset (por) ............................................ 345 power-up timer (pwrt) ......................................... 345 retfie ............................................................................ 390 retlw ............................................................................ 390 return .......................................................................... 391 return address stack ........................................................ 71 return stack pointer (stkptr) ........................................ 72 revision history ............................................................... 455 rlcf ................................................................................ 391 rlncf ............................................................................. 392 rrcf ............................................................................... 392 rrncf ........................ .................................................... 393 s sckx ............................................................................... 255 sdix ................................................................................. 255 sdox ............................................................................... 255 sec_idle mode ............................................................... 50 sec_run mode ................................................................ 46 serial clock, sckx .......................................................... 255 serial data in (sdix) ........................................................ 255 serial data out (sdox) ................................................... 255 serial peripheral interface. see spi mode. setf ............................................................................... 393 slave select (ssx ) ........................................................... 255 sleep ............................................................................. 394 sleep osc1 and osc2 pin states ...................................... 44 software simulator (mplab sim) ................................... 410 special event trigger. see compare (eccp module). special features of the cpu ........................................... 345 special function registers ................................................ 79 ethernet sfrs ........................................................... 80 map ............................................................................ 79 spi mode (mssp) associated registers ............................................... 264 bus mode compatibility ........................................... 263 clock speed and module interactions ..................... 263 effects of a reset .................................................... 263 enabling spi i/o ...................................................... 259 master mode ............................................................ 260 master/slave connection ........................................ 259 operation ................................................................. 258 operation in power-managed modes ...................... 263 serial clock ............................................................. 255 serial data in ........................................................... 255 serial data out ........................................................ 255 slave mode .............................................................. 261 slave select ............................................................. 255 slave select synchronization .................................. 261 spi clock ................................................................. 260 typical connection .................................................. 259 sspov ............................................................................ 290 sspov status flag ......................................................... 290 sspstat register r/w bit .................................................................... 272 sspxstat register r/w bit .................................................................... 270 ssx .................................................................................. 255 stack full/underflow resets .............................................. 73 subfsr .......................................................................... 405 subfwb ......................................................................... 394 sublw ............................................................................ 395 subulnk ........................................................................ 405 subwf ............................................................................ 395 subwfb ......................................................................... 396 swapf ............................................................................ 396 t table pointer operations (table) ........................................ 98 table reads/table writes ................................................. 73 tblrd ............................................................................. 397 tblwt ............................................................................ 398 pic18f97j60 family ds39762a-page 466 advance information ? 2006 microchip technology inc. timer0 .............................................................................. 163 associated registers ............................................... 165 operation ................................................................. 164 overflow interrupt .................................................... 165 prescaler .................................................................. 165 prescaler assignment (psa bit) .............................. 165 prescaler select (t0ps2:t0ps0 bits) ..................... 165 prescaler. see prescaler, timer0. reads and writes in 16-bit mode ............................ 164 source edge select (t0se bit) ................................ 164 source select (t0cs bit) ......................................... 164 switching prescaler assignment .............................. 165 timer1 .............................................................................. 167 16-bit read/write mode ........................................... 169 associated registers ............................................... 171 interrupt .................................................................... 170 operation ................................................................. 168 oscillator .......................................................... 167, 169 layout considerations ..................................... 170 overflow interrupt .................................................... 167 resetting, using the eccp special event trigger ....................................... 170 special event trigger (eccp) ................................. 192 tmr1h register ...................................................... 167 tmr1l register ....................................................... 167 use as a clock source ............................................ 169 use as a real-time clock ....................................... 170 timer2 .............................................................................. 173 associated registers ............................................... 174 interrupt .................................................................... 174 operation ................................................................. 173 output ...................................................................... 174 pr2 register .................................................... 186, 193 tmr2 to pr2 match interrupt .................................. 193 timer3 .............................................................................. 175 16-bit read/write mode ........................................... 177 associated registers ............................................... 177 operation ................................................................. 176 oscillator .......................................................... 175, 177 overflow interrupt ............................................ 175, 177 special event trigger (eccp) ................................. 177 tmr3h register ...................................................... 175 tmr3l register ....................................................... 175 timer4 .............................................................................. 179 associated registers ............................................... 180 mssp clock ............................................................. 180 operation ................................................................. 179 postscaler. see postscaler, timer4. pr4 register .................................................... 179, 186 prescaler. see prescaler, timer4. tmr4 register ......................................................... 179 tmr4 to pr4 match interrupt .......................... 179, 180 timing diagrams a/d conversion ........................................................ 446 asynchronous reception, rxdtp = 0 (rxx not inverted) ........................................... 315 asynchronous transmission (back-to-back), txckp = 0 (txx not inverted) ........................ 312 asynchronous transmission, txckp = 0 (txx not inverted) ............................................ 312 automatic baud rate calculation ............................ 310 auto-wake-up bit (wue) during normal operation ............................................. 317 auto-wake-up bit (wue) during sleep ................... 317 baud rate generator with clock arbitration ............ 287 brg overflow sequence ......................................... 310 brg reset due to sdax arbitration during start condition ..................................... 296 brown-out reset (bor) ........................................... 434 capture/compare/pwm (including eccp modules) ............................................... 436 clko and i/o .......................................................... 431 clock synchronization ............................................. 280 clock/instruction cycle .............................................. 74 eusart synchronous receive (master/slave) ...... 445 eusart synchronous transmission (master/slave) ................................................. 445 example spi master mode (cke = 0) ..................... 437 example spi master mode (cke = 1) ..................... 438 example spi slave mode (cke = 0) ....................... 439 example spi slave mode (cke = 1) ....................... 440 external clock (all modes except pll) ................... 429 external memory bus for sleep (extended microcontroller mode) .............................. 112, 114 external memory bus for tblrd (extended microcontroller mode) .............................. 112, 114 fail-safe clock monitor ........................................... 357 first start bit ............................................................ 288 full-bridge pwm output .......................................... 197 half-bridge pwm output ......................................... 196 i 2 c acknowledge sequence .................................... 293 i 2 c bus collision during a repeated start condition (case 1) .................................. 297 i 2 c bus collision during a repeated start condition (case 2) .................................. 297 i 2 c bus collision during a stop condition (case 1) ........................................... 298 i 2 c bus collision during a stop condition (case 2) ........................................... 298 i 2 c bus collision during start condition (sclx = 0) ....................................... 296 i 2 c bus collision during start condition (sdax only) .................................... 295 i 2 c bus collision for transmit and acknowledge ................................................... 294 i 2 c bus data ............................................................ 441 i 2 c bus start/stop bits ............................................ 441 i 2 c master mode (7 or 10-bit transmission) ........... 291 i 2 c master mode (7-bit reception) .......................... 292 i 2 c slave mode (10-bit recepti on, sen = 0) .......... 276 i 2 c slave mode (10-bit reception, sen = 0, admsk = 01001) ............................. 277 i 2 c slave mode (10-bit recepti on, sen = 1) .......... 282 i 2 c slave mode (10-bit transmission) .................... 278 i 2 c slave mode (7-bit reception, sen = 0) ............ 273 i 2 c slave mode (7-bit reception, sen = 0, admsk = 01011) ............................................ 274 i 2 c slave mode (7-bit reception, sen = 1) ............ 281 i 2 c slave mode (7-bit transmission) ...................... 275 i 2 c slave mode general call address sequence (7 or 10-bit address mode) ............................. 283 i 2 c stop condition receive or transmit mode ........ 293 master ssp i 2 c bus data ........................................ 443 master ssp i 2 c bus start/stop bits ........................ 443 parallel slave port (psp) read ............................... 162 parallel slave port (psp) write ............................... 161 program memory read ........................................... 432 program memory write ............................................ 433 pwm auto-shutdown (p1rsen = 0, auto-restart disabled) .................................... 202 pwm auto-shutdown (p1rsen = 1, auto-restart enabled) ..................................... 202 ? 2006 microchip technology inc. advance information ds39762a-page 467 pic18f97j60 family pwm direction change ........................................... 199 pwm direction change at near 100% duty cycle ....................................................... 199 pwm output ............................................................ 186 repeated start condition ......................................... 289 reset, watchdog timer (wdt), oscillator start-up timer (ost) and power-up timer (pwrt) .......................................................................... 434 send break character sequence ............................ 318 slave synchronization ............................................. 261 slow rise time (mclr tied to v dd , v dd rise > t pwrt ) ............................................ 57 spi mode (master mode) ......................................... 260 spi mode (slave mode, cke = 0) ........................... 262 spi mode (slave mode, cke = 1) ........................... 262 synchronous reception (master mode, sren) ...... 321 synchronous transmission ...................................... 319 synchronous transmission (through txen) .......... 320 time-out sequence on power-up (mclr not tied to v dd ), case 1 ....................... 56 time-out sequence on power-up (mclr not tied to v dd ), case 2 ....................... 57 time-out sequence on power-up (mclr tied to v dd , v dd rise tpwrt) ................ 56 timer0 and timer1 external clock .......................... 435 transition for entry to idle mode ................................ 50 transition for entry to sec_run mode .................... 47 transition for entry to sleep mode ............................ 49 transition for two-speed start-up (intrc to hspll) ........................................... 355 transition for wake from idle to run mode .............. 50 transition for wake from sleep mode (hspll) ....... 49 transition from rc_run mode to pri_run mode ................................................. 48 transition from sec_run mode to pri_run mode (hspll) .................................. 47 transition to rc_run mode ..................................... 48 timing diagrams and specifications ac characteristics internal rc accuracy ....................................... 430 capture/compare/pwm requirements (including eccp modules) .............................. 436 clko and i/o requirements ........................... 431, 432 eusart synchronous receive requirements .................................................. 445 eusart synchronous transmission requirements .................................................. 445 example spi mode requirements (master mode, cke = 0) .................................. 437 example spi mode requirements (master mode, cke = 1) .................................. 438 example spi mode requirements (slave mode, cke = 0) .................................... 439 example spi slave mode requirements (cke = 1) .................................. 440 external clock requirements .................................. 429 i 2 c bus data requirements (slave mode) ................................................... 442 i 2 c bus start/stop bits requirements (slave mode) ................................................... 441 master ssp i 2 c bus data requirements ................ 444 master ssp i 2 c bus start/stop bits requirements .................................................. 443 parallel slave port requirements ............................ 436 pll clock ................................................................ 430 program memory write requirements .................... 433 reset, watchdog timer, oscillator start-up timer, power-up timer and brown-out reset requirements ........................................ 434 timer0 and timer1 external clock requirements .................................................. 435 top-of-stack access .......................................................... 71 transmitting packets status vectors ......................................................... 237 trise register pspmode bit ......................................................... 160 tstfsz ........................................................................... 399 two-speed start-up ................................................. 345, 355 two-word instructions example cases ......................................................... 75 txstax register brgh bit ................................................................. 305 v v ddcore /v cap pin .......................................................... 354 voltage reference specifications .................................... 426 voltage regulator (on-chip) ........................................... 354 w watchdog timer (wdt) ........................................... 345, 353 associated registers ............................................... 353 control register ....................................................... 353 programming considerations .................................. 353 wcol ...................................................... 288, 289, 290, 293 wcol status flag ................................... 288, 289, 290, 293 www address ................................................................ 468 www, on-line support ................... ................................... 6 x xorlw ........................................................................... 399 xorwf ........................................................................... 400 pic18f97j60 family ds39762a-page 468 advance information ? 2006 microchip technology inc. notes: ? 2006 microchip technology inc. advance information ds39762a-page 469 pic18f97j60 family the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com pic18f97j60 family ds39762a-page 470 advance information ? 2006 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds39762a pic18f97j60 family 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2006 microchip technology inc. advance information ds39762a-page 471 pic18f97j60 family product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device pic18f66j60/66j65/67j60, PIC18F86J60/86j65/87j60, pic18f96j60/96j65/97j60, pic18f66j60/66j65/67j60t (1) , PIC18F86J60/86j65/87j60t (1) , pic18f96j60/96j65/97j60t (1) ; temperature range i = -40 c to +85 c (industrial) package pt = 64 and 80-lead tqfp (thin quad flatpack) pf = 100-lead tqfp (thin quad flatpack) pattern qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic18f67j60-i/pt 301 = industrial temp., tqfp package, qtp pattern #301. b) pic18f67j60t-i/pt = tape and reel, industrial temp., tqfp package. note 1: t = in tape and reel ds39762a-page 472 advance information ? 2006 microchip technology inc. americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://support.microchip.com web address: www.microchip.com atlanta alpharetta, ga tel: 770-640-0034 fax: 770-640-0307 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit farmington hills, mi tel: 248-538-2250 fax: 248-538-2260 kokomo kokomo, in tel: 765-864-8360 fax: 765-864-8387 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 san jose mountain view, ca tel: 650-215-1444 fax: 650-961-0286 toronto mississauga, ontario, canada tel: 905-673-0699 fax: 905-673-6509 asia/pacific australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8528-2100 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8676-6200 fax: 86-28-8676-6599 china - fuzhou tel: 86-591-8750-3506 fax: 86-591-8750-3521 china - hong kong sar tel: 852-2401-1200 fax: 852-2401-3431 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8203-2660 fax: 86-755-8203-1760 china - shunde tel: 86-757-2839-5507 fax: 86-757-2839-5571 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7250 fax: 86-29-8833-7256 asia/pacific india - bangalore tel: 91-80-4182-8400 fax: 91-80-4182-8422 india - new delhi tel: 91-11-5160-8631 fax: 91-11-5160-8632 india - pune tel: 91-20-2566-1512 fax: 91-20-2566-1513 japan - yokohama tel: 81-45-471- 6166 fax: 81-45-471-6122 korea - gumi tel: 82-54-473-4301 fax: 82-54-473-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - penang tel: 60-4-646-8870 fax: 60-4-646-5086 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-572-9526 fax: 886-3-572-6459 taiwan - kaohsiung tel: 886-7-536-4818 fax: 886-7-536-4803 taiwan - taipei tel: 886-2-2500-6610 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-399 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 uk - wokingham tel: 44-118-921-5869 fax: 44-118-921-5820 w orldwide s ales and s ervice 02/16/06 |
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